From nobody Sun Feb 8 19:56:01 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1621489548; cv=none; d=zohomail.com; s=zohoarc; b=hZ/RBEe6GDL8PlX/V4X9+IpKYdg5vgXIsRndce9Fat2CjN89RVu5Kig9dy0QrgB6hdTJMOYlC64gmXGMkUcinbCMbT7N3cDT6Du7y0Nl+IBfX0PgU1FaQf7wmSuhvHiC1TQoMUABvtIZbWU9N/qo3NwMDt6tNkVQErP8cPj1eAM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1621489548; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=c4rQYXYRpb8EfVUS1hNYxi6hnO91IC4G11/XlTb8qVM=; b=IYnR8Jh9QH4+xhYy7sbD3QP3ZCPRx445eBZJZuYpQ4T9jr/Uhgi4PM8QzgMZiEpkYI/sWLXfZcjCvtnr/MwjC2usqcPR9C6iHOssVAE4Dv4h3n2RZq12O7SExNmce8PUk8UPQR97TdXCUqp9cO7d2mRYqSuVIUHwO31ytrSqr8w= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1621489548930276.22196860879376; Wed, 19 May 2021 22:45:48 -0700 (PDT) Received: from localhost ([::1]:53358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ljbVD-0007je-Qk for importer@patchew.org; Thu, 20 May 2021 01:45:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60686) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTE-00055R-Af for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:44 -0400 Received: from mga06.intel.com ([134.134.136.31]:7415) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ljbTB-00077a-3L for qemu-devel@nongnu.org; Thu, 20 May 2021 01:43:44 -0400 Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2021 22:43:38 -0700 Received: from michael-optiplex-9020.sh.intel.com ([10.239.159.172]) by fmsmga008.fm.intel.com with ESMTP; 19 May 2021 22:43:36 -0700 IronPort-SDR: koB/Bo5SQBLg3kGrUP5a6vm4HnQJFzzjOpgHwZcO9oLyxfV2wnIi2CGT6q2DigH76AIc+vPWvH KtD9QU5CIqTg== X-IronPort-AV: E=McAfee;i="6200,9189,9989"; a="262370935" X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="262370935" IronPort-SDR: X046M9kit6O+KxosRLzmdIpqGw7kIR0IPI+3yCpsCuxmdVSCNn2vqSQLT3FBAhMFdV/cbZvV/v V2jOpawWE8tQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,313,1613462400"; d="scan'208";a="440160296" From: Yang Weijiang To: pbonzini@redhat.com, ehabkost@redhat.com, mtosatti@redhat.com, seanjc@google.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, kvm@vger.kernel.org Subject: [PATCH v8 2/6] target/i386: Enable XSS feature CPUID enumeration Date: Thu, 20 May 2021 13:57:07 +0800 Message-Id: <1621490231-4765-3-git-send-email-weijiang.yang@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> References: <1621490231-4765-1-git-send-email-weijiang.yang@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=134.134.136.31; envelope-from=weijiang.yang@intel.com; helo=mga06.intel.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yang Weijiang Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Currently, CPUID.(EAX=3D0DH,ECX=3D01H) doesn't enumerate features in XSS properly, so enable the support. XCR0 bits indicate user-mode XSAVE components, and XSS bits indicate supervisor-mode XSAVE components. Signed-off-by: Yang Weijiang --- target/i386/cpu.c | 68 +++++++++++++++++++++++++++++++++++++++-------- target/i386/cpu.h | 9 +++++++ 2 files changed, 66 insertions(+), 11 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5c76186883..d74d68e319 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1062,6 +1062,24 @@ static FeatureWordInfo feature_word_info[FEATURE_WOR= DS] =3D { }, .tcg_features =3D TCG_XSAVE_FEATURES, }, + [FEAT_XSAVE_XSS_LO] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_ECX, + }, + }, + [FEAT_XSAVE_XSS_HI] =3D { + .type =3D CPUID_FEATURE_WORD, + .cpuid =3D { + .eax =3D 0xD, + .needs_ecx =3D true, + .ecx =3D 1, + .reg =3D R_EDX + }, + }, [FEAT_6_EAX] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { @@ -1453,6 +1471,9 @@ typedef struct ExtSaveArea { uint32_t offset, size; } ExtSaveArea; =20 +/* CPUID feature bits available in XSS */ +#define CPUID_XSTATE_XSS_MASK 0 + static const ExtSaveArea x86_ext_save_areas[] =3D { [XSTATE_FP_BIT] =3D { /* x87 FP state component is always enabled if XSAVE is supported = */ @@ -1498,15 +1519,18 @@ static const ExtSaveArea x86_ext_save_areas[] =3D { .size =3D sizeof(XSavePKRU) }, }; =20 -static uint32_t xsave_area_size(uint64_t mask) +static uint32_t xsave_area_size(uint64_t mask, bool compacted) { + uint64_t ret =3D x86_ext_save_areas[0].size; + const ExtSaveArea *esa; + uint32_t offset =3D 0; int i; - uint64_t ret =3D 0; =20 - for (i =3D 0; i < ARRAY_SIZE(x86_ext_save_areas); i++) { - const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + for (i =3D 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { + esa =3D &x86_ext_save_areas[i]; if ((mask >> i) & 1) { - ret =3D MAX(ret, esa->offset + esa->size); + offset =3D compacted ? ret : esa->offset; + ret =3D MAX(ret, offset + esa->size); } } return ret; @@ -1517,7 +1541,7 @@ static inline bool accel_uses_host_cpuid(void) return kvm_enabled() || hvf_enabled(); } =20 -static inline uint64_t x86_cpu_xsave_components(X86CPU *cpu) +static inline uint64_t x86_cpu_xsave_xcr0_components(X86CPU *cpu) { return ((uint64_t)cpu->env.features[FEAT_XSAVE_XCR0_HI]) << 32 | cpu->env.features[FEAT_XSAVE_XCR0_LO]; @@ -1532,6 +1556,12 @@ static const char *get_register_name_32(unsigned int= reg) return x86_reg_info_32[reg].name; } =20 +static inline uint64_t x86_cpu_xsave_xss_components(X86CPU *cpu) +{ + return ((uint64_t)cpu->env.features[FEAT_XSAVE_XSS_HI]) << 32 | + cpu->env.features[FEAT_XSAVE_XSS_LO]; +} + /* * Returns the set of feature flags that are supported and migratable by * QEMU, for a given FeatureWord. @@ -5859,7 +5889,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, } =20 if (count =3D=3D 0) { - *ecx =3D xsave_area_size(x86_cpu_xsave_components(cpu)); + *ecx =3D xsave_area_size(x86_cpu_xsave_xcr0_components(cpu), f= alse); *eax =3D env->features[FEAT_XSAVE_XCR0_LO]; *edx =3D env->features[FEAT_XSAVE_XCR0_HI]; /* @@ -5868,14 +5898,25 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, * even through guest update xcr0, this will crash some legacy= guest * (e.g., CentOS 6), So set ebx =3D=3D ecx to workaroud it. */ - *ebx =3D kvm_enabled() ? *ecx : xsave_area_size(env->xcr0); + *ebx =3D kvm_enabled() ? *ecx : xsave_area_size(env->xcr0, fal= se); } else if (count =3D=3D 1) { + uint64_t xstate =3D x86_cpu_xsave_xcr0_components(cpu) | + x86_cpu_xsave_xss_components(cpu); + *eax =3D env->features[FEAT_XSAVE]; + *ebx =3D xsave_area_size(xstate, true); + *ecx =3D env->features[FEAT_XSAVE_XSS_LO]; + *edx =3D env->features[FEAT_XSAVE_XSS_HI]; } else if (count < ARRAY_SIZE(x86_ext_save_areas)) { - if ((x86_cpu_xsave_components(cpu) >> count) & 1) { - const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; + const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; + + if ((x86_cpu_xsave_xcr0_components(cpu) >> count) & 1) { *eax =3D esa->size; *ebx =3D esa->offset; + } else if ((x86_cpu_xsave_xss_components(cpu) >> count) & 1) { + *eax =3D esa->size; + *ebx =3D 0; + *ecx =3D 1; } } break; @@ -6206,6 +6247,9 @@ static void x86_cpu_reset(DeviceState *dev) } for (i =3D 2; i < ARRAY_SIZE(x86_ext_save_areas); i++) { const ExtSaveArea *esa =3D &x86_ext_save_areas[i]; + if (!((1 << i) & CPUID_XSTATE_XCR0_MASK)) { + continue; + } if (env->features[esa->feature] & esa->bits) { xcr0 |=3D 1ull << i; } @@ -6444,8 +6488,10 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) } } =20 - env->features[FEAT_XSAVE_XCR0_LO] =3D mask; + env->features[FEAT_XSAVE_XCR0_LO] =3D mask & CPUID_XSTATE_XCR0_MASK; env->features[FEAT_XSAVE_XCR0_HI] =3D mask >> 32; + env->features[FEAT_XSAVE_XSS_LO] =3D mask & CPUID_XSTATE_XSS_MASK; + env->features[FEAT_XSAVE_XSS_HI] =3D mask >> 32; } =20 /***** Steps involved on loading and filtering CPUID data diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 84cb6adcaa..42f835d455 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -503,6 +503,13 @@ typedef enum X86Seg { #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) =20 +/* CPUID feature bits available in XCR0 */ +#define CPUID_XSTATE_XCR0_MASK (XSTATE_FP_MASK | XSTATE_SSE_MASK | \ + XSTATE_YMM_MASK | XSTATE_BNDREGS_MASK | \ + XSTATE_BNDCSR_MASK | XSTATE_OPMASK_MASK |= \ + XSTATE_ZMM_Hi256_MASK | \ + XSTATE_Hi16_ZMM_MASK | XSTATE_PKRU_MASK) + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ @@ -541,6 +548,8 @@ typedef enum FeatureWord { FEAT_VMX_BASIC, FEAT_VMX_VMFUNC, FEAT_14_0_ECX, + FEAT_XSAVE_XSS_LO, /* CPUID[EAX=3D0xd,ECX=3D1].ECX */ + FEAT_XSAVE_XSS_HI, /* CPUID[EAX=3D0xd,ECX=3D1].EDX */ FEATURE_WORDS, } FeatureWord; =20 --=20 2.26.2