From nobody Mon Feb 9 16:34:49 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992776; cv=none; d=zohomail.com; s=zohoarc; b=Vyp8RJT3GD1kCujMEZ45v9Nu8M7pyiiBmNM7tfvE1vBhx3vdPO85lzOtJZK/574LMHrqsx2J6vvQ3n3wRFmMnB+4oIIw7Cxonvzm6VdAGulA8eHh0TwEH+5CO4No5MQnDnjAWGsXvW3El+vCCzC1CJCpsWdQo/QGfnLIjg1zNA0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618992776; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/d9ql4/ir7AEinx6yTaAPh0N8pN01/i4UYlUS9IIE5c=; b=cdu2l/LYFhEmVOKDjWQOzWCnF/7Yl0QZV62rupDvV96hxZw1ETDha93ZRdCSe6V43YAALFsjQClJg52y3YQ4IxlUvz6QAQhNFDtOCx+Rl9qTN+eeUldRrWZtoUeoxbNTp6/Q+1UxuuYvjziMv/eoExuHZEjIeDMHTxjb/6cffwk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618992776287127.05629672306395; Wed, 21 Apr 2021 01:12:56 -0700 (PDT) Received: from localhost ([::1]:59252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZ7yg-0001uv-4Y for importer@patchew.org; Wed, 21 Apr 2021 04:12:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51930) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rc-0001Ct-E2; Wed, 21 Apr 2021 04:05:36 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5037) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rZ-00023u-V6; Wed, 21 Apr 2021 04:05:36 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FQCjW4m1pzlYc2; Wed, 21 Apr 2021 16:03:27 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:17 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 6/8] hw/arm/virt-acpi-build: Add explicit IORT idmap for smmuv3 node Date: Wed, 21 Apr 2021 08:05:01 +0000 Message-ID: <1618992303-19556-7-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangxingang5@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang This add explicit IORT idmap info according to pci root bus number range, and only add smmu idmap for those which does not bypass iommu. For idmap directly to ITS node, this split the whole RID mapping to smmu idmap and its idmap. So this should cover the whole idmap for through/bypass SMMUv3 node. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/arm/virt-acpi-build.c | 128 +++++++++++++++++++++++++++++++++------ 1 file changed, 109 insertions(+), 19 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 60fe2e65a7..661b84edec 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -44,6 +44,7 @@ #include "hw/acpi/tpm.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/arm/virt.h" #include "hw/mem/nvdimm.h" @@ -237,6 +238,41 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineS= tate *vms) aml_append(scope, dev); } =20 +/* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ +static int +iort_host_bridges(Object *obj, void *opaque) +{ + GArray *idmap_blob =3D opaque; + + if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + PCIBus *bus =3D PCI_HOST_BRIDGE(obj)->bus; + + if (bus && !pci_bus_bypass_iommu(bus)) { + int min_bus, max_bus; + pci_bus_range(bus, &min_bus, &max_bus); + + AcpiIortIdMapping idmap =3D { + .input_base =3D cpu_to_le32(min_bus << 8), + .id_count =3D cpu_to_le32((max_bus - min_bus + 1) << 8), + .output_base =3D cpu_to_le32(min_bus << 8), + .output_reference =3D cpu_to_le32(0), + .flags =3D cpu_to_le32(0), + }; + g_array_append_val(idmap_blob, idmap); + } + } + + return 0; +} + +static int smmu_idmap_sort_func(gconstpointer a, gconstpointer b) +{ + AcpiIortIdMapping *idmap_a =3D (AcpiIortIdMapping *)a; + AcpiIortIdMapping *idmap_b =3D (AcpiIortIdMapping *)b; + + return idmap_a->input_base - idmap_b->input_base; +} + static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { @@ -247,6 +283,45 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) AcpiIortSmmu3 *smmu; size_t node_size, iort_node_offset, iort_length, smmu_offset =3D 0; AcpiIortRC *rc; + uint32_t base, i, rc_map_count; + GArray *smmu_idmap_blob =3D + g_array_new(false, true, sizeof(AcpiIortIdMapping)); + GArray *its_idmap_blob =3D + g_array_new(false, true, sizeof(AcpiIortIdMapping)); + + object_child_foreach_recursive(object_get_root(), + iort_host_bridges, smmu_idmap_blob); + + g_array_sort(smmu_idmap_blob, smmu_idmap_sort_func); + + /* Build the iort ID mapping to ITS directly */ + i =3D 0, base =3D 0; + while (base < 0xFFFF && i <=3D smmu_idmap_blob->len) { + AcpiIortIdMapping new_idmap =3D { + .input_base =3D cpu_to_le32(base), + .id_count =3D cpu_to_le32(0), + .output_base =3D cpu_to_le32(base), + .output_reference =3D cpu_to_le32(0), + .flags =3D cpu_to_le32(0), + }; + + if (i =3D=3D smmu_idmap_blob->len) { + if (base < 0xFFFF) { + new_idmap.id_count =3D cpu_to_le32(0xFFFF - base); + g_array_append_val(its_idmap_blob, new_idmap); + } + break; + } + + idmap =3D &g_array_index(smmu_idmap_blob, AcpiIortIdMapping, i); + if (base < idmap->input_base) { + new_idmap.id_count =3D cpu_to_le32(idmap->input_base - base); + g_array_append_val(its_idmap_blob, new_idmap); + } + + i++; + base =3D idmap->input_base + idmap->id_count; + } =20 iort =3D acpi_data_push(table_data, sizeof(*iort)); =20 @@ -280,13 +355,13 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) =20 /* SMMUv3 node */ smmu_offset =3D iort_node_offset + node_size; - node_size =3D sizeof(*smmu) + sizeof(*idmap); + node_size =3D sizeof(*smmu) + sizeof(*idmap) * smmu_idmap_blob->le= n; iort_length +=3D node_size; smmu =3D acpi_data_push(table_data, node_size); =20 smmu->type =3D ACPI_IORT_NODE_SMMU_V3; smmu->length =3D cpu_to_le16(node_size); - smmu->mapping_count =3D cpu_to_le32(1); + smmu->mapping_count =3D cpu_to_le32(smmu_idmap_blob->len); smmu->mapping_offset =3D cpu_to_le32(sizeof(*smmu)); smmu->base_address =3D cpu_to_le64(vms->memmap[VIRT_SMMU].base); smmu->flags =3D cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); @@ -295,23 +370,24 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) smmu->sync_gsiv =3D cpu_to_le32(irq + 2); smmu->gerr_gsiv =3D cpu_to_le32(irq + 3); =20 - /* Identity RID mapping covering the whole input RID range */ - idmap =3D &smmu->id_mapping_array[0]; - idmap->input_base =3D 0; - idmap->id_count =3D cpu_to_le32(0xFFFF); - idmap->output_base =3D 0; - /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference =3D cpu_to_le32(iort_node_offset); + for (i =3D 0; i < smmu_idmap_blob->len; i++) { + idmap =3D &smmu->id_mapping_array[i]; + *idmap =3D g_array_index(smmu_idmap_blob, AcpiIortIdMapping, i= ); + /* output IORT node is the ITS group node (the first node) */ + idmap->output_reference =3D cpu_to_le32(iort_node_offset); + } } =20 /* Root Complex Node */ - node_size =3D sizeof(*rc) + sizeof(*idmap); + rc_map_count =3D (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) ? + smmu_idmap_blob->len + its_idmap_blob->len : 1; + node_size =3D sizeof(*rc) + sizeof(*idmap) * rc_map_count; iort_length +=3D node_size; rc =3D acpi_data_push(table_data, node_size); =20 rc->type =3D ACPI_IORT_NODE_PCI_ROOT_COMPLEX; rc->length =3D cpu_to_le16(node_size); - rc->mapping_count =3D cpu_to_le32(1); + rc->mapping_count =3D cpu_to_le32(rc_map_count); rc->mapping_offset =3D cpu_to_le32(sizeof(*rc)); =20 /* fully coherent device */ @@ -319,20 +395,34 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) rc->memory_properties.memory_flags =3D 0x3; /* CCA =3D CPM =3D DCAS = =3D 1 */ rc->pci_segment_number =3D 0; /* MCFG pci_segment */ =20 - /* Identity RID mapping covering the whole input RID range */ - idmap =3D &rc->id_mapping_array[0]; - idmap->input_base =3D 0; - idmap->id_count =3D cpu_to_le32(0xFFFF); - idmap->output_base =3D 0; - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - /* output IORT node is the smmuv3 node */ - idmap->output_reference =3D cpu_to_le32(smmu_offset); + for (i =3D 0; i < rc_map_count; i++) { + idmap =3D &rc->id_mapping_array[i]; + + if (i < smmu_idmap_blob->len) { + *idmap =3D g_array_index(smmu_idmap_blob, AcpiIortIdMappin= g, i); + /* output IORT node is the smmuv3 node */ + idmap->output_reference =3D cpu_to_le32(smmu_offset); + } else { + *idmap =3D g_array_index(its_idmap_blob, + AcpiIortIdMapping, i - smmu_idmap_blob->len); + /* output IORT node is the ITS group node (the first node)= */ + idmap->output_reference =3D cpu_to_le32(iort_node_offset); + } + } } else { + /* Identity RID mapping covering the whole input RID range */ + idmap =3D &rc->id_mapping_array[0]; + idmap->input_base =3D cpu_to_le32(0); + idmap->id_count =3D cpu_to_le32(0xFFFF); + idmap->output_base =3D cpu_to_le32(0); /* output IORT node is the ITS group node (the first node) */ idmap->output_reference =3D cpu_to_le32(iort_node_offset); } =20 + g_array_free(smmu_idmap_blob, true); + g_array_free(its_idmap_blob, true); + /* * Update the pointer address in case table_data->data moves during ab= ove * acpi_data_push operations. --=20 2.19.1