From nobody Mon Feb 9 01:34:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992448; cv=none; d=zohomail.com; s=zohoarc; b=KUf/WjD3oY+sDlU3MXzAUUZcENnF/1kgKZihA5ciXT+taBW1Fn08YD+XAJa2YS5EcgVwS3lrVbXe5Ky7xQv9vHR+/KeeSZes3i1aljKcsxokiBOWsII65bkOXWawBLsYBGalotZY5O8JxHiIiaUq4VJqDuVzNNcLVpnNaPbdHqk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618992448; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SwGuPGkovXpkgJZ/lKT+UV2C720S44Dfgq7rt43w9mI=; b=QZw5ZnbVrOWU3GwErD4xW7EOZs7jSBObPSmVBnQucQ7AiXFKRFLzXw8SqSXaU++xppJOhqo0FBurTAjLVx+z047W3cygg3QWv2GCpeCQeuxA4b/+7rDcxO7bwNGTD/TiFEiN4VDgDMufhHmWb/KoRf0kSTECVrfZIg95TEO4fF0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618992448231721.9495952482145; Wed, 21 Apr 2021 01:07:28 -0700 (PDT) Received: from localhost ([::1]:41242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZ7tO-0002vv-6V for importer@patchew.org; Wed, 21 Apr 2021 04:07:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51876) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rZ-00018a-Pq; Wed, 21 Apr 2021 04:05:33 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:4460) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rW-0001xu-QX; Wed, 21 Apr 2021 04:05:33 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FQChB2Z4xzPrbG; Wed, 21 Apr 2021 16:02:18 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:13 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 1/8] hw/pci/pci_host: Allow bypass iommu for pci host Date: Wed, 21 Apr 2021 08:04:56 +0000 Message-ID: <1618992303-19556-2-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=wangxingang5@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang This add a bypass_iommu property for pci host, which indicates whether devices attached to the pci root bus will bypass iommu. In pci_device_iommu_address_space(), add a bypass_iommu check to avoid getting iommu address space for devices bypass iommu. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/pci/pci.c | 18 +++++++++++++++++- hw/pci/pci_host.c | 2 ++ include/hw/pci/pci.h | 1 + include/hw/pci/pci_host.h | 1 + 4 files changed, 21 insertions(+), 1 deletion(-) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 8f35e13a0c..301addfb35 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -417,6 +417,22 @@ const char *pci_root_bus_path(PCIDevice *dev) return rootbus->qbus.name; } =20 +bool pci_bus_bypass_iommu(PCIBus *bus) +{ + PCIBus *rootbus =3D bus; + PCIHostState *host_bridge; + + if (!pci_bus_is_root(bus)) { + rootbus =3D pci_device_root_bus(bus->parent_dev); + } + + host_bridge =3D PCI_HOST_BRIDGE(rootbus->qbus.parent); + + assert(host_bridge->bus =3D=3D rootbus); + + return host_bridge->bypass_iommu; +} + static void pci_root_bus_init(PCIBus *bus, DeviceState *parent, MemoryRegion *address_space_mem, MemoryRegion *address_space_io, @@ -2719,7 +2735,7 @@ AddressSpace *pci_device_iommu_address_space(PCIDevic= e *dev) =20 iommu_bus =3D parent_bus; } - if (iommu_bus && iommu_bus->iommu_fn) { + if (!pci_bus_bypass_iommu(bus) && iommu_bus && iommu_bus->iommu_fn) { return iommu_bus->iommu_fn(bus, iommu_bus->iommu_opaque, devfn); } return &address_space_memory; diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 8ca5fadcbd..2768db53e6 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -222,6 +222,8 @@ const VMStateDescription vmstate_pcihost =3D { static Property pci_host_properties_common[] =3D { DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, mig_enabled, true), + DEFINE_PROP_BOOL("pci-host-bypass-iommu", PCIHostState, + bypass_iommu, false), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 6be4e0c460..f4d51b672b 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -480,6 +480,7 @@ void pci_for_each_bus(PCIBus *bus, =20 PCIBus *pci_device_root_bus(const PCIDevice *d); const char *pci_root_bus_path(PCIDevice *dev); +bool pci_bus_bypass_iommu(PCIBus *bus); PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn); int pci_qdev_find_device(const char *id, PCIDevice **pdev); void pci_bus_get_w64_range(PCIBus *bus, Range *range); diff --git a/include/hw/pci/pci_host.h b/include/hw/pci/pci_host.h index 52e038c019..c6f4eb4585 100644 --- a/include/hw/pci/pci_host.h +++ b/include/hw/pci/pci_host.h @@ -43,6 +43,7 @@ struct PCIHostState { uint32_t config_reg; bool mig_enabled; PCIBus *bus; + bool bypass_iommu; =20 QLIST_ENTRY(PCIHostState) next; }; --=20 2.19.1 From nobody Mon Feb 9 01:34:33 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992657; cv=none; d=zohomail.com; s=zohoarc; b=Lb6I/M0Djs9rPzk/NhwXDCEGKBohzvuoRuzUEQe/9YGY0zC7ue5qbQeGD1cUNOuqLqR93qLzOJW6APnyIxciXLHN4og1zh37zGCRhWO1l4HzjEF9NfZms7Mm45esXzZkSkwGdvjJc5pnf2y9eTt7ME6Lztm+tJpXwiYyxWQNVGY= ARC-Message-Signature: i=1; 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Wed, 21 Apr 2021 04:10:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51948) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7re-0001JC-U1; Wed, 21 Apr 2021 04:05:38 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5041) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rd-0002CI-4P; Wed, 21 Apr 2021 04:05:38 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FQCjW6LXtzlYrY; Wed, 21 Apr 2021 16:03:27 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:14 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 2/8] hw/pxb: Add a bypass iommu property Date: Wed, 21 Apr 2021 08:04:57 +0000 Message-ID: <1618992303-19556-3-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangxingang5@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang This add a bypass_iommu property for pci_expander_bridge. The property can be used as: qemu -device pxb-pcie,bus_nr=3D0x10,addr=3D0x1,bypass_iommu=3Dtrue Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/pci-bridge/pci_expander_bridge.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expand= er_bridge.c index aedded1064..7112dc3062 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -57,6 +57,7 @@ struct PXBDev { =20 uint8_t bus_nr; uint16_t numa_node; + bool bypass_iommu; }; =20 static PXBDev *convert_to_pxb(PCIDevice *dev) @@ -255,6 +256,7 @@ static void pxb_dev_realize_common(PCIDevice *dev, bool= pcie, Error **errp) bus->map_irq =3D pxb_map_irq_fn; =20 PCI_HOST_BRIDGE(ds)->bus =3D bus; + PCI_HOST_BRIDGE(ds)->bypass_iommu =3D pxb->bypass_iommu; =20 pxb_register_bus(dev, bus, &local_err); if (local_err) { @@ -301,6 +303,7 @@ static Property pxb_dev_properties[] =3D { /* Note: 0 is not a legal PXB bus number. */ DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNE= D), + DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.19.1 From nobody Mon Feb 9 01:34:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992513; cv=none; d=zohomail.com; s=zohoarc; b=c3i3V2RMeYNIKu3MN5zfVTJshmLt2sxEoiRunrnr+VSh3r8RY4SM+iQmNLjwvPyTKnhyTXz9FJe8Dhl88xnGFCGUY6v7X+O3Fsivu37zlUfbDqlw61slnuaZ0j5DhARmUuVsY3NWdEx/KfFwaknPpG8KrmAjZIC5WgRHHsnNvUA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618992513; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bU5zFh8iYCtm8oAbkYXkcwL8KEeFb8OxsuUOIuTgYrI=; b=Bq3ej17FNqfKIYMa9ICPiModfEiNwm+t5lpC6fMI3qFX6ZKKYFEvm8zMB0oxXSwzZuTk7zgXyYLoh/UAGXuQPxZCFftMsv2yVtjnGnhdaWhpjB7xjGR9aCcxsmG4ndnEM4fsj0RCSufNWmQi1xoYeYONj0DNuDpfTb11+i0HHVE= ARC-Authentication-Results: i=1; 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Wed, 21 Apr 2021 16:03:27 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:15 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 3/8] hw/arm/virt: Add a machine option to bypass iommu for primary bus Date: Wed, 21 Apr 2021 08:04:58 +0000 Message-ID: <1618992303-19556-4-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangxingang5@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang This add a bypass_iommu option for arm virt machine, the option can be used in this manner: qemu -machine virt,iommu=3Dsmmuv3,bypass_iommu=3Dtrue Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/arm/virt.c | 26 ++++++++++++++++++++++++++ include/hw/arm/virt.h | 1 + 2 files changed, 27 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9f01d9041b..0ce6167aab 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1366,6 +1366,7 @@ static void create_pcie(VirtMachineState *vms) } =20 pci =3D PCI_HOST_BRIDGE(dev); + pci->bypass_iommu =3D vms->bypass_iommu; vms->bus =3D pci->bus; if (vms->bus) { for (i =3D 0; i < nb_nics; i++) { @@ -2319,6 +2320,21 @@ static void virt_set_iommu(Object *obj, const char *= value, Error **errp) } } =20 +static bool virt_get_bypass_iommu(Object *obj, Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + return vms->bypass_iommu; +} + +static void virt_set_bypass_iommu(Object *obj, bool value, + Error **errp) +{ + VirtMachineState *vms =3D VIRT_MACHINE(obj); + + vms->bypass_iommu =3D value; +} + static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) { @@ -2656,6 +2672,13 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) "Set the IOMMU type. " "Valid values are none and smmuv= 3"); =20 + object_class_property_add_bool(oc, "bypass_iommu", + virt_get_bypass_iommu, + virt_set_bypass_iommu); + object_class_property_set_description(oc, "bypass_iommu", + "Set on/off to enable/disable " + "bypass_iommu for primary bus"); + object_class_property_add_bool(oc, "ras", virt_get_ras, virt_set_ras); object_class_property_set_description(oc, "ras", @@ -2723,6 +2746,9 @@ static void virt_instance_init(Object *obj) /* Default disallows iommu instantiation */ vms->iommu =3D VIRT_IOMMU_NONE; =20 + /* The primary bus is attached to iommu by default */ + vms->bypass_iommu =3D false; + /* Default disallows RAS instantiation */ vms->ras =3D false; =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 921416f918..82bceadb82 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -147,6 +147,7 @@ struct VirtMachineState { OnOffAuto acpi; VirtGICType gic_version; VirtIOMMUType iommu; + bool bypass_iommu; VirtMSIControllerType msi_controller; uint16_t virtio_iommu_bdf; struct arm_boot_info bootinfo; --=20 2.19.1 From nobody Mon Feb 9 01:34:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992450; cv=none; d=zohomail.com; s=zohoarc; b=ilwQqTPqLUOuCczUu9w3c+NImaBBwO3c5EASs4ljF1sH2X4TdmHwraOpKrFxhoLd+QwNH4x/C/eI3lN57kPJXXCNQOxIH4/DQpJjH7Sea1CnJZLkNUYsItYyQS7zjur3FumcN3yFOxSpeRzWsT2lIsONdsJ1rgu1aRr/HA7fD08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618992450; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/mlzMGtkdW1GqGXMfhDUlb0+RTtoXhrl6eTWG3a1r+I=; b=HdAo3uBEyd4qD+zS6O4v374Hd9xmQCZeCbyyIQljjK2SizGD8VBlczt47d1JtdrBRKfhbmeBlkiU+nr0kYQVdOU8sxBttUc46OM1yc6qlPjIKLzobMYkSY4l8mN8dxQl/JjFJqbmNod2wfZ7OQzvqaHVDZWsj1hJBRvTrfdTkqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1618992450166172.72438268991573; Wed, 21 Apr 2021 01:07:30 -0700 (PDT) Received: from localhost ([::1]:41476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lZ7tR-00031y-17 for importer@patchew.org; Wed, 21 Apr 2021 04:07:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51928) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rc-0001Bu-4j; Wed, 21 Apr 2021 04:05:36 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5039) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rZ-00023x-Tp; Wed, 21 Apr 2021 04:05:35 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FQCjW5fmTzlYqR; Wed, 21 Apr 2021 16:03:27 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:15 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 4/8] hw/i386: Add a pc machine option to bypass iommu for primary bus Date: Wed, 21 Apr 2021 08:04:59 +0000 Message-ID: <1618992303-19556-5-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangxingang5@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang Add a bypass_iommu pc machine option to bypass iommu translation for the primary root bus. The option can be used as manner: qemu-system-x86_64 -machine q35,bypass_iommu=3Dtrue Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/i386/pc.c | 18 ++++++++++++++++++ hw/pci-host/q35.c | 1 + include/hw/i386/pc.h | 1 + 3 files changed, 20 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 8a84b25a03..2266a0520f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1529,6 +1529,20 @@ static void pc_machine_set_hpet(Object *obj, bool va= lue, Error **errp) pcms->hpet_enabled =3D value; } =20 +static bool pc_machine_get_bypass_iommu(Object *obj, Error **errp) +{ + PCMachineState *pcms =3D PC_MACHINE(obj); + + return pcms->bypass_iommu; +} + +static void pc_machine_set_bypass_iommu(Object *obj, bool value, Error **e= rrp) +{ + PCMachineState *pcms =3D PC_MACHINE(obj); + + pcms->bypass_iommu =3D value; +} + static void pc_machine_get_max_ram_below_4g(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) @@ -1628,6 +1642,7 @@ static void pc_machine_initfn(Object *obj) #ifdef CONFIG_HPET pcms->hpet_enabled =3D true; #endif + pcms->bypass_iommu =3D false; =20 pc_system_flash_create(pcms); pcms->pcspk =3D isa_new(TYPE_PC_SPEAKER); @@ -1752,6 +1767,9 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) object_class_property_add_bool(oc, "hpet", pc_machine_get_hpet, pc_machine_set_hpet); =20 + object_class_property_add_bool(oc, "bypass_iommu", + pc_machine_get_bypass_iommu, pc_machine_set_bypass_iommu); + object_class_property_add(oc, PC_MACHINE_MAX_FW_SIZE, "size", pc_machine_get_max_fw_size, pc_machine_set_max_fw_size, NULL, NULL); diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 2eb729dff5..ade05a5539 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -64,6 +64,7 @@ static void q35_host_realize(DeviceState *dev, Error **er= rp) s->mch.address_space_io, 0, TYPE_PCIE_BUS); PC_MACHINE(qdev_get_machine())->bus =3D pci->bus; + pci->bypass_iommu =3D PC_MACHINE(qdev_get_machine())->bypass_iommu; qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); } =20 diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index dcf060b791..83ee8f2a01 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -45,6 +45,7 @@ typedef struct PCMachineState { bool sata_enabled; bool pit_enabled; bool hpet_enabled; + bool bypass_iommu; uint64_t max_fw_size; =20 /* NUMA information: */ --=20 2.19.1 From nobody Mon Feb 9 01:34:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992712; cv=none; d=zohomail.com; s=zohoarc; b=dWrcHjRhvcFReqJgSDk0GkMuZoOdo7EuYsMgD2Io5Am9fMgqnwzI52YmNMC1zI1k73uKMgDNUbl0bPHu8BD2UkKUrk5YSd/sXWUp1aNAgxotlGHUjIrWzDqJk2WPLdMMkn9RVIvlm5U9GC20Ck+FuUswaWlv/vzgVUm05rSgs9g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618992712; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Ikvs8YNGqDGi/pJ6zE/dzsCCbjU5EwI3Ytn9W38XtEU=; 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Wed, 21 Apr 2021 04:05:34 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FQCjW61nrzlYrH; Wed, 21 Apr 2021 16:03:27 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:16 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 5/8] hw/pci: Add pci_bus_range to get bus number range Date: Wed, 21 Apr 2021 08:05:00 +0000 Message-ID: <1618992303-19556-6-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangxingang5@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang This helps to get the bus number range of a pci bridge hierarchy. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/pci/pci.c | 15 +++++++++++++++ include/hw/pci/pci.h | 1 + 2 files changed, 16 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 301addfb35..2ac3b8d76c 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -538,6 +538,21 @@ int pci_bus_num(PCIBus *s) return PCI_BUS_GET_CLASS(s)->bus_num(s); } =20 +void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus) +{ + int i; + *min_bus =3D *max_bus =3D pci_bus_num(bus); + + for (i =3D 0; i < ARRAY_SIZE(bus->devices); ++i) { + PCIDevice *dev =3D bus->devices[i]; + + if (dev && PCI_DEVICE_GET_CLASS(dev)->is_bridge) { + *min_bus =3D MIN(*min_bus, dev->config[PCI_SECONDARY_BUS]); + *max_bus =3D MAX(*max_bus, dev->config[PCI_SUBORDINATE_BUS]); + } + } +} + int pci_bus_numa_node(PCIBus *bus) { return PCI_BUS_GET_CLASS(bus)->numa_node(bus); diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index f4d51b672b..d0f4266e37 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -450,6 +450,7 @@ static inline PCIBus *pci_get_bus(const PCIDevice *dev) return PCI_BUS(qdev_get_parent_bus(DEVICE(dev))); } int pci_bus_num(PCIBus *s); +void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus); static inline int pci_dev_bus_num(const PCIDevice *dev) { return pci_bus_num(pci_get_bus(dev)); --=20 2.19.1 From nobody Mon Feb 9 01:34:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992776; cv=none; d=zohomail.com; s=zohoarc; b=Vyp8RJT3GD1kCujMEZ45v9Nu8M7pyiiBmNM7tfvE1vBhx3vdPO85lzOtJZK/574LMHrqsx2J6vvQ3n3wRFmMnB+4oIIw7Cxonvzm6VdAGulA8eHh0TwEH+5CO4No5MQnDnjAWGsXvW3El+vCCzC1CJCpsWdQo/QGfnLIjg1zNA0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1618992776; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Wed, 21 Apr 2021 04:05:36 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:5037) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rZ-00023u-V6; Wed, 21 Apr 2021 04:05:36 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.60]) by szxga06-in.huawei.com (SkyGuard) with ESMTP id 4FQCjW4m1pzlYc2; Wed, 21 Apr 2021 16:03:27 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:17 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 6/8] hw/arm/virt-acpi-build: Add explicit IORT idmap for smmuv3 node Date: Wed, 21 Apr 2021 08:05:01 +0000 Message-ID: <1618992303-19556-7-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangxingang5@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang This add explicit IORT idmap info according to pci root bus number range, and only add smmu idmap for those which does not bypass iommu. For idmap directly to ITS node, this split the whole RID mapping to smmu idmap and its idmap. So this should cover the whole idmap for through/bypass SMMUv3 node. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/arm/virt-acpi-build.c | 128 +++++++++++++++++++++++++++++++++------ 1 file changed, 109 insertions(+), 19 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 60fe2e65a7..661b84edec 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -44,6 +44,7 @@ #include "hw/acpi/tpm.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" +#include "hw/pci/pci_bus.h" #include "hw/pci-host/gpex.h" #include "hw/arm/virt.h" #include "hw/mem/nvdimm.h" @@ -237,6 +238,41 @@ static void acpi_dsdt_add_tpm(Aml *scope, VirtMachineS= tate *vms) aml_append(scope, dev); } =20 +/* Build the iort ID mapping to SMMUv3 for a given PCI host bridge */ +static int +iort_host_bridges(Object *obj, void *opaque) +{ + GArray *idmap_blob =3D opaque; + + if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + PCIBus *bus =3D PCI_HOST_BRIDGE(obj)->bus; + + if (bus && !pci_bus_bypass_iommu(bus)) { + int min_bus, max_bus; + pci_bus_range(bus, &min_bus, &max_bus); + + AcpiIortIdMapping idmap =3D { + .input_base =3D cpu_to_le32(min_bus << 8), + .id_count =3D cpu_to_le32((max_bus - min_bus + 1) << 8), + .output_base =3D cpu_to_le32(min_bus << 8), + .output_reference =3D cpu_to_le32(0), + .flags =3D cpu_to_le32(0), + }; + g_array_append_val(idmap_blob, idmap); + } + } + + return 0; +} + +static int smmu_idmap_sort_func(gconstpointer a, gconstpointer b) +{ + AcpiIortIdMapping *idmap_a =3D (AcpiIortIdMapping *)a; + AcpiIortIdMapping *idmap_b =3D (AcpiIortIdMapping *)b; + + return idmap_a->input_base - idmap_b->input_base; +} + static void build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { @@ -247,6 +283,45 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vir= tMachineState *vms) AcpiIortSmmu3 *smmu; size_t node_size, iort_node_offset, iort_length, smmu_offset =3D 0; AcpiIortRC *rc; + uint32_t base, i, rc_map_count; + GArray *smmu_idmap_blob =3D + g_array_new(false, true, sizeof(AcpiIortIdMapping)); + GArray *its_idmap_blob =3D + g_array_new(false, true, sizeof(AcpiIortIdMapping)); + + object_child_foreach_recursive(object_get_root(), + iort_host_bridges, smmu_idmap_blob); + + g_array_sort(smmu_idmap_blob, smmu_idmap_sort_func); + + /* Build the iort ID mapping to ITS directly */ + i =3D 0, base =3D 0; + while (base < 0xFFFF && i <=3D smmu_idmap_blob->len) { + AcpiIortIdMapping new_idmap =3D { + .input_base =3D cpu_to_le32(base), + .id_count =3D cpu_to_le32(0), + .output_base =3D cpu_to_le32(base), + .output_reference =3D cpu_to_le32(0), + .flags =3D cpu_to_le32(0), + }; + + if (i =3D=3D smmu_idmap_blob->len) { + if (base < 0xFFFF) { + new_idmap.id_count =3D cpu_to_le32(0xFFFF - base); + g_array_append_val(its_idmap_blob, new_idmap); + } + break; + } + + idmap =3D &g_array_index(smmu_idmap_blob, AcpiIortIdMapping, i); + if (base < idmap->input_base) { + new_idmap.id_count =3D cpu_to_le32(idmap->input_base - base); + g_array_append_val(its_idmap_blob, new_idmap); + } + + i++; + base =3D idmap->input_base + idmap->id_count; + } =20 iort =3D acpi_data_push(table_data, sizeof(*iort)); =20 @@ -280,13 +355,13 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) =20 /* SMMUv3 node */ smmu_offset =3D iort_node_offset + node_size; - node_size =3D sizeof(*smmu) + sizeof(*idmap); + node_size =3D sizeof(*smmu) + sizeof(*idmap) * smmu_idmap_blob->le= n; iort_length +=3D node_size; smmu =3D acpi_data_push(table_data, node_size); =20 smmu->type =3D ACPI_IORT_NODE_SMMU_V3; smmu->length =3D cpu_to_le16(node_size); - smmu->mapping_count =3D cpu_to_le32(1); + smmu->mapping_count =3D cpu_to_le32(smmu_idmap_blob->len); smmu->mapping_offset =3D cpu_to_le32(sizeof(*smmu)); smmu->base_address =3D cpu_to_le64(vms->memmap[VIRT_SMMU].base); smmu->flags =3D cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); @@ -295,23 +370,24 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) smmu->sync_gsiv =3D cpu_to_le32(irq + 2); smmu->gerr_gsiv =3D cpu_to_le32(irq + 3); =20 - /* Identity RID mapping covering the whole input RID range */ - idmap =3D &smmu->id_mapping_array[0]; - idmap->input_base =3D 0; - idmap->id_count =3D cpu_to_le32(0xFFFF); - idmap->output_base =3D 0; - /* output IORT node is the ITS group node (the first node) */ - idmap->output_reference =3D cpu_to_le32(iort_node_offset); + for (i =3D 0; i < smmu_idmap_blob->len; i++) { + idmap =3D &smmu->id_mapping_array[i]; + *idmap =3D g_array_index(smmu_idmap_blob, AcpiIortIdMapping, i= ); + /* output IORT node is the ITS group node (the first node) */ + idmap->output_reference =3D cpu_to_le32(iort_node_offset); + } } =20 /* Root Complex Node */ - node_size =3D sizeof(*rc) + sizeof(*idmap); + rc_map_count =3D (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) ? + smmu_idmap_blob->len + its_idmap_blob->len : 1; + node_size =3D sizeof(*rc) + sizeof(*idmap) * rc_map_count; iort_length +=3D node_size; rc =3D acpi_data_push(table_data, node_size); =20 rc->type =3D ACPI_IORT_NODE_PCI_ROOT_COMPLEX; rc->length =3D cpu_to_le16(node_size); - rc->mapping_count =3D cpu_to_le32(1); + rc->mapping_count =3D cpu_to_le32(rc_map_count); rc->mapping_offset =3D cpu_to_le32(sizeof(*rc)); =20 /* fully coherent device */ @@ -319,20 +395,34 @@ build_iort(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) rc->memory_properties.memory_flags =3D 0x3; /* CCA =3D CPM =3D DCAS = =3D 1 */ rc->pci_segment_number =3D 0; /* MCFG pci_segment */ =20 - /* Identity RID mapping covering the whole input RID range */ - idmap =3D &rc->id_mapping_array[0]; - idmap->input_base =3D 0; - idmap->id_count =3D cpu_to_le32(0xFFFF); - idmap->output_base =3D 0; - if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - /* output IORT node is the smmuv3 node */ - idmap->output_reference =3D cpu_to_le32(smmu_offset); + for (i =3D 0; i < rc_map_count; i++) { + idmap =3D &rc->id_mapping_array[i]; + + if (i < smmu_idmap_blob->len) { + *idmap =3D g_array_index(smmu_idmap_blob, AcpiIortIdMappin= g, i); + /* output IORT node is the smmuv3 node */ + idmap->output_reference =3D cpu_to_le32(smmu_offset); + } else { + *idmap =3D g_array_index(its_idmap_blob, + AcpiIortIdMapping, i - smmu_idmap_blob->len); + /* output IORT node is the ITS group node (the first node)= */ + idmap->output_reference =3D cpu_to_le32(iort_node_offset); + } + } } else { + /* Identity RID mapping covering the whole input RID range */ + idmap =3D &rc->id_mapping_array[0]; + idmap->input_base =3D cpu_to_le32(0); + idmap->id_count =3D cpu_to_le32(0xFFFF); + idmap->output_base =3D cpu_to_le32(0); /* output IORT node is the ITS group node (the first node) */ idmap->output_reference =3D cpu_to_le32(iort_node_offset); } =20 + g_array_free(smmu_idmap_blob, true); + g_array_free(its_idmap_blob, true); + /* * Update the pointer address in case table_data->data moves during ab= ove * acpi_data_push operations. --=20 2.19.1 From nobody Mon Feb 9 01:34:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.32; envelope-from=wangxingang5@huawei.com; helo=szxga06-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang In DMAR table, the drhd is set to cover all pci devices when intel_iommu is on. This patch add explicit scope data, including only the pci devices that go through iommu. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/i386/acpi-build.c | 68 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 66 insertions(+), 2 deletions(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index de98750aef..fdb26682cb 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -1988,6 +1988,56 @@ build_srat(GArray *table_data, BIOSLinker *linker, M= achineState *machine) x86ms->oem_table_id); } =20 +/* + * Insert DMAR scope for PCI bridges and endpoint devcie + */ +static void +insert_scope(PCIBus *bus, PCIDevice *dev, void *opaque) +{ + GArray *scope_blob =3D opaque; + AcpiDmarDeviceScope *scope =3D NULL; + + if (object_dynamic_cast(OBJECT(dev), TYPE_PCI_BRIDGE)) { + /* Dmar Scope Type: 0x02 for PCI Bridge */ + build_append_int_noprefix(scope_blob, 0x02, 1); + } else { + /* Dmar Scope Type: 0x01 for PCI Endpoint Device */ + build_append_int_noprefix(scope_blob, 0x01, 1); + } + + /* length */ + build_append_int_noprefix(scope_blob, + sizeof(*scope) + sizeof(scope->path[0]), 1); + /* reserved */ + build_append_int_noprefix(scope_blob, 0, 2); + /* enumeration_id */ + build_append_int_noprefix(scope_blob, 0, 1); + /* bus */ + build_append_int_noprefix(scope_blob, pci_bus_num(bus), 1); + /* device */ + build_append_int_noprefix(scope_blob, PCI_SLOT(dev->devfn), 1); + /* function */ + build_append_int_noprefix(scope_blob, PCI_FUNC(dev->devfn), 1); +} + +/* For a given PCI host bridge, walk and insert DMAR scope */ +static int +dmar_host_bridges(Object *obj, void *opaque) +{ + GArray *scope_blob =3D opaque; + + if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { + PCIBus *bus =3D PCI_HOST_BRIDGE(obj)->bus; + + if (bus && !pci_bus_bypass_iommu(bus)) { + pci_for_each_device(bus, pci_bus_num(bus), insert_scope, + scope_blob); + } + } + + return 0; +} + /* * VT-d spec 8.1 DMA Remapping Reporting Structure * (version Oct. 2014 or later) @@ -2007,6 +2057,15 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, /* Root complex IOAPIC use one path[0] only */ size_t ioapic_scope_size =3D sizeof(*scope) + sizeof(scope->path[0]); IntelIOMMUState *intel_iommu =3D INTEL_IOMMU_DEVICE(iommu); + GArray *scope_blob =3D g_array_new(false, true, 1); + + /* + * A PCI bus walk, for each PCI host bridge. + * Insert scope for each PCI bridge and endpoint device which + * is attached to a bus with iommu enabled. + */ + object_child_foreach_recursive(object_get_root(), + dmar_host_bridges, scope_blob); =20 assert(iommu); if (x86_iommu_ir_supported(iommu)) { @@ -2020,8 +2079,9 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linker= , const char *oem_id, /* DMAR Remapping Hardware Unit Definition structure */ drhd =3D acpi_data_push(table_data, sizeof(*drhd) + ioapic_scope_size); drhd->type =3D cpu_to_le16(ACPI_DMAR_TYPE_HARDWARE_UNIT); - drhd->length =3D cpu_to_le16(sizeof(*drhd) + ioapic_scope_size); - drhd->flags =3D ACPI_DMAR_INCLUDE_PCI_ALL; + drhd->length =3D + cpu_to_le16(sizeof(*drhd) + ioapic_scope_size + scope_blob->len); + drhd->flags =3D 0; /* Don't include all pci device */ drhd->pci_segment =3D cpu_to_le16(0); drhd->address =3D cpu_to_le64(Q35_HOST_BRIDGE_IOMMU_ADDR); =20 @@ -2035,6 +2095,10 @@ build_dmar_q35(GArray *table_data, BIOSLinker *linke= r, const char *oem_id, scope->path[0].device =3D PCI_SLOT(Q35_PSEUDO_DEVFN_IOAPIC); scope->path[0].function =3D PCI_FUNC(Q35_PSEUDO_DEVFN_IOAPIC); =20 + /* Add scope found above */ + g_array_append_vals(table_data, scope_blob->data, scope_blob->len); + g_array_free(scope_blob, true); + if (iommu->dt_supported) { atsr =3D acpi_data_push(table_data, sizeof(*atsr)); atsr->type =3D cpu_to_le16(ACPI_DMAR_TYPE_ATSR); --=20 2.19.1 From nobody Mon Feb 9 01:34:34 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=huawei.com ARC-Seal: i=1; a=rsa-sha256; t=1618992580; cv=none; d=zohomail.com; s=zohoarc; b=OD27EIw4U2n+hMR7+H7Gc2Yicogm0bVwgEZVNszHHH4XEexvP0jjXXkh2Zl8Eyve/g20ymlHAQnv21V+pxklKupPDsx7qql1XAw80ILc1CErcS82imhS24lzpeQrZkhbl8IIODCZQFxJlKFW5XStmr7rjEGCV3sl0AdNi4q4JAc= ARC-Message-Signature: i=1; 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Wed, 21 Apr 2021 04:09:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51884) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7ra-000197-Am; Wed, 21 Apr 2021 04:05:34 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:5019) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lZ7rX-00028E-Pi; Wed, 21 Apr 2021 04:05:34 -0400 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by szxga05-in.huawei.com (SkyGuard) with ESMTP id 4FQCj65sBlztVWy; Wed, 21 Apr 2021 16:03:06 +0800 (CST) Received: from huawei.com (10.174.185.226) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.498.0; Wed, 21 Apr 2021 16:05:18 +0800 From: Wang Xingang To: , , , , , , , , , , Subject: [PATCH RFC v3 8/8] hw/i386/acpi-build: Add bypass_iommu check when building IVRS table Date: Wed, 21 Apr 2021 08:05:03 +0000 Message-ID: <1618992303-19556-9-git-send-email-wangxingang5@huawei.com> X-Mailer: git-send-email 2.6.4.windows.1 In-Reply-To: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> References: <1618992303-19556-1-git-send-email-wangxingang5@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.174.185.226] X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=45.249.212.191; envelope-from=wangxingang5@huawei.com; helo=szxga05-in.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: xieyingtai@huawei.com, cenjiahui@huawei.com, wangxingang5@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Xingang Wang When building IVRS table, only devices which go through iommu will be scanned, and the corresponding ivhd will be inserted. Signed-off-by: Xingang Wang Signed-off-by: Jiahui Cen --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index fdb26682cb..71fb95737c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -2229,7 +2229,7 @@ ivrs_host_bridges(Object *obj, void *opaque) if (object_dynamic_cast(obj, TYPE_PCI_HOST_BRIDGE)) { PCIBus *bus =3D PCI_HOST_BRIDGE(obj)->bus; =20 - if (bus) { + if (bus && !pci_bus_bypass_iommu(bus)) { pci_for_each_device(bus, pci_bus_num(bus), insert_ivhd, ivhd_b= lob); } } --=20 2.19.1