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Wed, 31 Mar 2021 23:54:01 -0400 Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 31 Mar 2021 20:53:43 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 31 Mar 2021 20:53:42 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 0E2901976; Wed, 31 Mar 2021 22:53:40 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1617249239; x=1648785239; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kPRWlBV5fSZAJOSJef4KkuKkO157aZfgtqMV2r7N72U=; b=YFbGz9lwrdGl0G/4t9fBpqYk4QT0oytSC2KUYRyNnij6Roe9/Qj0CsqC QQ8yCjPbdZfS83O+WBhTKAFr992waQgevjWmoYqdkhGjflzoouf95Zr9i uvAsVaM5a4CC5nVTne4HCRaWlPtUf+vwC0wKUsOe0/Jnzxf4i/kHMWdO8 E=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH v2 21/21] Hexagon (target/hexagon) CABAC decode bin Date: Wed, 31 Mar 2021 22:53:33 -0500 Message-Id: <1617249213-22667-22-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617249213-22667-1-git-send-email-tsimpson@quicinc.com> References: <1617249213-22667-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The following instruction is added S2_cabacdecbin Rdd32=3Ddecbin(Rss32,Rtt32) Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/arch.c | 91 +++++++++++++++++++++++++++++++= ++++ target/hexagon/arch.h | 4 ++ target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/macros.def | 15 ++++++ target/hexagon/imported/shift.idef | 47 ++++++++++++++++++ target/hexagon/macros.h | 7 +++ tests/tcg/hexagon/misc.c | 28 +++++++++++ 7 files changed, 193 insertions(+) diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index e602a05..92d4104 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -27,6 +27,97 @@ #define SF_MANTBITS 23 #define float32_nan make_float32(0xffffffff) =20 +/* + * These three tables are used by the cabacdecbin instruction + */ +const uint8_t rLPS_table_64x4[64][4] =3D { + {128, 176, 208, 240}, + {128, 167, 197, 227}, + {128, 158, 187, 216}, + {123, 150, 178, 205}, + {116, 142, 169, 195}, + {111, 135, 160, 185}, + {105, 128, 152, 175}, + {100, 122, 144, 166}, + {95, 116, 137, 158}, + {90, 110, 130, 150}, + {85, 104, 123, 142}, + {81, 99, 117, 135}, + {77, 94, 111, 128}, + {73, 89, 105, 122}, + {69, 85, 100, 116}, + {66, 80, 95, 110}, + {62, 76, 90, 104}, + {59, 72, 86, 99}, + {56, 69, 81, 94}, + {53, 65, 77, 89}, + {51, 62, 73, 85}, + {48, 59, 69, 80}, + {46, 56, 66, 76}, + {43, 53, 63, 72}, + {41, 50, 59, 69}, + {39, 48, 56, 65}, + {37, 45, 54, 62}, + {35, 43, 51, 59}, + {33, 41, 48, 56}, + {32, 39, 46, 53}, + {30, 37, 43, 50}, + {29, 35, 41, 48}, + {27, 33, 39, 45}, + {26, 31, 37, 43}, + {24, 30, 35, 41}, + {23, 28, 33, 39}, + {22, 27, 32, 37}, + {21, 26, 30, 35}, + {20, 24, 29, 33}, + {19, 23, 27, 31}, + {18, 22, 26, 30}, + {17, 21, 25, 28}, + {16, 20, 23, 27}, + {15, 19, 22, 25}, + {14, 18, 21, 24}, + {14, 17, 20, 23}, + {13, 16, 19, 22}, + {12, 15, 18, 21}, + {12, 14, 17, 20}, + {11, 14, 16, 19}, + {11, 13, 15, 18}, + {10, 12, 15, 17}, + {10, 12, 14, 16}, + {9, 11, 13, 15}, + {9, 11, 12, 14}, + {8, 10, 12, 14}, + {8, 9, 11, 13}, + {7, 9, 11, 12}, + {7, 9, 10, 12}, + {7, 8, 10, 11}, + {6, 8, 9, 11}, + {6, 7, 9, 10}, + {6, 7, 8, 9}, + {2, 2, 2, 2} +}; + +const uint8_t AC_next_state_MPS_64[64] =3D { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 62, 63 +}; + + +const uint8_t AC_next_state_LPS_64[64] =3D { + 0, 0, 1, 2, 2, 4, 4, 5, 6, 7, + 8, 9, 9, 11, 11, 12, 13, 13, 15, 15, + 16, 16, 18, 18, 19, 19, 21, 21, 22, 22, + 23, 24, 24, 25, 26, 26, 27, 27, 28, 29, + 29, 30, 30, 30, 31, 32, 32, 33, 33, 33, + 34, 34, 35, 35, 35, 36, 36, 36, 37, 37, + 37, 38, 38, 63 +}; + #define BITS_MASK_8 0x5555555555555555ULL #define PAIR_MASK_8 0x3333333333333333ULL #define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h index 544288e..f6fdd88 100644 --- a/target/hexagon/arch.h +++ b/target/hexagon/arch.h @@ -20,6 +20,10 @@ =20 #include "qemu/int128.h" =20 +extern const uint8_t rLPS_table_64x4[64][4]; +extern const uint8_t AC_next_state_MPS_64[64]; +extern const uint8_t AC_next_state_LPS_64[64]; + uint64_t interleave(uint32_t odd, uint32_t even); uint64_t deinterleave(uint64_t src); int32_t conv_round(int32_t a, int n); diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index dc4eba4..35ae3d2 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -1767,6 +1767,7 @@ SH_RRR_ENC(S4_vxsubaddh, "0001","01-","-","110= ","ddddd") SH_RRR_ENC(S4_vxaddsubhr, "0001","11-","-","00-","ddddd") SH_RRR_ENC(S4_vxsubaddhr, "0001","11-","-","01-","ddddd") SH_RRR_ENC(S4_extractp_rp, "0001","11-","-","10-","ddddd") +SH_RRR_ENC(S2_cabacdecbin, "0001","11-","-","11-","ddddd") /* implici= t P0 write */ =20 =20 DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rd= d=3D(Rss,Rtt,Pu)") diff --git a/target/hexagon/imported/macros.def b/target/hexagon/imported/m= acros.def index 56c99b1..32ed3bf 100755 --- a/target/hexagon/imported/macros.def +++ b/target/hexagon/imported/macros.def @@ -92,6 +92,21 @@ DEF_MACRO( /* attribs */ ) =20 + +DEF_MACRO( + fINSERT_RANGE, + { + int offset=3DLOWBIT; + int width=3DHIBIT-LOWBIT+1; + /* clear bits where new bits go */ + INREG &=3D ~(((fCONSTLL(1)<>29)&3]; + rLPS =3D rLPS << 23; /* left aligned */ + + /* calculate rMPS */ + rMPS=3D (range&0xff800000) - rLPS; + + /* most probable region */ + if (offset < rMPS) { + RddV =3D AC_next_state_MPS_64[state]; + fINSERT_RANGE(RddV,8,8,valMPS); + fINSERT_RANGE(RddV,31,23,(rMPS>>23)); + fSETWORD(1,RddV,offset); + fWRITE_P0(valMPS); + + + } + /* least probable region */ + else { + RddV =3D AC_next_state_LPS_64[state]; + fINSERT_RANGE(RddV,8,8,((!state)?(1-valMPS):(valMPS))); + fINSERT_RANGE(RddV,31,23,(rLPS>>23)); + fSETWORD(1,RddV,(offset-rMPS)); + fWRITE_P0((valMPS^1)); + } +}) + + Q6INSN(S2_clb,"Rd32=3Dclb(Rs32)",ATTRIBS(), "Count leading bits", {RdV =3D fMAX(fCL1_4(RsV),fCL1_4(~RsV));}) =20 diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index a71da8c..1ffd531 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -222,6 +222,13 @@ static inline void gen_pred_cancel(TCGv pred, int slot= _num) (((HIBIT) - (LOWBIT) + 1) ? \ extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ 0LL) +#define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ + do { \ + int width =3D ((HIBIT) - (LOWBIT) + 1); \ + INREG =3D (width >=3D 0 ? \ + deposit64((INREG), (LOWBIT), width, (INVAL)) : \ + INREG); \ + } while (0) =20 #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) =20 diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index e5d78b4..17c3919 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -231,6 +231,14 @@ static void check(int val, int expect) } } =20 +static void check64(long long val, long long expect) +{ + if (val !=3D expect) { + printf("ERROR: 0x%016llx !=3D 0x%016llx\n", val, expect); + err++; + } +} + uint32_t init[10] =3D { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; uint32_t array[10]; =20 @@ -264,6 +272,16 @@ static long long creg_pair(int x, int y) return retval; } =20 +static long long decbin(long long x, long long y, int *pred) +{ + long long retval; + asm ("%0 =3D decbin(%2, %3)\n\t" + "%1 =3D p0\n\t" + : "=3Dr"(retval), "=3Dr"(*pred) + : "r"(x), "r"(y)); + return retval; +} + /* Check that predicates are auto-and'ed in a packet */ static int auto_and(void) { @@ -282,6 +300,8 @@ static int auto_and(void) =20 int main() { + long long res64; + int pred; =20 memcpy(array, init, sizeof(array)); S4_storerhnew_rr(array, 4, 0xffff); @@ -391,6 +411,14 @@ int main() res =3D test_clrtnew(2, 7); check(res, 7); =20 + res64 =3D decbin(0xf0f1f2f3f4f5f6f7LL, 0x7f6f5f4f3f2f1f0fLL, &pred); + check64(res64, 0x357980003700010cLL); + check(pred, 0); + + res64 =3D decbin(0xfLL, 0x1bLL, &pred); + check64(res64, 0x78000100LL); + check(pred, 1); + res =3D auto_and(); check(res, 0); =20 --=20 2.7.4