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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Simplify TCG generation of hex_reg_written Address feedback from Richard Henderson Signed-off-by: Taylor Simpson --- target/hexagon/genptr.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 7481f4c..349b949 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -43,9 +43,15 @@ static inline void gen_log_predicated_reg_write(int rnum= , TCGv val, int slot) tcg_gen_movcond_tl(TCG_COND_EQ, hex_new_value[rnum], slot_mask, zero, val, hex_new_value[rnum]); #if HEX_DEBUG - /* Do this so HELPER(debug_commit_end) will know */ - tcg_gen_movcond_tl(TCG_COND_EQ, hex_reg_written[rnum], slot_mask, zero, - one, hex_reg_written[rnum]); + /* + * Do this so HELPER(debug_commit_end) will know + * + * Note that slot_mask indicates the value is not written + * (i.e., slot was cancelled), so we create a true/false value before + * or'ing with hex_reg_written[rnum]. + */ + tcg_gen_setcond_tl(TCG_COND_EQ, slot_mask, slot_mask, zero); + tcg_gen_or_tl(hex_reg_written[rnum], hex_reg_written[rnum], slot_mask); #endif =20 tcg_temp_free(one); --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616641869; cv=none; d=zohomail.com; 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Wed, 24 Mar 2021 21:50:11 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640626; x=1648176626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wN+qOTd0EQlIrn9zlrkYOxhhMFsN/s5G02sYLSAvneI=; b=EqyZajRp5CCDg8rTPzWEcOxVygvW+1T/VBChDxCpASnxTldUQwJD4nQY +562LV1QY5A9Lknt1IIzEK21YoKFfbYkQA0SyeW23YAZMRv4OU8zni9gL 0h9oTZmCvVqyOPyCOVmhwmarRV6N5fgk/x36JhW8RRjrbBAkl5+a7iMqo M=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 02/15] Hexagon (target/hexagon) remove unnecessary inline directives Date: Wed, 24 Mar 2021 21:49:57 -0500 Message-Id: <1616640610-17319-3-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Address feedback from Richard Henderson Signed-off-by: Taylor Simpson --- linux-user/hexagon/cpu_loop.c | 2 +- target/hexagon/cpu.c | 9 ++++----- target/hexagon/cpu.h | 6 ++---- target/hexagon/decode.c | 6 +++--- target/hexagon/fma_emu.c | 39 ++++++++++++++++++++------------------- target/hexagon/op_helper.c | 39 +++++++++++++++++++-------------------- target/hexagon/translate.c | 2 +- 7 files changed, 50 insertions(+), 53 deletions(-) diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index 9a68ca0..a752a0a 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -25,7 +25,7 @@ =20 void cpu_loop(CPUHexagonState *env) { - CPUState *cs =3D CPU(hexagon_env_get_cpu(env)); + CPUState *cs =3D CPUSTATE_FROM_ENV(env); int trapnr, signum, sigcode; target_ulong sigaddr; target_ulong syscallnum; diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index b0b3040..002275a 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -69,10 +69,9 @@ const char * const hexagon_regnames[TOTAL_PER_THREAD_REG= S] =3D { * stacks at different locations. This is used to compensate so the diff = is * cleaner. */ -static inline target_ulong adjust_stack_ptrs(CPUHexagonState *env, - target_ulong addr) +static target_ulong adjust_stack_ptrs(CPUHexagonState *env, target_ulong a= ddr) { - HexagonCPU *cpu =3D container_of(env, HexagonCPU, env); + HexagonCPU *cpu =3D HEXAGONCPU_FROM_ENV(env); target_ulong stack_adjust =3D cpu->lldb_stack_adjust; target_ulong stack_start =3D env->stack_start; target_ulong stack_size =3D 0x10000; @@ -88,7 +87,7 @@ static inline target_ulong adjust_stack_ptrs(CPUHexagonSt= ate *env, } =20 /* HEX_REG_P3_0 (aka C4) is an alias for the predicate registers */ -static inline target_ulong read_p3_0(CPUHexagonState *env) +static target_ulong read_p3_0(CPUHexagonState *env) { int32_t control_reg =3D 0; int i; @@ -116,7 +115,7 @@ static void print_reg(FILE *f, CPUHexagonState *env, in= t regnum) =20 static void hexagon_dump(CPUHexagonState *env, FILE *f) { - HexagonCPU *cpu =3D container_of(env, HexagonCPU, env); + HexagonCPU *cpu =3D HEXAGONCPU_FROM_ENV(env); =20 if (cpu->lldb_compat) { /* diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index e04eac5..433f420 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -127,10 +127,8 @@ typedef struct HexagonCPU { target_ulong lldb_stack_adjust; } HexagonCPU; =20 -static inline HexagonCPU *hexagon_env_get_cpu(CPUHexagonState *env) -{ - return container_of(env, HexagonCPU, env); -} +#define HEXAGONCPU_FROM_ENV(env) container_of((env), HexagonCPU, env) +#define CPUSTATE_FROM_ENV(env) CPU(HEXAGONCPU_FROM_ENV(env)) =20 #include "cpu_bits.h" =20 diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 1c9c074..65d97ce 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -354,7 +354,7 @@ static void decode_split_cmpjump(Packet *pkt) } } =20 -static inline int decode_opcode_can_jump(int opcode) +static int decode_opcode_can_jump(int opcode) { if ((GET_ATTRIB(opcode, A_JUMP)) || (GET_ATTRIB(opcode, A_CALL)) || @@ -370,7 +370,7 @@ static inline int decode_opcode_can_jump(int opcode) return 0; } =20 -static inline int decode_opcode_ends_loop(int opcode) +static int decode_opcode_ends_loop(int opcode) { return GET_ATTRIB(opcode, A_HWLOOP0_END) || GET_ATTRIB(opcode, A_HWLOOP1_END); @@ -764,7 +764,7 @@ static void decode_add_endloop_insn(Insn *insn, int loo= pnum) } } =20 -static inline int decode_parsebits_is_loopend(uint32_t encoding32) +static int decode_parsebits_is_loopend(uint32_t encoding32) { uint32_t bits =3D parse_bits(encoding32); return bits =3D=3D 0x2; diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c index 842d903..f324b83 100644 --- a/target/hexagon/fma_emu.c +++ b/target/hexagon/fma_emu.c @@ -64,7 +64,7 @@ typedef union { }; } Float; =20 -static inline uint64_t float64_getmant(float64 f64) +static uint64_t float64_getmant(float64 f64) { Double a =3D { .i =3D f64 }; if (float64_is_normal(f64)) { @@ -91,7 +91,7 @@ int32_t float64_getexp(float64 f64) return -1; } =20 -static inline uint64_t float32_getmant(float32 f32) +static uint64_t float32_getmant(float32 f32) { Float a =3D { .i =3D f32 }; if (float32_is_normal(f32)) { @@ -118,17 +118,17 @@ int32_t float32_getexp(float32 f32) return -1; } =20 -static inline uint32_t int128_getw0(Int128 x) +static uint32_t int128_getw0(Int128 x) { return int128_getlo(x); } =20 -static inline uint32_t int128_getw1(Int128 x) +static uint32_t int128_getw1(Int128 x) { return int128_getlo(x) >> 32; } =20 -static inline Int128 int128_mul_6464(uint64_t ai, uint64_t bi) +static Int128 int128_mul_6464(uint64_t ai, uint64_t bi) { Int128 a, b; uint64_t pp0, pp1a, pp1b, pp1s, pp2; @@ -152,7 +152,7 @@ static inline Int128 int128_mul_6464(uint64_t ai, uint6= 4_t bi) return int128_make128(ret_low, pp2 + (pp1s >> 32)); } =20 -static inline Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow) +static Int128 int128_sub_borrow(Int128 a, Int128 b, int borrow) { Int128 ret =3D int128_sub(a, b); if (borrow !=3D 0) { @@ -170,7 +170,7 @@ typedef struct { uint8_t sticky; } Accum; =20 -static inline void accum_init(Accum *p) +static void accum_init(Accum *p) { p->mant =3D int128_zero(); p->exp =3D 0; @@ -180,7 +180,7 @@ static inline void accum_init(Accum *p) p->sticky =3D 0; } =20 -static inline Accum accum_norm_left(Accum a) +static Accum accum_norm_left(Accum a) { a.exp--; a.mant =3D int128_lshift(a.mant, 1); @@ -190,6 +190,7 @@ static inline Accum accum_norm_left(Accum a) return a; } =20 +/* This function is marked inline for performance reasons */ static inline Accum accum_norm_right(Accum a, int amt) { if (amt > 130) { @@ -226,7 +227,7 @@ static inline Accum accum_norm_right(Accum a, int amt) */ static Accum accum_add(Accum a, Accum b); =20 -static inline Accum accum_sub(Accum a, Accum b, int negate) +static Accum accum_sub(Accum a, Accum b, int negate) { Accum ret; accum_init(&ret); @@ -329,7 +330,7 @@ static Accum accum_add(Accum a, Accum b) } =20 /* Return an infinity with requested sign */ -static inline float64 infinite_float64(uint8_t sign) +static float64 infinite_float64(uint8_t sign) { if (sign) { return make_float64(DF_MINUS_INF); @@ -339,7 +340,7 @@ static inline float64 infinite_float64(uint8_t sign) } =20 /* Return a maximum finite value with requested sign */ -static inline float64 maxfinite_float64(uint8_t sign) +static float64 maxfinite_float64(uint8_t sign) { if (sign) { return make_float64(DF_MINUS_MAXF); @@ -349,7 +350,7 @@ static inline float64 maxfinite_float64(uint8_t sign) } =20 /* Return a zero value with requested sign */ -static inline float64 zero_float64(uint8_t sign) +static float64 zero_float64(uint8_t sign) { if (sign) { return make_float64(0x8000000000000000); @@ -369,7 +370,7 @@ float32 infinite_float32(uint8_t sign) } =20 /* Return a maximum finite value with the requested sign */ -static inline float32 maxfinite_float32(uint8_t sign) +static float32 maxfinite_float32(uint8_t sign) { if (sign) { return make_float32(SF_MINUS_MAXF); @@ -379,7 +380,7 @@ static inline float32 maxfinite_float32(uint8_t sign) } =20 /* Return a zero value with requested sign */ -static inline float32 zero_float32(uint8_t sign) +static float32 zero_float32(uint8_t sign) { if (sign) { return make_float32(0x80000000); @@ -389,7 +390,7 @@ static inline float32 zero_float32(uint8_t sign) } =20 #define GEN_XF_ROUND(SUFFIX, MANTBITS, INF_EXP, INTERNAL_TYPE) \ -static inline SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_statu= s) \ +static SUFFIX accum_round_##SUFFIX(Accum a, float_status * fp_status) \ { \ if ((int128_gethi(a.mant) =3D=3D 0) && (int128_getlo(a.mant) =3D=3D 0)= \ && ((a.guard | a.round | a.sticky) =3D=3D 0)) { \ @@ -526,8 +527,8 @@ static bool is_inf_prod(float64 a, float64 b) (float64_is_infinity(b) && is_finite(a) && (!float64_is_zero(a= )))); } =20 -static inline float64 special_fma(float64 a, float64 b, float64 c, - float_status *fp_status) +static float64 special_fma(float64 a, float64 b, float64 c, + float_status *fp_status) { float64 ret =3D make_float64(0); =20 @@ -586,8 +587,8 @@ static inline float64 special_fma(float64 a, float64 b,= float64 c, g_assert_not_reached(); } =20 -static inline float32 special_fmaf(float32 a, float32 b, float32 c, - float_status *fp_status) +static float32 special_fmaf(float32 a, float32 b, float32 c, + float_status *fp_status) { float64 aa, bb, cc; aa =3D float32_to_float64(a, fp_status); diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index d6b5c47..7361a07 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -35,7 +35,7 @@ static void QEMU_NORETURN do_raise_exception_err(CPUHexag= onState *env, uint32_t exception, uintptr_t pc) { - CPUState *cs =3D CPU(hexagon_env_get_cpu(env)); + CPUState *cs =3D CPUSTATE_FROM_ENV(env); qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); cs->exception_index =3D exception; cpu_loop_exit_restore(cs, pc); @@ -46,8 +46,8 @@ void QEMU_NORETURN HELPER(raise_exception)(CPUHexagonStat= e *env, uint32_t excp) do_raise_exception_err(env, excp, 0); } =20 -static inline void log_reg_write(CPUHexagonState *env, int rnum, - target_ulong val, uint32_t slot) +static void log_reg_write(CPUHexagonState *env, int rnum, + target_ulong val, uint32_t slot) { HEX_DEBUG_LOG("log_reg_write[%d] =3D " TARGET_FMT_ld " (0x" TARGET_FMT= _lx ")", rnum, val, val); @@ -63,8 +63,7 @@ static inline void log_reg_write(CPUHexagonState *env, in= t rnum, #endif } =20 -static inline void log_pred_write(CPUHexagonState *env, int pnum, - target_ulong val) +static void log_pred_write(CPUHexagonState *env, int pnum, target_ulong va= l) { HEX_DEBUG_LOG("log_pred_write[%d] =3D " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")\n", @@ -79,8 +78,8 @@ static inline void log_pred_write(CPUHexagonState *env, i= nt pnum, } } =20 -static inline void log_store32(CPUHexagonState *env, target_ulong addr, - target_ulong val, int width, int slot) +static void log_store32(CPUHexagonState *env, target_ulong addr, + target_ulong val, int width, int slot) { HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %" PRId32 " [0x08%" PRIx32 "])\n", @@ -90,8 +89,8 @@ static inline void log_store32(CPUHexagonState *env, targ= et_ulong addr, env->mem_log_stores[slot].data32 =3D val; } =20 -static inline void log_store64(CPUHexagonState *env, target_ulong addr, - int64_t val, int width, int slot) +static void log_store64(CPUHexagonState *env, target_ulong addr, + int64_t val, int width, int slot) { HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx ", %" PRId64 " [0x016%" PRIx64 "])\n", @@ -101,7 +100,7 @@ static inline void log_store64(CPUHexagonState *env, ta= rget_ulong addr, env->mem_log_stores[slot].data64 =3D val; } =20 -static inline void write_new_pc(CPUHexagonState *env, target_ulong addr) +static void write_new_pc(CPUHexagonState *env, target_ulong addr) { HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr); =20 @@ -132,7 +131,7 @@ void HELPER(debug_start_packet)(CPUHexagonState *env) } #endif =20 -static inline int32_t new_pred_value(CPUHexagonState *env, int pnum) +static int32_t new_pred_value(CPUHexagonState *env, int pnum) { return env->new_pred_value[pnum]; } @@ -332,8 +331,8 @@ static void check_noshuf(CPUHexagonState *env, uint32_t= slot) } } =20 -static inline uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +static uint8_t mem_load1(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) { uint8_t retval; check_noshuf(env, slot); @@ -341,8 +340,8 @@ static inline uint8_t mem_load1(CPUHexagonState *env, u= int32_t slot, return retval; } =20 -static inline uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +static uint16_t mem_load2(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) { uint16_t retval; check_noshuf(env, slot); @@ -350,8 +349,8 @@ static inline uint16_t mem_load2(CPUHexagonState *env, = uint32_t slot, return retval; } =20 -static inline uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +static uint32_t mem_load4(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) { uint32_t retval; check_noshuf(env, slot); @@ -359,8 +358,8 @@ static inline uint32_t mem_load4(CPUHexagonState *env, = uint32_t slot, return retval; } =20 -static inline uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, - target_ulong vaddr) +static uint64_t mem_load8(CPUHexagonState *env, uint32_t slot, + target_ulong vaddr) { uint64_t retval; check_noshuf(env, slot); @@ -939,7 +938,7 @@ float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV, return RxV; } =20 -static inline bool is_inf_prod(int32_t a, int32_t b) +static bool is_inf_prod(int32_t a, int32_t b) { return (float32_is_infinity(a) && float32_is_infinity(b)) || (float32_is_infinity(a) && is_finite(b) && !float32_is_zero(b))= || diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 2317508..5d92ab0 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -585,7 +585,7 @@ static void hexagon_tr_translate_packet(DisasContextBas= e *dcbase, CPUState *cpu) * The CPU log is used to compare against LLDB single stepping, * so end the TLB after every packet. */ - HexagonCPU *hex_cpu =3D container_of(env, HexagonCPU, env); + HexagonCPU *hex_cpu =3D HEXAGONCPU_FROM_ENV(env); if (hex_cpu->lldb_compat && qemu_loglevel_mask(CPU_LOG_TB_CPU)) { ctx->base.is_jmp =3D DISAS_TOO_MANY; } --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Wed, 24 Mar 2021 22:50:18 -0400 Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 24 Mar 2021 19:50:12 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 24 Mar 2021 19:50:12 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D9D6EF3E; Wed, 24 Mar 2021 21:50:11 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640616; x=1648176616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3jNrOdmQxJl0c2xX4pFV8sqmZ+8vTUVM89UXf22q8qs=; b=ro9lZZrvIYKVnUppnXXjUmss4ds1dDJGkbL+9EDrhGanfclGHCUIMO1l FzSeq4lLFs4UU/chjphr5gxrppvop+75pOBXdLkb6Kq0AoxsNwhmhespt NIr4NPio2p1G2AkWPpfFdlM3PbLZGwbruMYWCdgvHNoTllQE9Arvjigms E=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 03/15] Hexagon (target/hexagon) properly generate TB end for DISAS_NORETURN Date: Wed, 24 Mar 2021 21:49:58 -0500 Message-Id: <1616640610-17319-4-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) When exiting a TB, generate all the code before returning from hexagon_tr_translate_packet so that nothing needs to be done in hexagon_tr_tb_stop. Address feedback from Richard Henderson Signed-off-by: Taylor Simpson --- target/hexagon/translate.c | 62 +++++++++++++++++++++++++-----------------= ---- target/hexagon/translate.h | 3 --- 2 files changed, 34 insertions(+), 31 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 5d92ab0..19b9bc7 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -54,16 +54,41 @@ static const char * const hexagon_prednames[] =3D { "p0", "p1", "p2", "p3" }; =20 -void gen_exception(int excp) +static void gen_exception(int excp) { TCGv_i32 helper_tmp =3D tcg_const_i32(excp); gen_helper_raise_exception(cpu_env, helper_tmp); tcg_temp_free_i32(helper_tmp); } =20 -void gen_exception_debug(void) +static void gen_exec_counters(DisasContext *ctx) +{ + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], + hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); + tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], + hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); +} + +static void gen_end_tb(DisasContext *ctx) { - gen_exception(EXCP_DEBUG); + gen_exec_counters(ctx); + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + if (ctx->base.singlestep_enabled) { + gen_exception(EXCP_DEBUG); + } else { + tcg_gen_exit_tb(NULL, 0); + } + ctx->base.is_jmp =3D DISAS_NORETURN; +} + +static void gen_exception_end_tb(DisasContext *ctx, int excp) +{ + gen_exec_counters(ctx); + tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); + gen_exception(excp); + tcg_gen_exit_tb(NULL, 0); + ctx->base.is_jmp =3D DISAS_NORETURN; + } =20 #if HEX_DEBUG @@ -225,8 +250,7 @@ static void gen_insn(CPUHexagonState *env, DisasContext= *ctx, mark_implicit_writes(ctx, insn); insn->generate(env, ctx, insn, pkt); } else { - gen_exception(HEX_EXCP_INVALID_OPCODE); - ctx->base.is_jmp =3D DISAS_NORETURN; + gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); } } =20 @@ -447,14 +471,6 @@ static void update_exec_counters(DisasContext *ctx, Pa= cket *pkt) ctx->num_insns +=3D num_real_insns; } =20 -static void gen_exec_counters(DisasContext *ctx) -{ - tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_PKT_CNT], - hex_gpr[HEX_REG_QEMU_PKT_CNT], ctx->num_packets); - tcg_gen_addi_tl(hex_gpr[HEX_REG_QEMU_INSN_CNT], - hex_gpr[HEX_REG_QEMU_INSN_CNT], ctx->num_insns); -} - static void gen_commit_packet(DisasContext *ctx, Packet *pkt) { gen_reg_writes(ctx); @@ -478,7 +494,7 @@ static void gen_commit_packet(DisasContext *ctx, Packet= *pkt) #endif =20 if (pkt->pkt_has_cof) { - ctx->base.is_jmp =3D DISAS_NORETURN; + gen_end_tb(ctx); } } =20 @@ -491,8 +507,7 @@ static void decode_and_translate_packet(CPUHexagonState= *env, DisasContext *ctx) =20 nwords =3D read_packet_words(env, ctx, words); if (!nwords) { - gen_exception(HEX_EXCP_INVALID_PACKET); - ctx->base.is_jmp =3D DISAS_NORETURN; + gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); return; } =20 @@ -505,8 +520,7 @@ static void decode_and_translate_packet(CPUHexagonState= *env, DisasContext *ctx) gen_commit_packet(ctx, &pkt); ctx->base.pc_next +=3D pkt.encod_pkt_size_in_bytes; } else { - gen_exception(HEX_EXCP_INVALID_PACKET); - ctx->base.is_jmp =3D DISAS_NORETURN; + gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); } } =20 @@ -537,8 +551,7 @@ static bool hexagon_tr_breakpoint_check(DisasContextBas= e *dcbase, CPUState *cpu, DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); - ctx->base.is_jmp =3D DISAS_NORETURN; - gen_exception_debug(); + gen_exception_end_tb(ctx, EXCP_DEBUG); /* * The address covered by the breakpoint must be included in * [tb->pc, tb->pc + tb->size) in order to for it to be @@ -601,19 +614,12 @@ static void hexagon_tr_tb_stop(DisasContextBase *dcba= se, CPUState *cpu) gen_exec_counters(ctx); tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->base.pc_next); if (ctx->base.singlestep_enabled) { - gen_exception_debug(); + gen_exception(EXCP_DEBUG); } else { tcg_gen_exit_tb(NULL, 0); } break; case DISAS_NORETURN: - gen_exec_counters(ctx); - tcg_gen_mov_tl(hex_gpr[HEX_REG_PC], hex_next_PC); - if (ctx->base.singlestep_enabled) { - gen_exception_debug(); - } else { - tcg_gen_exit_tb(NULL, 0); - } break; default: g_assert_not_reached(); diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 938f7fb..12506c8 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -86,8 +86,5 @@ extern TCGv hex_llsc_addr; extern TCGv hex_llsc_val; extern TCGv_i64 hex_llsc_val_i64; =20 -void gen_exception(int excp); -void gen_exception_debug(void); - void process_store(DisasContext *ctx, Packet *pkt, int slot_num); #endif --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616641546; cv=none; d=zohomail.com; s=zohoarc; b=JFkGrxfe7PnLXAGcSHZ4OfKCKfjWxWkTGKX2jEUnudWzcoPm99w1q6zNVROHJRJjom9xmGyYJCgITXUJvn77dMzYr5DnWXc8Sa1StNpijI4EOQa8hn6TquIv74BupXywcHEf9h1OILU/JL5JWYm/5Im+9Ez2ASSDc955LXmh7MY= ARC-Message-Signature: i=1; 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i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640617; x=1648176617; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TSAFuo83vntVSDsWqoXFqnIbKl7a0mI/Gs99Nlw5zrQ=; b=wZQFRliLGIBEcj/HywDNX0tDqE96ySP9NA8ehGv/1f6ubPZA9cqFFA3M B7Np0D2WcCtB6XcnxNGF3k48CQa1rFQs5jP0/qzLRgBdKYrT16PBIjY0o XItR0PJHkgN/s66dMgymyA2rqA4x+5FLH8W4+09N+UMveWJ5bZ+bV2d2C o=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 04/15] Hexagon (target/hexagon) decide if pred has been written at TCG gen time Date: Wed, 24 Mar 2021 21:49:59 -0500 Message-Id: <1616640610-17319-5-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Multiple writes to the same preg are and'ed together. Rather than generating a runtime check, we can determine at TCG generation time if the predicate has previously been written in the packet. Test added to tests/tcg/hexagon/misc.c Address feedback from Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/gen_tcg_funcs.py | 2 +- target/hexagon/genptr.c | 22 +++++++++++++++------- target/hexagon/translate.c | 9 +++++++-- target/hexagon/translate.h | 2 ++ tests/tcg/hexagon/misc.c | 19 +++++++++++++++++++ 5 files changed, 44 insertions(+), 10 deletions(-) diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index db9f663..7ceb25b 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -316,7 +316,7 @@ def genptr_dst_write(f, tag, regtype, regid): print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "P"): if (regid in {"d", "e", "x"}): - f.write(" gen_log_pred_write(%s%sN, %s%sV);\n" % \ + f.write(" gen_log_pred_write(ctx, %s%sN, %s%sV);\n" % \ (regtype, regid, regtype, regid)) f.write(" ctx_log_pred_write(ctx, %s%sN);\n" % \ (regtype, regid)) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 349b949..9e9dfd5 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -122,20 +122,28 @@ static void gen_log_reg_write_pair(int rnum, TCGv_i64= val) #endif } =20 -static inline void gen_log_pred_write(int pnum, TCGv val) +static inline void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv va= l) { TCGv zero =3D tcg_const_tl(0); TCGv base_val =3D tcg_temp_new(); TCGv and_val =3D tcg_temp_new(); TCGv pred_written =3D tcg_temp_new(); =20 - /* Multiple writes to the same preg are and'ed together */ tcg_gen_andi_tl(base_val, val, 0xff); - tcg_gen_and_tl(and_val, base_val, hex_new_pred_value[pnum]); - tcg_gen_andi_tl(pred_written, hex_pred_written, 1 << pnum); - tcg_gen_movcond_tl(TCG_COND_NE, hex_new_pred_value[pnum], - pred_written, zero, - and_val, base_val); + + /* + * Section 6.1.3 of the Hexagon V67 Programmer's Reference Manual + * + * Multiple writes to the same preg are and'ed together + * If this is the first predicate write in the packet, do a + * straight assignment. Otherwise, do an and. + */ + if (!test_bit(pnum, ctx->pregs_written)) { + tcg_gen_mov_tl(hex_new_pred_value[pnum], base_val); + } else { + tcg_gen_and_tl(hex_new_pred_value[pnum], + hex_new_pred_value[pnum], base_val); + } tcg_gen_ori_tl(hex_pred_written, hex_pred_written, 1 << pnum); =20 tcg_temp_free(zero); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 19b9bc7..2d7ec12 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -173,6 +173,7 @@ static void gen_start_packet(DisasContext *ctx, Packet = *pkt) ctx->reg_log_idx =3D 0; bitmap_zero(ctx->regs_written, TOTAL_PER_THREAD_REGS); ctx->preg_log_idx =3D 0; + bitmap_zero(ctx->pregs_written, NUM_PREGS); for (i =3D 0; i < STORES_MAX; i++) { ctx->store_width[i] =3D 0; } @@ -227,7 +228,7 @@ static void mark_implicit_pred_write(DisasContext *ctx,= Insn *insn, } } =20 -static void mark_implicit_writes(DisasContext *ctx, Insn *insn) +static void mark_implicit_reg_writes(DisasContext *ctx, Insn *insn) { mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_FP, HEX_REG_FP); mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SP, HEX_REG_SP); @@ -236,7 +237,10 @@ static void mark_implicit_writes(DisasContext *ctx, In= sn *insn) mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA0, HEX_REG_SA0); mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_LC1, HEX_REG_LC1); mark_implicit_reg_write(ctx, insn, A_IMPLICIT_WRITES_SA1, HEX_REG_SA1); +} =20 +static void mark_implicit_pred_writes(DisasContext *ctx, Insn *insn) +{ mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P0, 0); mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P1, 1); mark_implicit_pred_write(ctx, insn, A_IMPLICIT_WRITES_P2, 2); @@ -247,8 +251,9 @@ static void gen_insn(CPUHexagonState *env, DisasContext= *ctx, Insn *insn, Packet *pkt) { if (insn->generate) { - mark_implicit_writes(ctx, insn); + mark_implicit_reg_writes(ctx, insn); insn->generate(env, ctx, insn, pkt); + mark_implicit_pred_writes(ctx, insn); } else { gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); } diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 12506c8..0ecfbd7 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -34,6 +34,7 @@ typedef struct DisasContext { DECLARE_BITMAP(regs_written, TOTAL_PER_THREAD_REGS); int preg_log[PRED_WRITES_MAX]; int preg_log_idx; + DECLARE_BITMAP(pregs_written, NUM_PREGS); uint8_t store_width[STORES_MAX]; uint8_t s1_store_processed; } DisasContext; @@ -60,6 +61,7 @@ static inline void ctx_log_pred_write(DisasContext *ctx, = int pnum) { ctx->preg_log[ctx->preg_log_idx] =3D pnum; ctx->preg_log_idx++; + set_bit(pnum, ctx->pregs_written); } =20 static inline bool is_preloaded(DisasContext *ctx, int num) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index 458759f..e5d78b4 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -264,6 +264,22 @@ static long long creg_pair(int x, int y) return retval; } =20 +/* Check that predicates are auto-and'ed in a packet */ +static int auto_and(void) +{ + int retval; + asm ("r5 =3D #1\n\t" + "{\n\t" + " p0 =3D cmp.eq(r1, #1)\n\t" + " p0 =3D cmp.eq(r1, #2)\n\t" + "}\n\t" + "%0 =3D p0\n\t" + : "=3Dr"(retval) + : + : "r5", "p0"); + return retval; +} + int main() { =20 @@ -375,6 +391,9 @@ int main() res =3D test_clrtnew(2, 7); check(res, 7); =20 + res =3D auto_and(); + check(res, 0); + puts(err ? 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Address feedback from Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/hexagon/cpu_bits.h | 2 +- target/hexagon/decode.c | 80 +++++++++++++++++++++++-------------------= ---- target/hexagon/insn.h | 21 ++++++------ target/hexagon/op_helper.c | 8 ++--- target/hexagon/translate.c | 6 ++-- target/hexagon/translate.h | 2 +- 6 files changed, 60 insertions(+), 59 deletions(-) diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 96af834..96fef71 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -47,7 +47,7 @@ static inline uint32_t iclass_bits(uint32_t encoding) return iclass; } =20 -static inline int is_packet_end(uint32_t endocing) +static inline bool is_packet_end(uint32_t endocing) { uint32_t bits =3D parse_bits(endocing); return ((bits =3D=3D 0x3) || (bits =3D=3D 0x0)); diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index 65d97ce..dffe1d1 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -340,8 +340,8 @@ static void decode_split_cmpjump(Packet *pkt) if (GET_ATTRIB(pkt->insn[i].opcode, A_NEWCMPJUMP)) { last =3D pkt->num_insns; pkt->insn[last] =3D pkt->insn[i]; /* copy the instruction */ - pkt->insn[last].part1 =3D 1; /* last instruction does the C= MP */ - pkt->insn[i].part1 =3D 0; /* existing instruction does the = JUMP */ + pkt->insn[last].part1 =3D true; /* last insn does the CMP= */ + pkt->insn[i].part1 =3D false; /* existing insn does the= JUMP */ pkt->num_insns++; } } @@ -354,7 +354,7 @@ static void decode_split_cmpjump(Packet *pkt) } } =20 -static int decode_opcode_can_jump(int opcode) +static bool decode_opcode_can_jump(int opcode) { if ((GET_ATTRIB(opcode, A_JUMP)) || (GET_ATTRIB(opcode, A_CALL)) || @@ -362,15 +362,15 @@ static int decode_opcode_can_jump(int opcode) (opcode =3D=3D J2_pause)) { /* Exception to A_JUMP attribute */ if (opcode =3D=3D J4_hintjumpr) { - return 0; + return false; } - return 1; + return true; } =20 - return 0; + return false; } =20 -static int decode_opcode_ends_loop(int opcode) +static bool decode_opcode_ends_loop(int opcode) { return GET_ATTRIB(opcode, A_HWLOOP0_END) || GET_ATTRIB(opcode, A_HWLOOP1_END); @@ -383,9 +383,9 @@ static void decode_set_insn_attr_fields(Packet *pkt) int numinsns =3D pkt->num_insns; uint16_t opcode; =20 - pkt->pkt_has_cof =3D 0; - pkt->pkt_has_endloop =3D 0; - pkt->pkt_has_dczeroa =3D 0; + pkt->pkt_has_cof =3D false; + pkt->pkt_has_endloop =3D false; + pkt->pkt_has_dczeroa =3D false; =20 for (i =3D 0; i < numinsns; i++) { opcode =3D pkt->insn[i].opcode; @@ -394,14 +394,14 @@ static void decode_set_insn_attr_fields(Packet *pkt) } =20 if (GET_ATTRIB(opcode, A_DCZEROA)) { - pkt->pkt_has_dczeroa =3D 1; + pkt->pkt_has_dczeroa =3D true; } =20 if (GET_ATTRIB(opcode, A_STORE)) { if (pkt->insn[i].slot =3D=3D 0) { - pkt->pkt_has_store_s0 =3D 1; + pkt->pkt_has_store_s0 =3D true; } else { - pkt->pkt_has_store_s1 =3D 1; + pkt->pkt_has_store_s1 =3D true; } } =20 @@ -422,9 +422,9 @@ static void decode_set_insn_attr_fields(Packet *pkt) */ static void decode_shuffle_for_execution(Packet *packet) { - int changed =3D 0; + bool changed =3D false; int i; - int flag; /* flag means we've seen a non-memory instruction */ + bool flag; /* flag means we've seen a non-memory instruction */ int n_mems; int last_insn =3D packet->num_insns - 1; =20 @@ -437,7 +437,7 @@ static void decode_shuffle_for_execution(Packet *packet) } =20 do { - changed =3D 0; + changed =3D false; /* * Stores go last, must not reorder. * Cannot shuffle stores past loads, either. @@ -445,13 +445,13 @@ static void decode_shuffle_for_execution(Packet *pack= et) * then a store, shuffle the store to the front. Don't shuffle * stores wrt each other or a load. */ - for (flag =3D n_mems =3D 0, i =3D last_insn; i >=3D 0; i--) { + for (flag =3D false, n_mems =3D 0, i =3D last_insn; i >=3D 0; i--)= { int opcode =3D packet->insn[i].opcode; =20 if (flag && GET_ATTRIB(opcode, A_STORE)) { decode_send_insn_to(packet, i, last_insn - n_mems); n_mems++; - changed =3D 1; + changed =3D true; } else if (GET_ATTRIB(opcode, A_STORE)) { n_mems++; } else if (GET_ATTRIB(opcode, A_LOAD)) { @@ -466,7 +466,7 @@ static void decode_shuffle_for_execution(Packet *packet) * a .new value */ } else { - flag =3D 1; + flag =3D true; } } =20 @@ -474,7 +474,7 @@ static void decode_shuffle_for_execution(Packet *packet) continue; } /* Compares go first, may be reordered wrt each other */ - for (flag =3D 0, i =3D 0; i < last_insn + 1; i++) { + for (flag =3D false, i =3D 0; i < last_insn + 1; i++) { int opcode =3D packet->insn[i].opcode; =20 if ((strstr(opcode_wregs[opcode], "Pd4") || @@ -483,7 +483,7 @@ static void decode_shuffle_for_execution(Packet *packet) /* This should be a compare (not a store conditional) */ if (flag) { decode_send_insn_to(packet, i, 0); - changed =3D 1; + changed =3D true; continue; } } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P3) && @@ -495,18 +495,18 @@ static void decode_shuffle_for_execution(Packet *pack= et) */ if (flag) { decode_send_insn_to(packet, i, 0); - changed =3D 1; + changed =3D true; continue; } } else if (GET_ATTRIB(opcode, A_IMPLICIT_WRITES_P0) && !GET_ATTRIB(opcode, A_NEWCMPJUMP)) { if (flag) { decode_send_insn_to(packet, i, 0); - changed =3D 1; + changed =3D true; continue; } } else { - flag =3D 1; + flag =3D true; } } if (changed) { @@ -543,7 +543,7 @@ static void decode_apply_extenders(Packet *packet) int i; for (i =3D 0; i < packet->num_insns; i++) { if (GET_ATTRIB(packet->insn[i].opcode, A_IT_EXTENDER)) { - packet->insn[i + 1].extension_valid =3D 1; + packet->insn[i + 1].extension_valid =3D true; apply_extender(packet, i + 1, packet->insn[i].immed[0]); } } @@ -764,7 +764,7 @@ static void decode_add_endloop_insn(Insn *insn, int loo= pnum) } } =20 -static int decode_parsebits_is_loopend(uint32_t encoding32) +static bool decode_parsebits_is_loopend(uint32_t encoding32) { uint32_t bits =3D parse_bits(encoding32); return bits =3D=3D 0x2; @@ -775,8 +775,11 @@ decode_set_slot_number(Packet *pkt) { int slot; int i; - int hit_mem_insn =3D 0; - int hit_duplex =3D 0; + bool hit_mem_insn =3D false; + bool hit_duplex =3D false; + bool slot0_found =3D false; + bool slot1_found =3D false; + int slot1_iidx =3D 0; =20 /* * The slots are encoded in reverse order @@ -801,7 +804,7 @@ decode_set_slot_number(Packet *pkt) if ((GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE) || GET_ATTRIB(pkt->insn[i].opcode, A_MEMLIKE_PACKET_RULES)) && !hit_mem_insn) { - hit_mem_insn =3D 1; + hit_mem_insn =3D true; pkt->insn[i].slot =3D 0; continue; } @@ -818,7 +821,7 @@ decode_set_slot_number(Packet *pkt) for (i =3D pkt->num_insns - 1; i >=3D 0; i--) { /* First subinsn always goes to slot 0 */ if (GET_ATTRIB(pkt->insn[i].opcode, A_SUBINSN) && !hit_duplex) { - hit_duplex =3D 1; + hit_duplex =3D true; pkt->insn[i].slot =3D 0; continue; } @@ -830,13 +833,10 @@ decode_set_slot_number(Packet *pkt) } =20 /* Fix the exceptions - slot 1 is never empty, always aligns to slot 0= */ - int slot0_found =3D 0; - int slot1_found =3D 0; - int slot1_iidx =3D 0; for (i =3D pkt->num_insns - 1; i >=3D 0; i--) { /* Is slot0 used? */ if (pkt->insn[i].slot =3D=3D 0) { - int is_endloop =3D (pkt->insn[i].opcode =3D=3D J2_endloop01); + bool is_endloop =3D (pkt->insn[i].opcode =3D=3D J2_endloop01); is_endloop |=3D (pkt->insn[i].opcode =3D=3D J2_endloop0); is_endloop |=3D (pkt->insn[i].opcode =3D=3D J2_endloop1); =20 @@ -845,17 +845,17 @@ decode_set_slot_number(Packet *pkt) * slot0 for endloop */ if (!is_endloop) { - slot0_found =3D 1; + slot0_found =3D true; } } /* Is slot1 used? */ if (pkt->insn[i].slot =3D=3D 1) { - slot1_found =3D 1; + slot1_found =3D true; slot1_iidx =3D i; } } /* Is slot0 empty and slot1 used? */ - if ((slot0_found =3D=3D 0) && (slot1_found =3D=3D 1)) { + if ((!slot0_found) && slot1_found) { /* Then push it to slot0 */ pkt->insn[slot1_iidx].slot =3D 0; } @@ -873,7 +873,7 @@ int decode_packet(int max_words, const uint32_t *words,= Packet *pkt, { int num_insns =3D 0; int words_read =3D 0; - int end_of_packet =3D 0; + bool end_of_packet =3D false; int new_insns =3D 0; uint32_t encoding32; =20 @@ -890,7 +890,7 @@ int decode_packet(int max_words, const uint32_t *words,= Packet *pkt, * decode works */ if (pkt->insn[num_insns].opcode =3D=3D A4_ext) { - pkt->insn[num_insns + 1].extension_valid =3D 1; + pkt->insn[num_insns + 1].extension_valid =3D true; } num_insns +=3D new_insns; words_read++; @@ -913,7 +913,7 @@ int decode_packet(int max_words, const uint32_t *words,= Packet *pkt, decode_add_endloop_insn(&pkt->insn[pkt->num_insns++], 0); } if (words_read >=3D 3) { - uint32_t has_loop0, has_loop1; + bool has_loop0, has_loop1; has_loop0 =3D decode_parsebits_is_loopend(words[0]); has_loop1 =3D decode_parsebits_is_loopend(words[1]); if (has_loop0 && has_loop1) { diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h index 5756a1d..2e34591 100644 --- a/target/hexagon/insn.h +++ b/target/hexagon/insn.h @@ -40,14 +40,15 @@ struct Instruction { =20 uint32_t iclass:6; uint32_t slot:3; - uint32_t part1:1; /* + uint32_t which_extended:1; /* If has an extender, which immediate */ + uint32_t new_value_producer_slot:4; + + bool part1; /* * cmp-jumps are split into two insns. * set for the compare and clear for the jump */ - uint32_t extension_valid:1; /* Has a constant extender attached */ - uint32_t which_extended:1; /* If has an extender, which immediate */ - uint32_t is_endloop:1; /* This is an end of loop */ - uint32_t new_value_producer_slot:4; + bool extension_valid; /* Has a constant extender attached */ + bool is_endloop; /* This is an end of loop */ int32_t immed[IMMEDS_MAX]; /* immediate field */ }; =20 @@ -58,13 +59,13 @@ struct Packet { uint16_t encod_pkt_size_in_bytes; =20 /* Pre-decodes about COF */ - uint32_t pkt_has_cof:1; /* Has any change-of-flow */ - uint32_t pkt_has_endloop:1; + bool pkt_has_cof; /* Has any change-of-flow */ + bool pkt_has_endloop; =20 - uint32_t pkt_has_dczeroa:1; + bool pkt_has_dczeroa; =20 - uint32_t pkt_has_store_s0:1; - uint32_t pkt_has_store_s1:1; + bool pkt_has_store_s0; + bool pkt_has_store_s1; =20 Insn insn[INSTRUCTIONS_MAX]; }; diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 7361a07..6a364ea 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -948,8 +948,8 @@ static bool is_inf_prod(int32_t a, int32_t b) float32 HELPER(sffma_lib)(CPUHexagonState *env, float32 RxV, float32 RsV, float32 RtV) { - int infinp; - int infminusinf; + bool infinp; + bool infminusinf; float32 tmp; =20 arch_fpop_start(env); @@ -982,8 +982,8 @@ float32 HELPER(sffma_lib)(CPUHexagonState *env, float32= RxV, float32 HELPER(sffms_lib)(CPUHexagonState *env, float32 RxV, float32 RsV, float32 RtV) { - int infinp; - int infminusinf; + bool infinp; + bool infminusinf; float32 tmp; =20 arch_fpop_start(env); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 2d7ec12..f835341 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -178,7 +178,7 @@ static void gen_start_packet(DisasContext *ctx, Packet = *pkt) ctx->store_width[i] =3D 0; } tcg_gen_movi_tl(hex_pkt_has_store_s1, pkt->pkt_has_store_s1); - ctx->s1_store_processed =3D 0; + ctx->s1_store_processed =3D false; =20 #if HEX_DEBUG /* Handy place to set a breakpoint before the packet executes */ @@ -211,7 +211,7 @@ static void mark_implicit_reg_write(DisasContext *ctx, = Insn *insn, int attrib, int rnum) { if (GET_ATTRIB(insn->opcode, attrib)) { - int is_predicated =3D GET_ATTRIB(insn->opcode, A_CONDEXEC); + bool is_predicated =3D GET_ATTRIB(insn->opcode, A_CONDEXEC); if (is_predicated && !is_preloaded(ctx, rnum)) { tcg_gen_mov_tl(hex_new_value[rnum], hex_gpr[rnum]); } @@ -355,7 +355,7 @@ void process_store(DisasContext *ctx, Packet *pkt, int = slot_num) if (slot_num =3D=3D 1 && ctx->s1_store_processed) { return; } - ctx->s1_store_processed =3D 1; + ctx->s1_store_processed =3D true; =20 if (is_predicated) { TCGv cancelled =3D tcg_temp_new(); diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 0ecfbd7..97b12a7 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -36,7 +36,7 @@ typedef struct DisasContext { int preg_log_idx; DECLARE_BITMAP(pregs_written, NUM_PREGS); uint8_t store_width[STORES_MAX]; - uint8_t s1_store_processed; + bool s1_store_processed; } DisasContext; =20 static inline void ctx_log_reg_write(DisasContext *ctx, int rnum) --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616641712; cv=none; d=zohomail.com; s=zohoarc; b=FIN5ixNYBi24wJd8RlvCakAS+MkkgPN8L5i+2yhvh+XsCf28+Hc26l7UlpGkZd4AYCKprqdet5ZrX5N4G0BSR7nglBv26SEjnX1YCqIV+sqcmkuAJJnLigIbM+u/cSE1+17T8T3Qr8Dxb2rn+wL7e2mK+u4cFdswgFOKdfPeZOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616641712; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 06/15] Hexagon (target/hexagon) utility function changes Date: Wed, 24 Mar 2021 21:50:01 -0500 Message-Id: <1616640610-17319-7-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Remove unused carry_from_add64 function Change type of softfloat_roundingmodes Address feedback from Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/arch.c | 15 +-------------- target/hexagon/arch.h | 1 - target/hexagon/macros.h | 2 -- 3 files changed, 1 insertion(+), 17 deletions(-) diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index 09de124..bb51f19 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -76,19 +76,6 @@ uint64_t deinterleave(uint64_t src) return myeven | (myodd << 32); } =20 -uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c) -{ - uint64_t tmpa, tmpb, tmpc; - tmpa =3D fGETUWORD(0, a); - tmpb =3D fGETUWORD(0, b); - tmpc =3D tmpa + tmpb + c; - tmpa =3D fGETUWORD(1, a); - tmpb =3D fGETUWORD(1, b); - tmpc =3D tmpa + tmpb + fGETUWORD(1, tmpc); - tmpc =3D fGETUWORD(1, tmpc); - return tmpc; -} - int32_t conv_round(int32_t a, int n) { int64_t val; @@ -108,7 +95,7 @@ int32_t conv_round(int32_t a, int n) =20 /* Floating Point Stuff */ =20 -static const int softfloat_roundingmodes[] =3D { +static const FloatRoundMode softfloat_roundingmodes[] =3D { float_round_nearest_even, float_round_to_zero, float_round_down, diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h index 1f7f036..6e0b0d9 100644 --- a/target/hexagon/arch.h +++ b/target/hexagon/arch.h @@ -22,7 +22,6 @@ =20 uint64_t interleave(uint32_t odd, uint32_t even); uint64_t deinterleave(uint64_t src); -uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c); int32_t conv_round(int32_t a, int n); void arch_fpop_start(CPUHexagonState *env); void arch_fpop_end(CPUHexagonState *env); diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index cfcb817..8cb211d 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -341,8 +341,6 @@ static inline void gen_logical_not(TCGv dest, TCGv src) #define fWRITE_LC0(VAL) WRITE_RREG(HEX_REG_LC0, VAL) #define fWRITE_LC1(VAL) WRITE_RREG(HEX_REG_LC1, VAL) =20 -#define fCARRY_FROM_ADD(A, B, C) carry_from_add64(A, B, C) - #define fSET_OVERFLOW() SET_USR_FIELD(USR_OVF, 1) #define fSET_LPCFG(VAL) SET_USR_FIELD(USR_LPCFG, (VAL)) #define fGET_LPCFG (GET_USR_FIELD(USR_LPCFG)) --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; 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Wed, 24 Mar 2021 21:50:12 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640637; x=1648176637; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zv0c/bMh9A2p6l98XySvwf3wixFcSgRYJANVVKa4XaE=; b=mu6gRxJDd6BGDeFhPF8u2y7UHEXQ3B6D75/JvuHe7P2X0GZ4VfNorG/p fTWwnfAoclEUWevfr6A4TerAyoV9/v8f2EOcLPaOfi2/d8KvyokY3ly0r qpmGJINWZtLDPv3CETG+xeB0w6kjV/U0EnIzEt50q6Syoa42MVmATcfOt 8=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 07/15] Hexagon (target/hexagon) use softfloat default NaN and tininess Date: Wed, 24 Mar 2021 21:50:02 -0500 Message-Id: <1616640610-17319-8-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Address feedback from Richard Henderson Signed-off-by: Taylor Simpson --- fpu/softfloat-specialize.c.inc | 5 +++++ target/hexagon/cpu.c | 5 +++++ target/hexagon/op_helper.c | 47 --------------------------------------= ---- 3 files changed, 10 insertions(+), 47 deletions(-) diff --git a/fpu/softfloat-specialize.c.inc b/fpu/softfloat-specialize.c.inc index c2f87ad..c7ab148 100644 --- a/fpu/softfloat-specialize.c.inc +++ b/fpu/softfloat-specialize.c.inc @@ -145,6 +145,9 @@ static FloatParts parts_default_nan(float_status *statu= s) #elif defined(TARGET_HPPA) /* snan_bit_is_one, set msb-1. */ frac =3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#elif defined(TARGET_HEXAGON) + sign =3D 1; + frac =3D ~0ULL; #else /* This case is true for Alpha, ARM, MIPS, OpenRISC, PPC, RISC-V, * S390, SH4, TriCore, and Xtensa. I cannot find documentation @@ -180,6 +183,8 @@ static FloatParts parts_silence_nan(FloatParts a, float= _status *status) #if defined(TARGET_HPPA) a.frac &=3D ~(1ULL << (DECOMPOSED_BINARY_POINT - 1)); a.frac |=3D 1ULL << (DECOMPOSED_BINARY_POINT - 2); +#elif defined(TARGET_HEXAGON) + return parts_default_nan(status); #else if (snan_bit_is_one(status)) { return parts_default_nan(status); diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 002275a..ed829ce 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -23,6 +23,7 @@ #include "exec/exec-all.h" #include "qapi/error.h" #include "hw/qdev-properties.h" +#include "fpu/softfloat-helpers.h" =20 static void hexagon_v67_cpu_init(Object *obj) { @@ -205,8 +206,12 @@ static void hexagon_cpu_reset(DeviceState *dev) CPUState *cs =3D CPU(dev); HexagonCPU *cpu =3D HEXAGON_CPU(cs); HexagonCPUClass *mcc =3D HEXAGON_CPU_GET_CLASS(cpu); + CPUHexagonState *env =3D &cpu->env; =20 mcc->parent_reset(dev); + + set_default_nan_mode(1, &env->fp_status); + set_float_detect_tininess(float_tininess_before_rounding, &env->fp_sta= tus); } =20 static void hexagon_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 6a364ea..2ceca39 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -297,26 +297,6 @@ int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, = int32_t M, int32_t CS) } =20 /* - * Hexagon FP operations return ~0 instead of NaN - * The hex_check_sfnan/hex_check_dfnan functions perform this check - */ -static float32 hex_check_sfnan(float32 x) -{ - if (float32_is_any_nan(x)) { - return make_float32(0xFFFFFFFFU); - } - return x; -} - -static float64 hex_check_dfnan(float64 x) -{ - if (float64_is_any_nan(x)) { - return make_float64(0xFFFFFFFFFFFFFFFFULL); - } - return x; -} - -/* * mem_noshuf * Section 5.5 of the Hexagon V67 Programmer's Reference Manual * @@ -373,7 +353,6 @@ float64 HELPER(conv_sf2df)(CPUHexagonState *env, float3= 2 RsV) float64 out_f64; arch_fpop_start(env); out_f64 =3D float32_to_float64(RsV, &env->fp_status); - out_f64 =3D hex_check_dfnan(out_f64); arch_fpop_end(env); return out_f64; } @@ -383,7 +362,6 @@ float32 HELPER(conv_df2sf)(CPUHexagonState *env, float6= 4 RssV) float32 out_f32; arch_fpop_start(env); out_f32 =3D float64_to_float32(RssV, &env->fp_status); - out_f32 =3D hex_check_sfnan(out_f32); arch_fpop_end(env); return out_f32; } @@ -393,7 +371,6 @@ float32 HELPER(conv_uw2sf)(CPUHexagonState *env, int32_= t RsV) float32 RdV; arch_fpop_start(env); RdV =3D uint32_to_float32(RsV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -403,7 +380,6 @@ float64 HELPER(conv_uw2df)(CPUHexagonState *env, int32_= t RsV) float64 RddV; arch_fpop_start(env); RddV =3D uint32_to_float64(RsV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -413,7 +389,6 @@ float32 HELPER(conv_w2sf)(CPUHexagonState *env, int32_t= RsV) float32 RdV; arch_fpop_start(env); RdV =3D int32_to_float32(RsV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -423,7 +398,6 @@ float64 HELPER(conv_w2df)(CPUHexagonState *env, int32_t= RsV) float64 RddV; arch_fpop_start(env); RddV =3D int32_to_float64(RsV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -433,7 +407,6 @@ float32 HELPER(conv_ud2sf)(CPUHexagonState *env, int64_= t RssV) float32 RdV; arch_fpop_start(env); RdV =3D uint64_to_float32(RssV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -443,7 +416,6 @@ float64 HELPER(conv_ud2df)(CPUHexagonState *env, int64_= t RssV) float64 RddV; arch_fpop_start(env); RddV =3D uint64_to_float64(RssV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -453,7 +425,6 @@ float32 HELPER(conv_d2sf)(CPUHexagonState *env, int64_t= RssV) float32 RdV; arch_fpop_start(env); RdV =3D int64_to_float32(RssV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -463,7 +434,6 @@ float64 HELPER(conv_d2df)(CPUHexagonState *env, int64_t= RssV) float64 RddV; arch_fpop_start(env); RddV =3D int64_to_float64(RssV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -625,7 +595,6 @@ float32 HELPER(sfadd)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_add(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -635,7 +604,6 @@ float32 HELPER(sfsub)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_sub(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -687,7 +655,6 @@ float32 HELPER(sfmax)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_maxnum(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -697,7 +664,6 @@ float32 HELPER(sfmin)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D float32_minnum(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -764,7 +730,6 @@ float64 HELPER(dfadd)(CPUHexagonState *env, float64 Rss= V, float64 RttV) float64 RddV; arch_fpop_start(env); RddV =3D float64_add(RssV, RttV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -774,7 +739,6 @@ float64 HELPER(dfsub)(CPUHexagonState *env, float64 Rss= V, float64 RttV) float64 RddV; arch_fpop_start(env); RddV =3D float64_sub(RssV, RttV, &env->fp_status); - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -787,7 +751,6 @@ float64 HELPER(dfmax)(CPUHexagonState *env, float64 Rss= V, float64 RttV) if (float64_is_any_nan(RssV) || float64_is_any_nan(RttV)) { float_raise(float_flag_invalid, &env->fp_status); } - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -800,7 +763,6 @@ float64 HELPER(dfmin)(CPUHexagonState *env, float64 Rss= V, float64 RttV) if (float64_is_any_nan(RssV) || float64_is_any_nan(RttV)) { float_raise(float_flag_invalid, &env->fp_status); } - RddV =3D hex_check_dfnan(RddV); arch_fpop_end(env); return RddV; } @@ -876,7 +838,6 @@ float32 HELPER(sfmpy)(CPUHexagonState *env, float32 RsV= , float32 RtV) float32 RdV; arch_fpop_start(env); RdV =3D internal_mpyf(RsV, RtV, &env->fp_status); - RdV =3D hex_check_sfnan(RdV); arch_fpop_end(env); return RdV; } @@ -886,7 +847,6 @@ float32 HELPER(sffma)(CPUHexagonState *env, float32 RxV, { arch_fpop_start(env); RxV =3D internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); - RxV =3D hex_check_sfnan(RxV); arch_fpop_end(env); return RxV; } @@ -918,7 +878,6 @@ float32 HELPER(sffma_sc)(CPUHexagonState *env, float32 = RxV, RxV =3D check_nan(RxV, RsV, &env->fp_status); RxV =3D check_nan(RxV, RtV, &env->fp_status); tmp =3D internal_fmafx(RsV, RtV, RxV, fSXTN(8, 64, PuV), &env->fp_stat= us); - tmp =3D hex_check_sfnan(tmp); if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { RxV =3D tmp; } @@ -933,7 +892,6 @@ float32 HELPER(sffms)(CPUHexagonState *env, float32 RxV, arch_fpop_start(env); neg_RsV =3D float32_sub(float32_zero, RsV, &env->fp_status); RxV =3D internal_fmafx(neg_RsV, RtV, RxV, 0, &env->fp_status); - RxV =3D hex_check_sfnan(RxV); arch_fpop_end(env); return RxV; } @@ -964,7 +922,6 @@ float32 HELPER(sffma_lib)(CPUHexagonState *env, float32= RxV, RxV =3D check_nan(RxV, RsV, &env->fp_status); RxV =3D check_nan(RxV, RtV, &env->fp_status); tmp =3D internal_fmafx(RsV, RtV, RxV, 0, &env->fp_status); - tmp =3D hex_check_sfnan(tmp); if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { RxV =3D tmp; } @@ -999,7 +956,6 @@ float32 HELPER(sffms_lib)(CPUHexagonState *env, float32= RxV, RxV =3D check_nan(RxV, RtV, &env->fp_status); float32 minus_RsV =3D float32_sub(float32_zero, RsV, &env->fp_status); tmp =3D internal_fmafx(minus_RsV, RtV, RxV, 0, &env->fp_status); - tmp =3D hex_check_sfnan(tmp); if (!(float32_is_zero(RxV) && is_zero_prod(RsV, RtV))) { RxV =3D tmp; } @@ -1023,13 +979,11 @@ float64 HELPER(dfmpyfix)(CPUHexagonState *env, float= 64 RssV, float64 RttV) float64_is_normal(RttV)) { RddV =3D float64_mul(RssV, make_float64(0x4330000000000000), &env->fp_status); - RddV =3D hex_check_dfnan(RddV); } else if (float64_is_denormal(RttV) && (float64_getexp(RssV) >=3D 512) && float64_is_normal(RssV)) { RddV =3D float64_mul(RssV, make_float64(0x3cb0000000000000), &env->fp_status); - RddV =3D hex_check_dfnan(RddV); } else { RddV =3D RssV; } @@ -1042,7 +996,6 @@ float64 HELPER(dfmpyhh)(CPUHexagonState *env, float64 = RxxV, { arch_fpop_start(env); RxxV =3D internal_mpyhh(RssV, RttV, RxxV, &env->fp_status); - RxxV =3D hex_check_dfnan(RxxV); arch_fpop_end(env); return RxxV; } --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616641207; cv=none; d=zohomail.com; s=zohoarc; b=JCTZtJsMcizpkIw1tzCJXlk9QBamnrBHXu0euCp5p/W5Ksg7ePdSCa0u7ZrVSBxV7tr9vAa0sSIyBoQOkLL8DIz9+Vw8MScuuejYrIqcwslYXgzEx/ZjldTqlI02mwcsyBxOtkJ52sP6h1VvyAQJaiynIklJckgzEb03iUPTMsY= ARC-Message-Signature: i=1; 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i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640616; x=1648176616; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8Gc7OWL4e4CSUMeIzlN9hR2nRkf+HnkrEhtt/X3v1ms=; b=wBei8YfrVQbK6fsvR3UyeVLeMJKMqE6HfEleAt0fSsgnvBr0n/GMcDkB wCJaCOWsCFhUAxsUl/dEH+PxtnDCCHfpOxjWmUMZzEJSn+W+lytHAwYS4 ZWldEXT5xcLjh+zfDHTIMmtl+dT/kKgblxK2zD/zdWL+8o3RY33Xkk64e I=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 08/15] Hexagon (target/hexagon) replace float32_mul_pow2 with float32_scalbn Date: Wed, 24 Mar 2021 21:50:03 -0500 Message-Id: <1616640610-17319-9-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Address feedback from Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/arch.c | 28 +++++++++++----------------- 1 file changed, 11 insertions(+), 17 deletions(-) diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index bb51f19..40b6e3d 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -143,12 +143,6 @@ void arch_fpop_end(CPUHexagonState *env) } } =20 -static float32 float32_mul_pow2(float32 a, uint32_t p, float_status *fp_st= atus) -{ - float32 b =3D make_float32((SF_BIAS + p) << SF_MANTBITS); - return float32_mul(a, b, fp_status); -} - int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjus= t, float_status *fp_status) { @@ -217,22 +211,22 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, fl= oat32 *Rd, int *adjust, if ((n_exp - d_exp + SF_BIAS) <=3D SF_MANTBITS) { /* Near quotient underflow / inexact Q */ PeV =3D 0x80; - RtV =3D float32_mul_pow2(RtV, -64, fp_status); - RsV =3D float32_mul_pow2(RsV, 64, fp_status); + RtV =3D float32_scalbn(RtV, -64, fp_status); + RsV =3D float32_scalbn(RsV, 64, fp_status); } else if ((n_exp - d_exp + SF_BIAS) > (SF_MAXEXP - 24)) { /* Near quotient overflow */ PeV =3D 0x40; - RtV =3D float32_mul_pow2(RtV, 32, fp_status); - RsV =3D float32_mul_pow2(RsV, -32, fp_status); + RtV =3D float32_scalbn(RtV, 32, fp_status); + RsV =3D float32_scalbn(RsV, -32, fp_status); } else if (n_exp <=3D SF_MANTBITS + 2) { - RtV =3D float32_mul_pow2(RtV, 64, fp_status); - RsV =3D float32_mul_pow2(RsV, 64, fp_status); + RtV =3D float32_scalbn(RtV, 64, fp_status); + RsV =3D float32_scalbn(RsV, 64, fp_status); } else if (d_exp <=3D 1) { - RtV =3D float32_mul_pow2(RtV, 32, fp_status); - RsV =3D float32_mul_pow2(RsV, 32, fp_status); + RtV =3D float32_scalbn(RtV, 32, fp_status); + RsV =3D float32_scalbn(RsV, 32, fp_status); } else if (d_exp > 252) { - RtV =3D float32_mul_pow2(RtV, -32, fp_status); - RsV =3D float32_mul_pow2(RsV, -32, fp_status); + RtV =3D float32_scalbn(RtV, -32, fp_status); + RsV =3D float32_scalbn(RsV, -32, fp_status); } RdV =3D 0; ret =3D 1; @@ -274,7 +268,7 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, in= t *adjust, /* Basic checks passed */ r_exp =3D float32_getexp(RsV); if (r_exp <=3D 24) { - RsV =3D float32_mul_pow2(RsV, 64, fp_status); + RsV =3D float32_scalbn(RsV, 64, fp_status); PeV =3D 0xe0; } RdV =3D 0; --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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24 Mar 2021 19:50:13 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 24 Mar 2021 19:50:13 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 0BA2F1711; Wed, 24 Mar 2021 21:50:12 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640622; x=1648176622; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jiNc9kgzyZehu78WvkvpZSW4of/Vo42i1e4PkQKdlro=; b=ZNX57UZHEsg4AzAFuJOQrKxhPB/s3dXE08bI8pxhx8ZYf9H0hnbPFRSa +1eshDSVxoau7jDIcoTF42CScHHBaxoKGvhM8iPOlAV4mIhlJ9LWjg3Wo lL0pAopohfH6mtGqLlPwbFyp5EiPO2Pe6qb8FVyK5CCVMoJauRtJeaOFy U=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 09/15] Hexagon (target/hexagon) use softfloat for float-to-int conversions Date: Wed, 24 Mar 2021 21:50:04 -0500 Message-Id: <1616640610-17319-10-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Use the proper return for helpers that convert to unsigned Remove target/hexagon/conv_emu.[ch] Address feedback from Richard Henderson Signed-off-by: Taylor Simpson --- target/hexagon/conv_emu.c | 177 ----------------------------------------= ---- target/hexagon/conv_emu.h | 31 -------- target/hexagon/fma_emu.c | 1 - target/hexagon/helper.h | 16 ++-- target/hexagon/meson.build | 1 - target/hexagon/op_helper.c | 169 ++++++++++++++++++++++++++++++++--------= -- tests/tcg/hexagon/fpstuff.c | 145 ++++++++++++++++++++++++++++++++++++ 7 files changed, 281 insertions(+), 259 deletions(-) delete mode 100644 target/hexagon/conv_emu.c delete mode 100644 target/hexagon/conv_emu.h diff --git a/target/hexagon/conv_emu.c b/target/hexagon/conv_emu.c deleted file mode 100644 index 3985b10..0000000 --- a/target/hexagon/conv_emu.c +++ /dev/null @@ -1,177 +0,0 @@ -/* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#include "qemu/osdep.h" -#include "qemu/host-utils.h" -#include "fpu/softfloat.h" -#include "macros.h" -#include "conv_emu.h" - -#define LL_MAX_POS 0x7fffffffffffffffULL -#define MAX_POS 0x7fffffffU - -static uint64_t conv_f64_to_8u_n(float64 in, int will_negate, - float_status *fp_status) -{ - uint8_t sign =3D float64_is_neg(in); - if (float64_is_infinity(in)) { - float_raise(float_flag_invalid, fp_status); - if (float64_is_neg(in)) { - return 0ULL; - } else { - return ~0ULL; - } - } - if (float64_is_any_nan(in)) { - float_raise(float_flag_invalid, fp_status); - return ~0ULL; - } - if (float64_is_zero(in)) { - return 0; - } - if (sign) { - float_raise(float_flag_invalid, fp_status); - return 0; - } - if (float64_lt(in, float64_half, fp_status)) { - /* Near zero, captures large fracshifts, denorms, etc */ - float_raise(float_flag_inexact, fp_status); - switch (get_float_rounding_mode(fp_status)) { - case float_round_down: - if (will_negate) { - return 1; - } else { - return 0; - } - case float_round_up: - if (!will_negate) { - return 1; - } else { - return 0; - } - default: - return 0; /* nearest or towards zero */ - } - } - return float64_to_uint64(in, fp_status); -} - -static void clr_float_exception_flags(uint8_t flag, float_status *fp_statu= s) -{ - uint8_t flags =3D fp_status->float_exception_flags; - flags &=3D ~flag; - set_float_exception_flags(flags, fp_status); -} - -static uint32_t conv_df_to_4u_n(float64 fp64, int will_negate, - float_status *fp_status) -{ - uint64_t tmp; - tmp =3D conv_f64_to_8u_n(fp64, will_negate, fp_status); - if (tmp > 0x00000000ffffffffULL) { - clr_float_exception_flags(float_flag_inexact, fp_status); - float_raise(float_flag_invalid, fp_status); - return ~0U; - } - return (uint32_t)tmp; -} - -uint64_t conv_df_to_8u(float64 in, float_status *fp_status) -{ - return conv_f64_to_8u_n(in, 0, fp_status); -} - -uint32_t conv_df_to_4u(float64 in, float_status *fp_status) -{ - return conv_df_to_4u_n(in, 0, fp_status); -} - -int64_t conv_df_to_8s(float64 in, float_status *fp_status) -{ - uint8_t sign =3D float64_is_neg(in); - uint64_t tmp; - if (float64_is_any_nan(in)) { - float_raise(float_flag_invalid, fp_status); - return -1; - } - if (sign) { - float64 minus_fp64 =3D float64_abs(in); - tmp =3D conv_f64_to_8u_n(minus_fp64, 1, fp_status); - } else { - tmp =3D conv_f64_to_8u_n(in, 0, fp_status); - } - if (tmp > (LL_MAX_POS + sign)) { - clr_float_exception_flags(float_flag_inexact, fp_status); - float_raise(float_flag_invalid, fp_status); - tmp =3D (LL_MAX_POS + sign); - } - if (sign) { - return -tmp; - } else { - return tmp; - } -} - -int32_t conv_df_to_4s(float64 in, float_status *fp_status) -{ - uint8_t sign =3D float64_is_neg(in); - uint64_t tmp; - if (float64_is_any_nan(in)) { - float_raise(float_flag_invalid, fp_status); - return -1; - } - if (sign) { - float64 minus_fp64 =3D float64_abs(in); - tmp =3D conv_f64_to_8u_n(minus_fp64, 1, fp_status); - } else { - tmp =3D conv_f64_to_8u_n(in, 0, fp_status); - } - if (tmp > (MAX_POS + sign)) { - clr_float_exception_flags(float_flag_inexact, fp_status); - float_raise(float_flag_invalid, fp_status); - tmp =3D (MAX_POS + sign); - } - if (sign) { - return -tmp; - } else { - return tmp; - } -} - -uint64_t conv_sf_to_8u(float32 in, float_status *fp_status) -{ - float64 fp64 =3D float32_to_float64(in, fp_status); - return conv_df_to_8u(fp64, fp_status); -} - -uint32_t conv_sf_to_4u(float32 in, float_status *fp_status) -{ - float64 fp64 =3D float32_to_float64(in, fp_status); - return conv_df_to_4u(fp64, fp_status); -} - -int64_t conv_sf_to_8s(float32 in, float_status *fp_status) -{ - float64 fp64 =3D float32_to_float64(in, fp_status); - return conv_df_to_8s(fp64, fp_status); -} - -int32_t conv_sf_to_4s(float32 in, float_status *fp_status) -{ - float64 fp64 =3D float32_to_float64(in, fp_status); - return conv_df_to_4s(fp64, fp_status); -} diff --git a/target/hexagon/conv_emu.h b/target/hexagon/conv_emu.h deleted file mode 100644 index cade9de..0000000 --- a/target/hexagon/conv_emu.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, see . - */ - -#ifndef HEXAGON_CONV_EMU_H -#define HEXAGON_CONV_EMU_H - -uint64_t conv_sf_to_8u(float32 in, float_status *fp_status); -uint32_t conv_sf_to_4u(float32 in, float_status *fp_status); -int64_t conv_sf_to_8s(float32 in, float_status *fp_status); -int32_t conv_sf_to_4s(float32 in, float_status *fp_status); - -uint64_t conv_df_to_8u(float64 in, float_status *fp_status); -uint32_t conv_df_to_4u(float64 in, float_status *fp_status); -int64_t conv_df_to_8s(float64 in, float_status *fp_status); -int32_t conv_df_to_4s(float64 in, float_status *fp_status); - -#endif diff --git a/target/hexagon/fma_emu.c b/target/hexagon/fma_emu.c index f324b83..d3b45d4 100644 --- a/target/hexagon/fma_emu.c +++ b/target/hexagon/fma_emu.c @@ -19,7 +19,6 @@ #include "qemu/int128.h" #include "fpu/softfloat.h" #include "macros.h" -#include "conv_emu.h" #include "fma_emu.h" =20 #define DF_INF_EXP 0x7ff diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index a5f340c..715c246 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -38,21 +38,21 @@ DEF_HELPER_2(conv_ud2sf, f32, env, s64) DEF_HELPER_2(conv_ud2df, f64, env, s64) DEF_HELPER_2(conv_d2sf, f32, env, s64) DEF_HELPER_2(conv_d2df, f64, env, s64) -DEF_HELPER_2(conv_sf2uw, s32, env, f32) +DEF_HELPER_2(conv_sf2uw, i32, env, f32) DEF_HELPER_2(conv_sf2w, s32, env, f32) -DEF_HELPER_2(conv_sf2ud, s64, env, f32) +DEF_HELPER_2(conv_sf2ud, i64, env, f32) DEF_HELPER_2(conv_sf2d, s64, env, f32) -DEF_HELPER_2(conv_df2uw, s32, env, f64) +DEF_HELPER_2(conv_df2uw, i32, env, f64) DEF_HELPER_2(conv_df2w, s32, env, f64) -DEF_HELPER_2(conv_df2ud, s64, env, f64) +DEF_HELPER_2(conv_df2ud, i64, env, f64) DEF_HELPER_2(conv_df2d, s64, env, f64) -DEF_HELPER_2(conv_sf2uw_chop, s32, env, f32) +DEF_HELPER_2(conv_sf2uw_chop, i32, env, f32) DEF_HELPER_2(conv_sf2w_chop, s32, env, f32) -DEF_HELPER_2(conv_sf2ud_chop, s64, env, f32) +DEF_HELPER_2(conv_sf2ud_chop, i64, env, f32) DEF_HELPER_2(conv_sf2d_chop, s64, env, f32) -DEF_HELPER_2(conv_df2uw_chop, s32, env, f64) +DEF_HELPER_2(conv_df2uw_chop, i32, env, f64) DEF_HELPER_2(conv_df2w_chop, s32, env, f64) -DEF_HELPER_2(conv_df2ud_chop, s64, env, f64) +DEF_HELPER_2(conv_df2ud_chop, i64, env, f64) DEF_HELPER_2(conv_df2d_chop, s64, env, f64) DEF_HELPER_3(sfadd, f32, env, f32, f32) DEF_HELPER_3(sfsub, f32, env, f32, f32) diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index 15318a6..7b380fc 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -185,7 +185,6 @@ hexagon_ss.add(files( 'printinsn.c', 'arch.c', 'fma_emu.c', - 'conv_emu.c', )) =20 target_arch +=3D {'hexagon': hexagon_ss} diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 2ceca39..5bc9a93 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -25,7 +25,6 @@ #include "arch.h" #include "hex_arch_types.h" #include "fma_emu.h" -#include "conv_emu.h" =20 #define SF_BIAS 127 #define SF_MANTBITS 23 @@ -438,11 +437,17 @@ float64 HELPER(conv_d2df)(CPUHexagonState *env, int64= _t RssV) return RddV; } =20 -int32_t HELPER(conv_sf2uw)(CPUHexagonState *env, float32 RsV) +uint32_t HELPER(conv_sf2uw)(CPUHexagonState *env, float32 RsV) { - int32_t RdV; + uint32_t RdV; arch_fpop_start(env); - RdV =3D conv_sf_to_4u(RsV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D 0; + } else { + RdV =3D float32_to_uint32(RsV, &env->fp_status); + } arch_fpop_end(env); return RdV; } @@ -451,16 +456,28 @@ int32_t HELPER(conv_sf2w)(CPUHexagonState *env, float= 32 RsV) { int32_t RdV; arch_fpop_start(env); - RdV =3D conv_sf_to_4s(RsV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D -1; + } else { + RdV =3D float32_to_int32(RsV, &env->fp_status); + } arch_fpop_end(env); return RdV; } =20 -int64_t HELPER(conv_sf2ud)(CPUHexagonState *env, float32 RsV) +uint64_t HELPER(conv_sf2ud)(CPUHexagonState *env, float32 RsV) { - int64_t RddV; + uint64_t RddV; arch_fpop_start(env); - RddV =3D conv_sf_to_8u(RsV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D 0; + } else { + RddV =3D float32_to_uint64(RsV, &env->fp_status); + } arch_fpop_end(env); return RddV; } @@ -469,16 +486,28 @@ int64_t HELPER(conv_sf2d)(CPUHexagonState *env, float= 32 RsV) { int64_t RddV; arch_fpop_start(env); - RddV =3D conv_sf_to_8s(RsV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D -1; + } else { + RddV =3D float32_to_int64(RsV, &env->fp_status); + } arch_fpop_end(env); return RddV; } =20 -int32_t HELPER(conv_df2uw)(CPUHexagonState *env, float64 RssV) +uint32_t HELPER(conv_df2uw)(CPUHexagonState *env, float64 RssV) { - int32_t RdV; + uint32_t RdV; arch_fpop_start(env); - RdV =3D conv_df_to_4u(RssV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D 0; + } else { + RdV =3D float64_to_uint32(RssV, &env->fp_status); + } arch_fpop_end(env); return RdV; } @@ -487,16 +516,28 @@ int32_t HELPER(conv_df2w)(CPUHexagonState *env, float= 64 RssV) { int32_t RdV; arch_fpop_start(env); - RdV =3D conv_df_to_4s(RssV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float64_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D -1; + } else { + RdV =3D float64_to_int32(RssV, &env->fp_status); + } arch_fpop_end(env); return RdV; } =20 -int64_t HELPER(conv_df2ud)(CPUHexagonState *env, float64 RssV) +uint64_t HELPER(conv_df2ud)(CPUHexagonState *env, float64 RssV) { - int64_t RddV; + uint64_t RddV; arch_fpop_start(env); - RddV =3D conv_df_to_8u(RssV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D 0; + } else { + RddV =3D float64_to_uint64(RssV, &env->fp_status); + } arch_fpop_end(env); return RddV; } @@ -505,17 +546,28 @@ int64_t HELPER(conv_df2d)(CPUHexagonState *env, float= 64 RssV) { int64_t RddV; arch_fpop_start(env); - RddV =3D conv_df_to_8s(RssV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float64_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D -1; + } else { + RddV =3D float64_to_int64(RssV, &env->fp_status); + } arch_fpop_end(env); return RddV; } =20 -int32_t HELPER(conv_sf2uw_chop)(CPUHexagonState *env, float32 RsV) +uint32_t HELPER(conv_sf2uw_chop)(CPUHexagonState *env, float32 RsV) { - int32_t RdV; + uint32_t RdV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RdV =3D conv_sf_to_4u(RsV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D 0; + } else { + RdV =3D float32_to_uint32_round_to_zero(RsV, &env->fp_status); + } arch_fpop_end(env); return RdV; } @@ -524,18 +576,28 @@ int32_t HELPER(conv_sf2w_chop)(CPUHexagonState *env, = float32 RsV) { int32_t RdV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RdV =3D conv_sf_to_4s(RsV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D -1; + } else { + RdV =3D float32_to_int32_round_to_zero(RsV, &env->fp_status); + } arch_fpop_end(env); return RdV; } =20 -int64_t HELPER(conv_sf2ud_chop)(CPUHexagonState *env, float32 RsV) +uint64_t HELPER(conv_sf2ud_chop)(CPUHexagonState *env, float32 RsV) { - int64_t RddV; + uint64_t RddV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RddV =3D conv_sf_to_8u(RsV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float32_is_neg(RsV) && !float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D 0; + } else { + RddV =3D float32_to_uint64_round_to_zero(RsV, &env->fp_status); + } arch_fpop_end(env); return RddV; } @@ -544,18 +606,28 @@ int64_t HELPER(conv_sf2d_chop)(CPUHexagonState *env, = float32 RsV) { int64_t RddV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RddV =3D conv_sf_to_8s(RsV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float32_is_any_nan(RsV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D -1; + } else { + RddV =3D float32_to_int64_round_to_zero(RsV, &env->fp_status); + } arch_fpop_end(env); return RddV; } =20 -int32_t HELPER(conv_df2uw_chop)(CPUHexagonState *env, float64 RssV) +uint32_t HELPER(conv_df2uw_chop)(CPUHexagonState *env, float64 RssV) { - int32_t RdV; + uint32_t RdV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RdV =3D conv_df_to_4u(RssV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float64_is_neg(RssV) && !float32_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D 0; + } else { + RdV =3D float64_to_uint32_round_to_zero(RssV, &env->fp_status); + } arch_fpop_end(env); return RdV; } @@ -564,18 +636,28 @@ int32_t HELPER(conv_df2w_chop)(CPUHexagonState *env, = float64 RssV) { int32_t RdV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RdV =3D conv_df_to_4s(RssV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float64_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RdV =3D -1; + } else { + RdV =3D float64_to_int32_round_to_zero(RssV, &env->fp_status); + } arch_fpop_end(env); return RdV; } =20 -int64_t HELPER(conv_df2ud_chop)(CPUHexagonState *env, float64 RssV) +uint64_t HELPER(conv_df2ud_chop)(CPUHexagonState *env, float64 RssV) { - int64_t RddV; + uint64_t RddV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RddV =3D conv_df_to_8u(RssV, &env->fp_status); + /* Hexagon checks the sign before rounding */ + if (float64_is_neg(RssV) && !float64_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D 0; + } else { + RddV =3D float64_to_uint64_round_to_zero(RssV, &env->fp_status); + } arch_fpop_end(env); return RddV; } @@ -584,8 +666,13 @@ int64_t HELPER(conv_df2d_chop)(CPUHexagonState *env, f= loat64 RssV) { int64_t RddV; arch_fpop_start(env); - set_float_rounding_mode(float_round_to_zero, &env->fp_status); - RddV =3D conv_df_to_8s(RssV, &env->fp_status); + /* Hexagon returns -1 for NaN */ + if (float64_is_any_nan(RssV)) { + float_raise(float_flag_invalid, &env->fp_status); + RddV =3D -1; + } else { + RddV =3D float64_to_int64_round_to_zero(RssV, &env->fp_status); + } arch_fpop_end(env); return RddV; } diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index e4f1a0e..6b60f92 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -37,10 +37,12 @@ const int SF_NaN =3D 0x7fc00000; const int SF_NaN_special =3D 0x7f800001; const int SF_ANY =3D 0x3f800000; const int SF_HEX_NAN =3D 0xffffffff; +const int SF_small_neg =3D 0xab98fba8; =20 const long long DF_NaN =3D 0x7ff8000000000000ULL; const long long DF_ANY =3D 0x3f80000000000000ULL; const long long DF_HEX_NAN =3D 0xffffffffffffffffULL; +const long long DF_small_neg =3D 0xbd731f7500000000ULL; =20 int err; =20 @@ -358,12 +360,155 @@ static void check_canonical_NaN(void) check_fpstatus(usr, 0); } =20 +static void check_float2int_convs() +{ + int res32; + long long res64; + int usr; + + /* + * Check that the various forms of float-to-unsigned + * check sign before rounding + */ + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2uw(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(SF_small_neg) + : "r2", "usr"); + check32(res32, 0); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2uw(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(SF_small_neg) + : "r2", "usr"); + check32(res32, 0); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2ud(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(SF_small_neg) + : "r2", "usr"); + check64(res64, 0); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2ud(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(SF_small_neg) + : "r2", "usr"); + check64(res64, 0); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2uw(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_small_neg) + : "r2", "usr"); + check32(res32, 0); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2uw(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_small_neg) + : "r2", "usr"); + check32(res32, 0); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2ud(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_small_neg) + : "r2", "usr"); + check64(res64, 0); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2ud(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_small_neg) + : "r2", "usr"); + check64(res64, 0); + check_fpstatus(usr, FPINVF); + + /* + * Check that the various forms of float-to-signed return -1 for NaN + */ + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2w(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(SF_NaN) + : "r2", "usr"); + check32(res32, -1); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2w(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(SF_NaN) + : "r2", "usr"); + check32(res32, -1); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2d(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(SF_NaN) + : "r2", "usr"); + check64(res64, -1); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2d(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(SF_NaN) + : "r2", "usr"); + check64(res64, -1); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2w(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_NaN) + : "r2", "usr"); + check32(res32, -1); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2w(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_NaN) + : "r2", "usr"); + check32(res32, -1); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2d(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_NaN) + : "r2", "usr"); + check64(res64, -1); + check_fpstatus(usr, FPINVF); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2d(%2):chop\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_NaN) + : "r2", "usr"); + check64(res64, -1); + check_fpstatus(usr, FPINVF); +} + int main() { check_compare_exception(); check_sfminmax(); check_dfminmax(); check_canonical_NaN(); + check_float2int_convs(); =20 puts(err ? "FAIL" : "PASS"); return err ? 1 : 0; --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616642085; cv=none; d=zohomail.com; s=zohoarc; b=GP5A/PAnhgJV4MKS3kWg9oDr/8vmZJxgTeTfIur63HipbmqT5cYN4wNTSLmvZnd+b06fMpb6V6JnbXTL/0iMkoWLTTxO35N0TlWXkFFlvnKtV2yfLDd6pjw1rRs6Xo896aWmYV5n8JxV0cWEx7yGXk10VXwnjAgkNMhkRKafajo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616642085; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kjbH84mUl/0NgRK8bdL0QgXvWjnXFfpOdzcxJHphvC0=; b=V+Z1zGIbgYHQmZwoaPujjNpdl2Hm6KETtEbQb020Sy9tQ5F3djXhYAuetEM8RqgS4Lw4DtPvnE8t2AsWdgqenHJ/QLNZA5k3FcBi44wFxxvaXRACrG+pvwMWtvigRWRXFKtr88P7HcA0yzG6N0Ne92ASkJ4T3SEcHF0lORsdVM0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1616642085895695.1223771027326; Wed, 24 Mar 2021 20:14:45 -0700 (PDT) Received: from localhost ([::1]:58198 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lPGSK-0003Sn-DY for importer@patchew.org; Wed, 24 Mar 2021 23:14:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPG56-0003bs-BB for qemu-devel@nongnu.org; Wed, 24 Mar 2021 22:50:44 -0400 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:22812) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1lPG4y-0002dD-Fs for qemu-devel@nongnu.org; Wed, 24 Mar 2021 22:50:44 -0400 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-02.qualcomm.com with ESMTP; 24 Mar 2021 19:50:14 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 24 Mar 2021 19:50:13 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 0EAA31713; Wed, 24 Mar 2021 21:50:12 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640636; x=1648176636; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=txk2LVHnaZQSu2qcyZtZZZkfa4yk1+GdGPNXwmWpg2Y=; b=aUrU14abM4XLDVVWqEFIqQvNH4XlYPNXo/05DWMH5Prk4AqyZynidmlO 5kRtp5EnI4FHQkAJZvSQsPIIVGHz9WsI4zr1AtEuS6SdBjSdrzWUxKnNU /eXkwzPGD3xpj9z4ZS3Mz0o+k93XyP3xSiUaZ2X9Hhno8ghzHOFO3765Q A=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 10/15] Hexagon (target/hexagon) instructions with multiple definitions Date: Wed, 24 Mar 2021 21:50:05 -0500 Message-Id: <1616640610-17319-11-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Instructions with multiple definitions require special handling because the generator wants to create a helper, but helpers can only return a single result. Therefore, we must override the generated code. The following instructions are added A4_addp_c Rdd32 =3D add(Rss32, Rtt32, Px4):carry Add with carry A4_subp_c Rdd32 =3D sub(Rss32, Rtt32, Px4):carry Sub with carry A5_ACS Rxx32,Pe4 =3D vacsh(Rss32, Rtt32) Add compare and select elements of two vectors A6_vminub_RdP Rdd32,Pe4 =3D vminub(Rtt32, Rss32) Vector min of bytes F2_invsqrta Rd32,Pe4 =3D sfinvsqrta(Rs32) Square root approx F2_sfrecipa Rd32,Pe4 =3D sfrecipa(Rs32, Rt32) Recripocal approx Test cases in tests/tcg/hexagon/multi_result.c FP exception tests added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson --- target/hexagon/arch.c | 57 +++++++- target/hexagon/arch.h | 2 + target/hexagon/gen_tcg.h | 107 +++++++++++++++ target/hexagon/genptr.c | 111 +++++++++++++++ target/hexagon/helper.h | 6 + target/hexagon/imported/alu.idef | 44 ++++++ target/hexagon/imported/encode_pp.def | 6 + target/hexagon/imported/float.idef | 32 +++++ target/hexagon/macros.h | 41 ++++++ target/hexagon/op_helper.c | 130 ++++++++++++++++++ tests/tcg/hexagon/Makefile.target | 1 + tests/tcg/hexagon/fpstuff.c | 97 +++++++++++++ tests/tcg/hexagon/multi_result.c | 249 ++++++++++++++++++++++++++++++= ++++ 13 files changed, 879 insertions(+), 4 deletions(-) create mode 100644 tests/tcg/hexagon/multi_result.c diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index 40b6e3d..d756dfa 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -181,12 +181,13 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, fl= oat32 *Rd, int *adjust, /* or put Inf in num fixup? */ uint8_t RsV_sign =3D float32_is_neg(RsV); uint8_t RtV_sign =3D float32_is_neg(RtV); + /* Check that RsV is NOT infinite before we overwrite it */ + if (!float32_is_infinity(RsV)) { + float_raise(float_flag_divbyzero, fp_status); + } RsV =3D infinite_float32(RsV_sign ^ RtV_sign); RtV =3D float32_one; RdV =3D float32_one; - if (float32_is_infinity(RsV)) { - float_raise(float_flag_divbyzero, fp_status); - } } else if (float32_is_infinity(RtV)) { RsV =3D make_float32(0x80000000 & (RsV ^ RtV)); RtV =3D float32_one; @@ -246,7 +247,7 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, in= t *adjust, int r_exp; int ret =3D 0; RsV =3D *Rs; - if (float32_is_infinity(RsV)) { + if (float32_is_any_nan(RsV)) { if (extract32(RsV, 22, 1) =3D=3D 0) { float_raise(float_flag_invalid, fp_status); } @@ -279,3 +280,51 @@ int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, i= nt *adjust, *adjust =3D PeV; return ret; } + +int arch_recip_lookup(int index) +{ + index &=3D 0x7f; + unsigned const int roundrom[128] =3D { + 0x0fe, 0x0fa, 0x0f6, 0x0f2, 0x0ef, 0x0eb, 0x0e7, 0x0e4, + 0x0e0, 0x0dd, 0x0d9, 0x0d6, 0x0d2, 0x0cf, 0x0cc, 0x0c9, + 0x0c6, 0x0c2, 0x0bf, 0x0bc, 0x0b9, 0x0b6, 0x0b3, 0x0b1, + 0x0ae, 0x0ab, 0x0a8, 0x0a5, 0x0a3, 0x0a0, 0x09d, 0x09b, + 0x098, 0x096, 0x093, 0x091, 0x08e, 0x08c, 0x08a, 0x087, + 0x085, 0x083, 0x080, 0x07e, 0x07c, 0x07a, 0x078, 0x075, + 0x073, 0x071, 0x06f, 0x06d, 0x06b, 0x069, 0x067, 0x065, + 0x063, 0x061, 0x05f, 0x05e, 0x05c, 0x05a, 0x058, 0x056, + 0x054, 0x053, 0x051, 0x04f, 0x04e, 0x04c, 0x04a, 0x049, + 0x047, 0x045, 0x044, 0x042, 0x040, 0x03f, 0x03d, 0x03c, + 0x03a, 0x039, 0x037, 0x036, 0x034, 0x033, 0x032, 0x030, + 0x02f, 0x02d, 0x02c, 0x02b, 0x029, 0x028, 0x027, 0x025, + 0x024, 0x023, 0x021, 0x020, 0x01f, 0x01e, 0x01c, 0x01b, + 0x01a, 0x019, 0x017, 0x016, 0x015, 0x014, 0x013, 0x012, + 0x011, 0x00f, 0x00e, 0x00d, 0x00c, 0x00b, 0x00a, 0x009, + 0x008, 0x007, 0x006, 0x005, 0x004, 0x003, 0x002, 0x000, + }; + return roundrom[index]; +}; + +int arch_invsqrt_lookup(int index) +{ + index &=3D 0x7f; + unsigned const int roundrom[128] =3D { + 0x069, 0x066, 0x063, 0x061, 0x05e, 0x05b, 0x059, 0x057, + 0x054, 0x052, 0x050, 0x04d, 0x04b, 0x049, 0x047, 0x045, + 0x043, 0x041, 0x03f, 0x03d, 0x03b, 0x039, 0x037, 0x036, + 0x034, 0x032, 0x030, 0x02f, 0x02d, 0x02c, 0x02a, 0x028, + 0x027, 0x025, 0x024, 0x022, 0x021, 0x01f, 0x01e, 0x01d, + 0x01b, 0x01a, 0x019, 0x017, 0x016, 0x015, 0x014, 0x012, + 0x011, 0x010, 0x00f, 0x00d, 0x00c, 0x00b, 0x00a, 0x009, + 0x008, 0x007, 0x006, 0x005, 0x004, 0x003, 0x002, 0x001, + 0x0fe, 0x0fa, 0x0f6, 0x0f3, 0x0ef, 0x0eb, 0x0e8, 0x0e4, + 0x0e1, 0x0de, 0x0db, 0x0d7, 0x0d4, 0x0d1, 0x0ce, 0x0cb, + 0x0c9, 0x0c6, 0x0c3, 0x0c0, 0x0be, 0x0bb, 0x0b8, 0x0b6, + 0x0b3, 0x0b1, 0x0af, 0x0ac, 0x0aa, 0x0a8, 0x0a5, 0x0a3, + 0x0a1, 0x09f, 0x09d, 0x09b, 0x099, 0x097, 0x095, 0x093, + 0x091, 0x08f, 0x08d, 0x08b, 0x089, 0x087, 0x086, 0x084, + 0x082, 0x080, 0x07f, 0x07d, 0x07b, 0x07a, 0x078, 0x077, + 0x075, 0x074, 0x072, 0x071, 0x06f, 0x06e, 0x06c, 0x06b, + }; + return roundrom[index]; +}; diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h index 6e0b0d9..544288e 100644 --- a/target/hexagon/arch.h +++ b/target/hexagon/arch.h @@ -29,5 +29,7 @@ int arch_sf_recip_common(float32 *Rs, float32 *Rt, float3= 2 *Rd, int *adjust, float_status *fp_status); int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, float_status *fp_status); +int arch_recip_lookup(int index); +int arch_invsqrt_lookup(int index); =20 #endif diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index a30048e..0b2c2ca 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -195,6 +195,113 @@ #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) =20 +/* + * Mathematical operations with more than one definition require + * special handling + */ +#define fGEN_TCG_A5_ACS(SHORTCODE) \ + do { \ + gen_helper_vacsh_val(RxxV, cpu_env, RxxV, RssV, RttV); \ + gen_helper_vacsh_pred(PeV, cpu_env, RxxV, RssV, RttV); \ + } while (0) + +/* + * Approximate reciprocal + * r3,p1 =3D sfrecipa(r0, r1) + */ +#define fGEN_TCG_F2_sfrecipa(SHORTCODE) \ + do { \ + gen_helper_sfrecipa_val(RdV, cpu_env, RsV, RtV); \ + gen_helper_sfrecipa_pred(PeV, cpu_env, RsV, RtV); \ + } while (0) + +/* + * Approximation of the reciprocal square root + * r1,p0 =3D sfinvsqrta(r0) + */ +#define fGEN_TCG_F2_sfinvsqrta(SHORTCODE) \ + do { \ + gen_helper_sfinvsqrta_val(RdV, cpu_env, RsV); \ + gen_helper_sfinvsqrta_pred(PeV, cpu_env, RsV); \ + } while (0) + +/* + * Add or subtract with carry. + * Predicate register is used as an extra input and output. + * r5:4 =3D add(r1:0, r3:2, p1):carry + */ +#define fGEN_TCG_A4_addp_c(SHORTCODE) \ + do { \ + TCGv LSB =3D tcg_temp_new(); \ + TCGv_i64 LSB_i64 =3D tcg_temp_new_i64(); \ + TCGv_i64 tmp_i64 =3D tcg_temp_new_i64(); \ + TCGv tmp =3D tcg_temp_new(); \ + tcg_gen_add_i64(RddV, RssV, RttV); \ + fLSBOLD(PxV); \ + tcg_gen_extu_i32_i64(LSB_i64, LSB); \ + tcg_gen_add_i64(RddV, RddV, LSB_i64); \ + gen_carry_from_add64(tmp_i64, RssV, RttV, LSB_i64); \ + tcg_gen_extrl_i64_i32(tmp, tmp_i64); \ + f8BITSOF(PxV, tmp); \ + tcg_temp_free(LSB); \ + tcg_temp_free_i64(LSB_i64); \ + tcg_temp_free_i64(tmp_i64); \ + tcg_temp_free(tmp); \ + } while (0) + +/* r5:4 =3D sub(r1:0, r3:2, p1):carry */ +#define fGEN_TCG_A4_subp_c(SHORTCODE) \ + do { \ + TCGv LSB =3D tcg_temp_new(); \ + TCGv_i64 LSB_i64 =3D tcg_temp_new_i64(); \ + TCGv_i64 tmp_i64 =3D tcg_temp_new_i64(); \ + TCGv tmp =3D tcg_temp_new(); \ + tcg_gen_not_i64(tmp_i64, RttV); \ + tcg_gen_add_i64(RddV, RssV, tmp_i64); \ + fLSBOLD(PxV); \ + tcg_gen_extu_i32_i64(LSB_i64, LSB); \ + tcg_gen_add_i64(RddV, RddV, LSB_i64); \ + gen_carry_from_add64(tmp_i64, RssV, tmp_i64, LSB_i64); \ + tcg_gen_extrl_i64_i32(tmp, tmp_i64); \ + f8BITSOF(PxV, tmp); \ + tcg_temp_free(LSB); \ + tcg_temp_free_i64(LSB_i64); \ + tcg_temp_free_i64(tmp_i64); \ + tcg_temp_free(tmp); \ + } while (0) + +/* + * Compare each of the 8 unsigned bytes + * The minimum is placed in each byte of the destination. + * Each bit of the predicate is set true if the bit from the first operand + * is greater than the bit from the second operand. + * r5:4,p1 =3D vminub(r1:0, r3:2) + */ +#define fGEN_TCG_A6_vminub_RdP(SHORTCODE) \ + do { \ + TCGv BYTE =3D tcg_temp_new(); \ + TCGv left =3D tcg_temp_new(); \ + TCGv right =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + int i; \ + tcg_gen_movi_tl(PeV, 0); \ + tcg_gen_movi_i64(RddV, 0); \ + for (i =3D 0; i < 8; i++) { \ + fGETUBYTE(i, RttV); \ + tcg_gen_mov_tl(left, BYTE); \ + fGETUBYTE(i, RssV); \ + tcg_gen_mov_tl(right, BYTE); \ + tcg_gen_setcond_tl(TCG_COND_GT, tmp, left, right); \ + fSETBIT(i, PeV, tmp); \ + fMIN(tmp, left, right); \ + fSETBYTE(i, RddV, tmp); \ + } \ + tcg_temp_free(BYTE); \ + tcg_temp_free(left); \ + tcg_temp_free(right); \ + tcg_temp_free(tmp); \ + } while (0) + /* Floating point */ #define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ gen_helper_conv_sf2df(RddV, cpu_env, RsV) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index 9e9dfd5..a382664 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -268,6 +268,69 @@ static inline void gen_write_ctrl_reg_pair(DisasContex= t *ctx, int reg_num, } } =20 +static inline TCGv gen_get_byte(TCGv result, int N, TCGv src, bool sign) +{ + if (sign) { + tcg_gen_sextract_tl(result, src, N * 8, 8); + } else { + tcg_gen_extract_tl(result, src, N * 8, 8); + } + return result; +} + +static inline TCGv gen_get_byte_i64(TCGv result, int N, TCGv_i64 src, bool= sign) +{ + TCGv_i64 res64 =3D tcg_temp_new_i64(); + if (sign) { + tcg_gen_sextract_i64(res64, src, N * 8, 8); + } else { + tcg_gen_extract_i64(res64, src, N * 8, 8); + } + tcg_gen_extrl_i64_i32(result, res64); + tcg_temp_free_i64(res64); + + return result; +} + +static inline void gen_set_byte(int N, TCGv result, TCGv src) +{ + tcg_gen_deposit_tl(result, result, src, N * 8, 8); +} + +static inline void gen_set_byte_i64(int N, TCGv_i64 result, TCGv src) +{ + TCGv_i64 src64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(src64, src); + tcg_gen_deposit_i64(result, result, src64, N * 8, 8); + tcg_temp_free_i64(src64); +} + +static inline TCGv gen_get_word(TCGv result, int N, TCGv_i64 src, bool sig= n) +{ + if (N =3D=3D 0) { + tcg_gen_extrl_i64_i32(result, src); + } else if (N =3D=3D 1) { + tcg_gen_extrh_i64_i32(result, src); + } else { + g_assert_not_reached(); + } + return result; +} + +static inline TCGv_i64 gen_get_word_i64(TCGv_i64 result, int N, TCGv_i64 s= rc, + bool sign) +{ + TCGv word =3D tcg_temp_new(); + gen_get_word(word, N, src, sign); + if (sign) { + tcg_gen_ext_i32_i64(result, word); + } else { + tcg_gen_extu_i32_i64(result, word); + } + tcg_temp_free(word); + return result; +} + static inline void gen_load_locked4u(TCGv dest, TCGv vaddr, int mem_index) { tcg_gen_qemu_ld32u(dest, vaddr, mem_index); @@ -341,5 +404,53 @@ static inline void gen_store_conditional8(CPUHexagonSt= ate *env, tcg_gen_movi_tl(hex_llsc_addr, ~0); } =20 +static inline TCGv_i64 gen_carry_from_add64(TCGv_i64 result, TCGv_i64 a, + TCGv_i64 b, TCGv_i64 c) +{ + TCGv_i64 WORD =3D tcg_temp_new_i64(); + TCGv_i64 tmpa =3D tcg_temp_new_i64(); + TCGv_i64 tmpb =3D tcg_temp_new_i64(); + TCGv_i64 tmpc =3D tcg_temp_new_i64(); + TCGv_i64 tmpx =3D tcg_temp_new_i64(); + + /* + * tmpa =3D fGETUWORD(0, a); + * tmpb =3D fGETUWORD(0, b); + * tmpc =3D tmpa + tmpb + c; + * tmpa =3D fGETUWORD(1, a); + * tmpb =3D fGETUWORD(1, b); + * tmpc =3D tmpa + tmpb + fGETUWORD(1, tmpc); + * result =3D fGETUWORD(1, tmpc); + * return result; + */ + tcg_gen_mov_i64(tmpa, fGETUWORD(0, a)); + tcg_gen_mov_i64(tmpb, fGETUWORD(0, b)); + tcg_gen_add_i64(tmpc, tmpa, tmpb); + tcg_gen_add_i64(tmpc, tmpc, c); + tcg_gen_mov_i64(tmpa, fGETUWORD(1, a)); + tcg_gen_mov_i64(tmpb, fGETUWORD(1, b)); + tcg_gen_add_i64(tmpx, tmpa, tmpb); + tcg_gen_add_i64(tmpc, tmpx, fGETUWORD(1, tmpc)); + tcg_gen_mov_i64(result, fGETUWORD(1, tmpc)); + + tcg_temp_free_i64(WORD); + tcg_temp_free_i64(tmpa); + tcg_temp_free_i64(tmpb); + tcg_temp_free_i64(tmpc); + tcg_temp_free_i64(tmpx); + return result; +} + +static inline TCGv gen_8bitsof(TCGv result, TCGv value) +{ + TCGv zero =3D tcg_const_tl(0); + TCGv ones =3D tcg_const_tl(0xff); + tcg_gen_movcond_tl(TCG_COND_NE, result, value, zero, ones, zero); + tcg_temp_free(zero); + tcg_temp_free(ones); + + return result; +} + #include "tcg_funcs_generated.c.inc" #include "tcg_func_table_generated.c.inc" diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index 715c246..46c601b 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -26,6 +26,12 @@ DEF_HELPER_FLAGS_3(debug_commit_end, TCG_CALL_NO_WG, voi= d, env, int, int) #endif DEF_HELPER_2(commit_store, void, env, int) DEF_HELPER_FLAGS_4(fcircadd, TCG_CALL_NO_RWG_SE, s32, s32, s32, s32, s32) +DEF_HELPER_3(sfrecipa_val, f32, env, f32, f32) +DEF_HELPER_3(sfrecipa_pred, s32, env, f32, f32) +DEF_HELPER_2(sfinvsqrta_val, f32, env, f32) +DEF_HELPER_2(sfinvsqrta_pred, s32, env, f32) +DEF_HELPER_4(vacsh_val, s64, env, s64, s64, s64) +DEF_HELPER_4(vacsh_pred, s32, env, s64, s64, s64) =20 /* Floating point */ DEF_HELPER_2(conv_sf2df, f64, env, f32) diff --git a/target/hexagon/imported/alu.idef b/target/hexagon/imported/alu= .idef index 45cc529..58477ae 100644 --- a/target/hexagon/imported/alu.idef +++ b/target/hexagon/imported/alu.idef @@ -153,6 +153,21 @@ Q6INSN(A2_subp,"Rdd32=3Dsub(Rtt32,Rss32)",ATTRIBS(), "Sub", { RddV=3DRttV-RssV;}) =20 +/* 64-bit with carry */ + +Q6INSN(A4_addp_c,"Rdd32=3Dadd(Rss32,Rtt32,Px4):carry",ATTRIBS(),"Add with = Carry", +{ + RddV =3D RssV + RttV + fLSBOLD(PxV); + PxV =3D f8BITSOF(fCARRY_FROM_ADD(RssV,RttV,fLSBOLD(PxV))); +}) + +Q6INSN(A4_subp_c,"Rdd32=3Dsub(Rss32,Rtt32,Px4):carry",ATTRIBS(),"Sub with = Carry", +{ + RddV =3D RssV + ~RttV + fLSBOLD(PxV); + PxV =3D f8BITSOF(fCARRY_FROM_ADD(RssV,~RttV,fLSBOLD(PxV))); +}) + + /* NEG and ABS */ =20 Q6INSN(A2_negsat,"Rd32=3Dneg(Rs32):sat",ATTRIBS(), @@ -1240,6 +1255,35 @@ MINMAX(uw,WORD,UWORD,2) #undef VMINORMAX3 =20 =20 +Q6INSN(A5_ACS,"Rxx32,Pe4=3Dvacsh(Rss32,Rtt32)",ATTRIBS(), +"Add Compare and Select elements of two vectors, record the maximums and t= he decisions ", +{ + fHIDE(int i;) + fHIDE(int xv;) + fHIDE(int sv;) + fHIDE(int tv;) + for (i =3D 0; i < 4; i++) { + xv =3D (int) fGETHALF(i,RxxV); + sv =3D (int) fGETHALF(i,RssV); + tv =3D (int) fGETHALF(i,RttV); + xv =3D xv + tv; //assumes 17bit datapath + sv =3D sv - tv; //assumes 17bit datapath + fSETBIT(i*2, PeV, (xv > sv)); + fSETBIT(i*2+1,PeV, (xv > sv)); + fSETHALF(i, RxxV, fSATH(fMAX(xv,sv))); + } +}) + +Q6INSN(A6_vminub_RdP,"Rdd32,Pe4=3Dvminub(Rtt32,Rss32)",ATTRIBS(), +"Vector minimum of bytes, records minimum and decision vector", +{ + fHIDE(int i;) + for (i =3D 0; i < 8; i++) { + fSETBIT(i, PeV, (fGETUBYTE(i,RttV) > fGETUBYTE(i,RssV))); + fSETBYTE(i,RddV,fMIN(fGETUBYTE(i,RttV),fGETUBYTE(i,RssV))); + } +}) + /**********************************************/ /* Vector Min/Max */ /**********************************************/ diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index c21cb73..514c240 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -1017,6 +1017,8 @@ MPY_ENC(M7_dcmpyiwc_acc, "1010","xxxxx","1","0","= 1","0","10") =20 =20 =20 +MPY_ENC(A5_ACS, "1010","xxxxx","0","1","0","1","ee") +MPY_ENC(A6_vminub_RdP, "1010","ddddd","0","1","1","1","ee") /* */ =20 @@ -1028,6 +1030,7 @@ MPY_ENC(F2_sfmin, "1011","ddddd","0","0","= 0","1","01") MPY_ENC(F2_sfmpy, "1011","ddddd","0","0","1","0","00") MPY_ENC(F2_sffixupn, "1011","ddddd","0","0","1","1","00") MPY_ENC(F2_sffixupd, "1011","ddddd","0","0","1","1","01") +MPY_ENC(F2_sfrecipa, "1011","ddddd","1","1","1","1","ee") =20 DEF_FIELDROW_DESC32(ICLASS_M" 1100 -------- PP------ --------","[#12] Rd= =3D(Rs,Rt)") DEF_FIELD32(ICLASS_M" 1100 -------- PP------ --!-----",Mc_tH,"Rt i= s High") /*Rt high */ @@ -1641,6 +1644,7 @@ SH2_RR_ENC(F2_conv_sf2w, "1011","100","-","0= 00","ddddd") SH2_RR_ENC(F2_conv_sf2uw_chop, "1011","011","-","001","ddddd") SH2_RR_ENC(F2_conv_sf2w_chop, "1011","100","-","001","ddddd") SH2_RR_ENC(F2_sffixupr, "1011","101","-","000","ddddd") +SH2_RR_ENC(F2_sfinvsqrta, "1011","111","-","0ee","ddddd") =20 =20 DEF_FIELDROW_DESC32(ICLASS_S2op" 1100 -------- PP------ --------","[#= 12] Rd=3D(Rs,#u6)") @@ -1745,6 +1749,8 @@ SH_RRR_ENC(S4_extractp_rp, "0001","11-","-","10-= ","ddddd") DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rd= d=3D(Rss,Rtt,Pu)") SH_RRR_ENC(S2_valignrb, "0010","0--","-","-uu","ddddd") SH_RRR_ENC(S2_vsplicerb, "0010","100","-","-uu","ddddd") +SH_RRR_ENC(A4_addp_c, "0010","110","-","-xx","ddddd") +SH_RRR_ENC(A4_subp_c, "0010","111","-","-xx","ddddd") =20 =20 DEF_FIELDROW_DESC32(ICLASS_S3op" 0011 -------- PP------ --------","[#3] Rd= d=3D(Rss,Rt)") diff --git a/target/hexagon/imported/float.idef b/target/hexagon/imported/f= loat.idef index 76cecfe..3e75bc4 100644 --- a/target/hexagon/imported/float.idef +++ b/target/hexagon/imported/float.idef @@ -146,6 +146,22 @@ Q6INSN(F2_sfimm_n,"Rd32=3Dsfmake(#u10):neg",ATTRIBS(), }) =20 =20 +Q6INSN(F2_sfrecipa,"Rd32,Pe4=3Dsfrecipa(Rs32,Rt32)",ATTRIBS(), +"Reciprocal Approximation for Division", +{ + fHIDE(int idx;) + fHIDE(int adjust;) + fHIDE(int mant;) + fHIDE(int exp;) + if (fSF_RECIP_COMMON(RsV,RtV,RdV,adjust)) { + PeV =3D adjust; + idx =3D (RtV >> 16) & 0x7f; + mant =3D (fSF_RECIP_LOOKUP(idx) << 15) | 1; + exp =3D fSF_BIAS() - (fSF_GETEXP(RtV) - fSF_BIAS()) - 1; + RdV =3D fMAKESF(fGETBIT(31,RtV),exp,mant); + } +}) + Q6INSN(F2_sffixupn,"Rd32=3Dsffixupn(Rs32,Rt32)",ATTRIBS(), "Fix Up Numerator", { @@ -162,6 +178,22 @@ Q6INSN(F2_sffixupd,"Rd32=3Dsffixupd(Rs32,Rt32)",ATTRIB= S(), RdV =3D RtV; }) =20 +Q6INSN(F2_sfinvsqrta,"Rd32,Pe4=3Dsfinvsqrta(Rs32)",ATTRIBS(), +"Reciprocal Square Root Approximation", +{ + fHIDE(int idx;) + fHIDE(int adjust;) + fHIDE(int mant;) + fHIDE(int exp;) + if (fSF_INVSQRT_COMMON(RsV,RdV,adjust)) { + PeV =3D adjust; + idx =3D (RsV >> 17) & 0x7f; + mant =3D (fSF_INVSQRT_LOOKUP(idx) << 15); + exp =3D fSF_BIAS() - ((fSF_GETEXP(RsV) - fSF_BIAS()) >> 1) - 1; + RdV =3D fMAKESF(fGETBIT(31,RsV),exp,mant); + } +}) + Q6INSN(F2_sffixupr,"Rd32=3Dsffixupr(Rs32)",ATTRIBS(), "Fix Up Radicand", { diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index 8cb211d..123c995 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -177,7 +177,11 @@ static inline void gen_pred_cancel(TCGv pred, int slot= _num) =20 #define fMAX(A, B) (((A) > (B)) ? (A) : (B)) =20 +#ifdef QEMU_GENERATE +#define fMIN(DST, A, B) tcg_gen_movcond_i32(TCG_COND_LT, DST, A, B, A, B) +#else #define fMIN(A, B) (((A) < (B)) ? (A) : (B)) +#endif =20 #define fABS(A) (((A) < 0) ? (-(A)) : (A)) #define fINSERT_BITS(REG, WIDTH, OFFSET, INVAL) \ @@ -191,7 +195,11 @@ static inline void gen_pred_cancel(TCGv pred, int slot= _num) extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ 0LL) =20 +#ifdef QEMU_GENERATE +#define f8BITSOF(RES, VAL) gen_8bitsof(RES, VAL) +#else #define f8BITSOF(VAL) ((VAL) ? 0xff : 0x00) +#endif =20 #ifdef QEMU_GENERATE #define fLSBOLD(VAL) tcg_gen_andi_tl(LSB, (VAL), 1) @@ -501,14 +509,33 @@ static inline void gen_logical_not(TCGv dest, TCGv sr= c) gen_store_conditional##SIZE(env, ctx, PdN, PRED, EA, SRC); #endif =20 +#ifdef QEMU_GENERATE +#define GETBYTE_FUNC(X) \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_get_byte, \ + __builtin_choose_expr(TYPE_TCGV_I64(X), \ + gen_get_byte_i64, (void)0)) +#define fGETBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, true) +#define fGETUBYTE(N, SRC) GETBYTE_FUNC(SRC)(BYTE, N, SRC, false) +#else #define fGETBYTE(N, SRC) ((int8_t)((SRC >> ((N) * 8)) & 0xff)) #define fGETUBYTE(N, SRC) ((uint8_t)((SRC >> ((N) * 8)) & 0xff)) +#endif =20 +#ifdef QEMU_GENERATE +#define SETBYTE_FUNC(X) \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_set_byte, \ + __builtin_choose_expr(TYPE_TCGV_I64(X), \ + gen_set_byte_i64, (void)0)) +#define fSETBYTE(N, DST, VAL) SETBYTE_FUNC(DST)(N, DST, VAL) +#else #define fSETBYTE(N, DST, VAL) \ do { \ DST =3D (DST & ~(0x0ffLL << ((N) * 8))) | \ (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ } while (0) +#endif #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) #define fSETHALF(N, DST, VAL) \ @@ -519,10 +546,20 @@ static inline void gen_logical_not(TCGv dest, TCGv sr= c) #define fSETHALFw fSETHALF #define fSETHALFd fSETHALF =20 +#ifdef QEMU_GENERATE +#define GETWORD_FUNC(X) \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_get_word, \ + __builtin_choose_expr(TYPE_TCGV_I64(X), \ + gen_get_word_i64, (void)0)) +#define fGETWORD(N, SRC) GETWORD_FUNC(WORD)(WORD, N, SRC, true) +#define fGETUWORD(N, SRC) GETWORD_FUNC(WORD)(WORD, N, SRC, false) +#else #define fGETWORD(N, SRC) \ ((int64_t)((int32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) #define fGETUWORD(N, SRC) \ ((uint64_t)((uint32_t)((SRC >> ((N) * 32)) & 0x0ffffffffLL))) +#endif =20 #define fSETWORD(N, DST, VAL) \ do { \ @@ -530,10 +567,14 @@ static inline void gen_logical_not(TCGv dest, TCGv sr= c) (((VAL) & 0x0ffffffffLL) << ((N) * 32)); \ } while (0) =20 +#ifdef QEMU_GENERATE +#define fSETBIT(N, DST, VAL) tcg_gen_deposit_tl(DST, DST, VAL, N, 1) +#else #define fSETBIT(N, DST, VAL) \ do { \ DST =3D (DST & ~(1ULL << (N))) | (((uint64_t)(VAL)) << (N)); \ } while (0) +#endif =20 #define fGETBIT(N, SRC) (((SRC) >> N) & 1) #define fSETBITS(HI, LO, DST, VAL) \ diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 5bc9a93..9ea4580 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -295,6 +295,136 @@ int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset,= int32_t M, int32_t CS) return new_ptr; } =20 +static float32 build_float32(uint8_t sign, uint32_t exp, uint32_t mant) +{ + return make_float32( + ((sign & 1) << 31) | + ((exp & 0xff) << SF_MANTBITS) | + (mant & ((1 << SF_MANTBITS) - 1))); +} + +/* + * sfrecipa, sfinvsqrta, vacsh have two results + * r0,p0=3Dsfrecipa(r1,r2) + * r0,p0=3Dsfinvsqrta(r1) + * r1:0,p0=3Dvacsh(r3:2,r5:4) + * Since helpers can only return a single value, we have two helpers + * for each of these. They each contain basically the same code (copy/past= ed + * from the arch library), but one returns the register and the other + * returns the predicate. + */ +float32 HELPER(sfrecipa_val)(CPUHexagonState *env, float32 RsV, float32 Rt= V) +{ + /* int32_t PeV; Not needed to compute value */ + float32 RdV; + int idx; + int adjust; + int mant; + int exp; + + arch_fpop_start(env); + if (arch_sf_recip_common(&RsV, &RtV, &RdV, &adjust, &env->fp_status)) { + /* PeV =3D adjust; Not needed to compute value */ + idx =3D (RtV >> 16) & 0x7f; + mant =3D (arch_recip_lookup(idx) << 15) | 1; + exp =3D SF_BIAS - (float32_getexp(RtV) - SF_BIAS) - 1; + RdV =3D build_float32(extract32(RtV, 31, 1), exp, mant); + } + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(sfrecipa_pred)(CPUHexagonState *env, float32 RsV, float32 R= tV) +{ + int32_t PeV =3D 0; + float32 RdV; + int adjust; + + arch_fpop_start(env); + if (arch_sf_recip_common(&RsV, &RtV, &RdV, &adjust, &env->fp_status)) { + PeV =3D adjust; + } + arch_fpop_end(env); + return PeV; +} + +float32 HELPER(sfinvsqrta_val)(CPUHexagonState *env, float32 RsV) +{ + /* int32_t PeV; Not needed for val version */ + float32 RdV; + int idx; + int adjust; + int mant; + int exp; + + arch_fpop_start(env); + if (arch_sf_invsqrt_common(&RsV, &RdV, &adjust, &env->fp_status)) { + /* PeV =3D adjust; Not needed for val version */ + idx =3D (RsV >> 17) & 0x7f; + mant =3D (arch_invsqrt_lookup(idx) << 15); + exp =3D SF_BIAS - ((float32_getexp(RsV) - SF_BIAS) >> 1) - 1; + RdV =3D build_float32(extract32(RsV, 31, 1), exp, mant); + } + arch_fpop_end(env); + return RdV; +} + +int32_t HELPER(sfinvsqrta_pred)(CPUHexagonState *env, float32 RsV) +{ + int32_t PeV =3D 0; + float32 RdV; + int adjust; + + arch_fpop_start(env); + if (arch_sf_invsqrt_common(&RsV, &RdV, &adjust, &env->fp_status)) { + PeV =3D adjust; + } + arch_fpop_end(env); + return PeV; +} + +int64_t HELPER(vacsh_val)(CPUHexagonState *env, + int64_t RxxV, int64_t RssV, int64_t RttV) +{ + int32_t PeV =3D 0; + int i; + int xv; + int sv; + int tv; + for (i =3D 0; i < 4; i++) { + xv =3D (int)fGETHALF(i, RxxV); + sv =3D (int)fGETHALF(i, RssV); + tv =3D (int)fGETHALF(i, RttV); + xv =3D xv + tv; + sv =3D sv - tv; + fSETBIT(i * 2, PeV, (xv > sv)); + fSETBIT(i * 2 + 1, PeV, (xv > sv)); + fSETHALF(i, RxxV, fSATH(fMAX(xv, sv))); + } + return RxxV; +} + +int32_t HELPER(vacsh_pred)(CPUHexagonState *env, + int64_t RxxV, int64_t RssV, int64_t RttV) +{ + int32_t PeV =3D 0; + int i; + int xv; + int sv; + int tv; + for (i =3D 0; i < 4; i++) { + xv =3D (int)fGETHALF(i, RxxV); + sv =3D (int)fGETHALF(i, RssV); + tv =3D (int)fGETHALF(i, RttV); + xv =3D xv + tv; + sv =3D sv - tv; + fSETBIT(i * 2, PeV, (xv > sv)); + fSETBIT(i * 2 + 1, PeV, (xv > sv)); + fSETHALF(i, RxxV, fSATH(fMAX(xv, sv))); + } + return PeV; +} + /* * mem_noshuf * Section 5.5 of the Hexagon V67 Programmer's Reference Manual diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 616af69..18218ad 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -39,6 +39,7 @@ HEX_TESTS =3D first HEX_TESTS +=3D misc HEX_TESTS +=3D preg_alias HEX_TESTS +=3D dual_stores +HEX_TESTS +=3D multi_result HEX_TESTS +=3D mem_noshuf HEX_TESTS +=3D atomics HEX_TESTS +=3D fpstuff diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 6b60f92..0dff429 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -250,6 +250,87 @@ static void check_dfminmax(void) check_fpstatus(usr, FPINVF); } =20 +static void check_recip_exception(void) +{ + int result; + int usr; + + /* + * Check that sfrecipa doesn't set status bits when + * a NaN with bit 22 non-zero is passed + */ + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "p0", "usr"); + check32(result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(SF_ANY), "r"(SF_NaN) + : "r2", "p0", "usr"); + check32(result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(SF_NaN) + : "r2", "p0", "usr"); + check32(result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + /* + * Check that sfrecipa doesn't set status bits when + * a NaN with bit 22 zero is passed + */ + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(SF_NaN_special), "r"(SF_ANY) + : "r2", "p0", "usr"); + check32(result, SF_HEX_NAN); + check_fpstatus(usr, FPINVF); + + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(SF_ANY), "r"(SF_NaN_special) + : "r2", "p0", "usr"); + check32(result, SF_HEX_NAN); + check_fpstatus(usr, FPINVF); + + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(SF_NaN_special) + : "r2", "p0", "usr"); + check32(result, SF_HEX_NAN); + check_fpstatus(usr, FPINVF); + + /* + * Check that sfrecipa properly sets divid-by-zero + */ + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(0x885dc960), "r"(0x80000000) + : "r2", "p0", "usr"); + check32(result, 0x3f800000); + check_fpstatus(usr, FPDBZF); + + asm (CLEAR_FPSTATUS + "%0,p0 =3D sfrecipa(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(result), "=3Dr"(usr) : "r"(0x7f800000), "r"(SF_ZERO) + : "r2", "p0", "usr"); + check32(result, 0x3f800000); + check_fpstatus(usr, 0); +} + static void check_canonical_NaN(void) { int sf_result; @@ -360,6 +441,20 @@ static void check_canonical_NaN(void) check_fpstatus(usr, 0); } =20 +static void check_invsqrta(void) +{ + int result; + int predval; + + asm volatile("%0,p0 =3D sfinvsqrta(%2)\n\t" + "%1 =3D p0\n\t" + : "+r"(result), "=3Dr"(predval) + : "r"(0x7f800000) + : "p0"); + check32(result, 0xff800000); + check32(predval, 0x0); +} + static void check_float2int_convs() { int res32; @@ -507,7 +602,9 @@ int main() check_compare_exception(); check_sfminmax(); check_dfminmax(); + check_recip_exception(); check_canonical_NaN(); + check_invsqrta(); check_float2int_convs(); =20 puts(err ? "FAIL" : "PASS"); diff --git a/tests/tcg/hexagon/multi_result.c b/tests/tcg/hexagon/multi_res= ult.c new file mode 100644 index 0000000..99ae657 --- /dev/null +++ b/tests/tcg/hexagon/multi_result.c @@ -0,0 +1,249 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +static int sfrecipa(int Rs, int Rt, int *pred_result) +{ + int result; + int predval; + + asm volatile("%0,p0 =3D sfrecipa(%2, %3)\n\t" + "%1 =3D p0\n\t" + : "+r"(result), "=3Dr"(predval) + : "r"(Rs), "r"(Rt) + : "p0"); + *pred_result =3D predval; + return result; +} + +static int sfinvsqrta(int Rs, int *pred_result) +{ + int result; + int predval; + + asm volatile("%0,p0 =3D sfinvsqrta(%2)\n\t" + "%1 =3D p0\n\t" + : "+r"(result), "=3Dr"(predval) + : "r"(Rs) + : "p0"); + *pred_result =3D predval; + return result; +} + +static long long vacsh(long long Rxx, long long Rss, long long Rtt, + int *pred_result) +{ + long long result =3D Rxx; + int predval; + + asm volatile("%0,p0 =3D vacsh(%2, %3)\n\t" + "%1 =3D p0\n\t" + : "+r"(result), "=3Dr"(predval) + : "r"(Rss), "r"(Rtt) + : "p0"); + *pred_result =3D predval; + return result; +} + +static long long vminub(long long Rtt, long long Rss, + int *pred_result) +{ + long long result; + int predval; + + asm volatile("%0,p0 =3D vminub(%2, %3)\n\t" + "%1 =3D p0\n\t" + : "=3Dr"(result), "=3Dr"(predval) + : "r"(Rtt), "r"(Rss) + : "p0"); + *pred_result =3D predval; + return result; +} + +static long long add_carry(long long Rss, long long Rtt, + int pred_in, int *pred_result) +{ + long long result; + int predval =3D pred_in; + + asm volatile("p0 =3D %1\n\t" + "%0 =3D add(%2, %3, p0):carry\n\t" + "%1 =3D p0\n\t" + : "=3Dr"(result), "+r"(predval) + : "r"(Rss), "r"(Rtt) + : "p0"); + *pred_result =3D predval; + return result; +} + +static long long sub_carry(long long Rss, long long Rtt, + int pred_in, int *pred_result) +{ + long long result; + int predval =3D pred_in; + + asm volatile("p0 =3D !cmp.eq(%1, #0)\n\t" + "%0 =3D sub(%2, %3, p0):carry\n\t" + "%1 =3D p0\n\t" + : "=3Dr"(result), "+r"(predval) + : "r"(Rss), "r"(Rtt) + : "p0"); + *pred_result =3D predval; + return result; +} + +int err; + +static void check_ll(long long val, long long expect) +{ + if (val !=3D expect) { + printf("ERROR: 0x%016llx !=3D 0x%016llx\n", val, expect); + err++; + } +} + +static void check(int val, int expect) +{ + if (val !=3D expect) { + printf("ERROR: 0x%08x !=3D 0x%08x\n", val, expect); + err++; + } +} + +static void check_p(int val, int expect) +{ + if (val !=3D expect) { + printf("ERROR: 0x%02x !=3D 0x%02x\n", val, expect); + err++; + } +} + +static void test_sfrecipa() +{ + int res; + int pred_result; + + res =3D sfrecipa(0x04030201, 0x05060708, &pred_result); + check(res, 0x59f38001); + check_p(pred_result, 0x00); +} + +static void test_sfinvsqrta() +{ + int res; + int pred_result; + + res =3D sfinvsqrta(0x04030201, &pred_result); + check(res, 0x4d330000); + check_p(pred_result, 0xe0); + + res =3D sfinvsqrta(0x0, &pred_result); + check(res, 0x3f800000); + check_p(pred_result, 0x0); +} + +static void test_vacsh() +{ + long long res64; + int pred_result; + + res64 =3D vacsh(0x0807060504030201LL, + 0x0102030405060708LL, + 0x0LL, &pred_result); + check_ll(res64, 0x807060505060708LL); + check_p(pred_result, 0xf0); +} + +static void test_vminub() +{ + long long res64; + int pred_result; + + res64 =3D vminub(0x0807060504030201LL, + 0x0102030405060708LL, + &pred_result); + check_ll(res64, 0x0102030404030201LL); + check_p(pred_result, 0xf0); + + res64 =3D vminub(0x0802060405030701LL, + 0x0107030504060208LL, + &pred_result); + check_ll(res64, 0x0102030404030201LL); + check_p(pred_result, 0xaa); +} + +static void test_add_carry() +{ + long long res64; + int pred_result; + + res64 =3D add_carry(0x0000000000000000LL, + 0xffffffffffffffffLL, + 1, &pred_result); + check_ll(res64, 0x0000000000000000LL); + check_p(pred_result, 0xff); + + res64 =3D add_carry(0x0000000100000000LL, + 0xffffffffffffffffLL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); + + res64 =3D add_carry(0x0000000100000000LL, + 0xffffffffffffffffLL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); +} + +static void test_sub_carry() +{ + long long res64; + int pred_result; + + res64 =3D sub_carry(0x0000000000000000LL, + 0x0000000000000000LL, + 1, &pred_result); + check_ll(res64, 0x0000000000000000LL); + check_p(pred_result, 0xff); + + res64 =3D sub_carry(0x0000000100000000LL, + 0x0000000000000000LL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); + + res64 =3D sub_carry(0x0000000100000000LL, + 0x0000000000000000LL, + 0, &pred_result); + check_ll(res64, 0x00000000ffffffffLL); + check_p(pred_result, 0xff); +} + +int main() +{ + test_sfrecipa(); + test_sfinvsqrta(); + test_vacsh(); + test_vminub(); + test_add_carry(); + test_sub_carry(); + + puts(err ? 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Wed, 24 Mar 2021 22:50:36 -0400 Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 24 Mar 2021 19:50:14 -0700 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 24 Mar 2021 19:50:13 -0700 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 11978172B; Wed, 24 Mar 2021 21:50:12 -0500 (CDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1616640626; x=1648176626; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MQvBHyV3nhqceEI/8zCslbJOlH2t0wbftP/VFdurkzM=; b=EgL333aR5FqED7vHspQss4ppQqnMqqmU0cG1bo068DH9pjyRobGwEB+Z g/WNnWKf3NqtZbdqaZSu/cQeB7pSJzl9u0ve5QNJtfyK42d7vDE8I/Eb7 9kKxhKBGlBDtCEOIxeVoelmpdDROwBmrNpE8FxQdLKeJQaB3iHcDo8pnZ 4=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 11/15] Hexagon (target/hexagon) circular addressing Date: Wed, 24 Mar 2021 21:50:06 -0500 Message-Id: <1616640610-17319-12-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The following instructions are added L2_loadrub_pci Rd32 =3D memub(Rx32++#s4:0:circ(Mu2)) L2_loadrb_pci Rd32 =3D memb(Rx32++#s4:0:circ(Mu2)) L2_loadruh_pci Rd32 =3D memuh(Rx32++#s4:1:circ(Mu2)) L2_loadrh_pci Rd32 =3D memh(Rx32++#s4:1:circ(Mu2)) L2_loadri_pci Rd32 =3D memw(Rx32++#s4:2:circ(Mu2)) L2_loadrd_pci Rdd32 =3D memd(Rx32++#s4:3:circ(Mu2)) S2_storerb_pci memb(Rx32++#s4:0:circ(Mu2)) =3D Rt32 S2_storerh_pci memh(Rx32++#s4:1:circ(Mu2)) =3D Rt32 S2_storerf_pci memh(Rx32++#s4:1:circ(Mu2)) =3D Rt.H32 S2_storeri_pci memw(Rx32++#s4:2:circ(Mu2)) =3D Rt32 S2_storerd_pci memd(Rx32++#s4:3:circ(Mu2)) =3D Rtt32 S2_storerbnew_pci memb(Rx32++#s4:0:circ(Mu2)) =3D Nt8.new S2_storerhnew_pci memw(Rx32++#s4:1:circ(Mu2)) =3D Nt8.new S2_storerinew_pci memw(Rx32++#s4:2:circ(Mu2)) =3D Nt8.new L2_loadrub_pcr Rd32 =3D memub(Rx32++I:circ(Mu2)) L2_loadrb_pcr Rd32 =3D memb(Rx32++I:circ(Mu2)) L2_loadruh_pcr Rd32 =3D memuh(Rx32++I:circ(Mu2)) L2_loadrh_pcr Rd32 =3D memh(Rx32++I:circ(Mu2)) L2_loadri_pcr Rd32 =3D memw(Rx32++I:circ(Mu2)) L2_loadrd_pcr Rdd32 =3D memd(Rx32++I:circ(Mu2)) S2_storerb_pcr memb(Rx32++I:circ(Mu2)) =3D Rt32 S2_storerh_pcr memh(Rx32++I:circ(Mu2)) =3D Rt32 S2_storerf_pcr memh(Rx32++I:circ(Mu2)) =3D Rt32.H32 S2_storeri_pcr memw(Rx32++I:circ(Mu2)) =3D Rt32 S2_storerd_pcr memd(Rx32++I:circ(Mu2)) =3D Rtt32 S2_storerbnew_pcr memb(Rx32++I:circ(Mu2)) =3D Nt8.new S2_storerhnew_pcr memh(Rx32++I:circ(Mu2)) =3D Nt8.new S2_storerinew_pcr memw(Rx32++I:circ(Mu2)) =3D Nt8.new Test cases in tests/tcg/hexagon/circ.c Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 127 +++++++++++ target/hexagon/genptr.c | 85 ++++++++ target/hexagon/imported/encode_pp.def | 9 + target/hexagon/imported/ldst.idef | 4 + target/hexagon/imported/macros.def | 26 +++ target/hexagon/macros.h | 87 ++++++++ tests/tcg/hexagon/Makefile.target | 1 + tests/tcg/hexagon/circ.c | 393 ++++++++++++++++++++++++++++++= ++++ 8 files changed, 732 insertions(+) create mode 100644 tests/tcg/hexagon/circ.c diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 0b2c2ca..2d64590 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -38,6 +38,8 @@ * _ap absolute set r0 =3D memw(r1=3D##vari= able) * _pr post increment register r0 =3D memw(r1++m1) * _pi post increment immediate r0 =3D memb(r1++#1) + * _pci post increment circular immediate r0 =3D memw(r1++#4:circ= (m0)) + * _pcr post increment circular register r0 =3D memw(r1++I:circ(= m0)) */ =20 /* Macros for complex addressing modes */ @@ -56,7 +58,28 @@ fEA_REG(RxV); \ fPM_I(RxV, siV); \ } while (0) +#define GET_EA_pci \ + do { \ + fEA_REG(RxV); \ + fPM_CIRI(RxV, siV, MuV); \ + } while (0) +#define GET_EA_pcr(SHIFT) \ + do { \ + fEA_REG(RxV); \ + fPM_CIRR(RxV, fREAD_IREG(MuV, (SHIFT)), MuV); \ + } while (0) =20 +/* + * Many instructions will work with just macro redefinitions + * with the caveat that they need a tmp variable to carry a + * value between them. + */ +#define fGEN_TCG_tmp(SHORTCODE) \ + do { \ + TCGv tmp =3D tcg_temp_new(); \ + SHORTCODE; \ + tcg_temp_free(tmp); \ + } while (0) =20 /* Instructions with multiple definitions */ #define fGEN_TCG_LOAD_AP(RES, SIZE, SIGN) \ @@ -80,6 +103,44 @@ #define fGEN_TCG_L4_loadrd_ap(SHORTCODE) \ fGEN_TCG_LOAD_AP(RddV, 8, u) =20 +#define fGEN_TCG_L2_loadrub_pci(SHORTCODE) \ + fGEN_TCG_tmp(SHORTCODE) +#define fGEN_TCG_L2_loadrb_pci(SHORTCODE) \ + fGEN_TCG_tmp(SHORTCODE) +#define fGEN_TCG_L2_loadruh_pci(SHORTCODE) \ + fGEN_TCG_tmp(SHORTCODE) +#define fGEN_TCG_L2_loadrh_pci(SHORTCODE) \ + fGEN_TCG_tmp(SHORTCODE) +#define fGEN_TCG_L2_loadri_pci(SHORTCODE) \ + fGEN_TCG_tmp(SHORTCODE) +#define fGEN_TCG_L2_loadrd_pci(SHORTCODE) \ + fGEN_TCG_tmp(SHORTCODE) + +#define fGEN_TCG_PCR(SHIFT, LOAD) \ + do { \ + TCGv ireg =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + fEA_REG(RxV); \ + fREAD_IREG(MuV, SHIFT); \ + gen_helper_fcircadd(RxV, RxV, ireg, MuV, fREAD_CSREG(MuN)); \ + LOAD; \ + tcg_temp_free(tmp); \ + tcg_temp_free(ireg); \ + } while (0) + +#define fGEN_TCG_L2_loadrub_pcr(SHORTCODE) \ + fGEN_TCG_PCR(0, fLOAD(1, 1, u, EA, RdV)) +#define fGEN_TCG_L2_loadrb_pcr(SHORTCODE) \ + fGEN_TCG_PCR(0, fLOAD(1, 1, s, EA, RdV)) +#define fGEN_TCG_L2_loadruh_pcr(SHORTCODE) \ + fGEN_TCG_PCR(1, fLOAD(1, 2, u, EA, RdV)) +#define fGEN_TCG_L2_loadrh_pcr(SHORTCODE) \ + fGEN_TCG_PCR(1, fLOAD(1, 2, s, EA, RdV)) +#define fGEN_TCG_L2_loadri_pcr(SHORTCODE) \ + fGEN_TCG_PCR(2, fLOAD(1, 4, u, EA, RdV)) +#define fGEN_TCG_L2_loadrd_pcr(SHORTCODE) \ + fGEN_TCG_PCR(3, fLOAD(1, 8, u, EA, RddV)) + #define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE @@ -195,6 +256,72 @@ #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) =20 +#define fGEN_TCG_STORE(SHORTCODE) \ + do { \ + TCGv HALF =3D tcg_temp_new(); \ + TCGv BYTE =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + SHORTCODE; \ + tcg_temp_free(HALF); \ + tcg_temp_free(BYTE); \ + tcg_temp_free(tmp); \ + } while (0) + +#define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ + do { \ + TCGv ireg =3D tcg_temp_new(); \ + TCGv HALF =3D tcg_temp_new(); \ + TCGv BYTE =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + fEA_REG(RxV); \ + fPM_CIRR(RxV, fREAD_IREG(MuV, SHIFT), MuV); \ + STORE; \ + tcg_temp_free(ireg); \ + tcg_temp_free(HALF); \ + tcg_temp_free(BYTE); \ + tcg_temp_free(tmp); \ + } while (0) + +#define fGEN_TCG_S2_storerb_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV))) + +#define fGEN_TCG_S2_storerh_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV))) + +#define fGEN_TCG_S2_storerf_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV))) + +#define fGEN_TCG_S2_storeri_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV)) + +#define fGEN_TCG_S2_storerd_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV)) + +#define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN))) + +#define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN))) + +#define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) +#define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ + fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN)) + /* * Mathematical operations with more than one definition require * special handling diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index a382664..aaa2901 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -27,6 +27,12 @@ #include "macros.h" #include "gen_tcg.h" =20 +static inline TCGv gen_read_reg(TCGv result, int num) +{ + tcg_gen_mov_tl(result, hex_gpr[num]); + return result; +} + static inline TCGv gen_read_preg(TCGv pred, uint8_t num) { tcg_gen_mov_tl(pred, hex_pred[num]); @@ -292,6 +298,16 @@ static inline TCGv gen_get_byte_i64(TCGv result, int N= , TCGv_i64 src, bool sign) return result; } =20 +static inline TCGv gen_get_half(TCGv result, int N, TCGv src, bool sign) +{ + if (sign) { + tcg_gen_sextract_tl(result, src, N * 16, 16); + } else { + tcg_gen_extract_tl(result, src, N * 16, 16); + } + return result; +} + static inline void gen_set_byte(int N, TCGv result, TCGv src) { tcg_gen_deposit_tl(result, result, src, N * 8, 8); @@ -404,6 +420,75 @@ static inline void gen_store_conditional8(CPUHexagonSt= ate *env, tcg_gen_movi_tl(hex_llsc_addr, ~0); } =20 +static inline void gen_store32(TCGv vaddr, TCGv src, int width, int slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], width); + tcg_gen_mov_tl(hex_store_val32[slot], src); +} + +static inline void gen_store1(TCGv_env cpu_env, TCGv vaddr, TCGv src, + DisasContext *ctx, int slot) +{ + gen_store32(vaddr, src, 1, slot); + ctx->store_width[slot] =3D 1; +} + +static inline void gen_store1i(TCGv_env cpu_env, TCGv vaddr, int32_t src, + DisasContext *ctx, int slot) +{ + TCGv tmp =3D tcg_const_tl(src); + gen_store1(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free(tmp); +} + +static inline void gen_store2(TCGv_env cpu_env, TCGv vaddr, TCGv src, + DisasContext *ctx, int slot) +{ + gen_store32(vaddr, src, 2, slot); + ctx->store_width[slot] =3D 2; +} + +static inline void gen_store2i(TCGv_env cpu_env, TCGv vaddr, int32_t src, + DisasContext *ctx, int slot) +{ + TCGv tmp =3D tcg_const_tl(src); + gen_store2(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free(tmp); +} + +static inline void gen_store4(TCGv_env cpu_env, TCGv vaddr, TCGv src, + DisasContext *ctx, int slot) +{ + gen_store32(vaddr, src, 4, slot); + ctx->store_width[slot] =3D 4; +} + +static inline void gen_store4i(TCGv_env cpu_env, TCGv vaddr, int32_t src, + DisasContext *ctx, int slot) +{ + TCGv tmp =3D tcg_const_tl(src); + gen_store4(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free(tmp); +} + +static inline void gen_store8(TCGv_env cpu_env, TCGv vaddr, TCGv_i64 src, + DisasContext *ctx, int slot) +{ + tcg_gen_mov_tl(hex_store_addr[slot], vaddr); + tcg_gen_movi_tl(hex_store_width[slot], 8); + tcg_gen_mov_i64(hex_store_val64[slot], src); + ctx->store_width[slot] =3D 8; +} + +static inline void gen_store8i(TCGv_env cpu_env, TCGv vaddr, int64_t src, + DisasContext *ctx, int slot) +{ + TCGv_i64 tmp =3D tcg_const_i64(src); + gen_store8(cpu_env, vaddr, tmp, ctx, slot); + tcg_temp_free_i64(tmp); +} + static inline TCGv_i64 gen_carry_from_add64(TCGv_i64 result, TCGv_i64 a, TCGv_i64 b, TCGv_i64 c) { diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index 514c240..c97219f 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -294,6 +294,7 @@ DEF_CLASS32(ICLASS_LD" ---- -------- PP------ --------"= ,LD) =20 =20 DEF_CLASS32(ICLASS_LD" 0--- -------- PP------ --------",LD_ADDR_ROFFSET) +DEF_CLASS32(ICLASS_LD" 100- -------- PP----0- --------",LD_ADDR_POST_CIRC_= IMMED) DEF_CLASS32(ICLASS_LD" 101- -------- PP00---- --------",LD_ADDR_POST_IMMED) DEF_CLASS32(ICLASS_LD" 101- -------- PP01---- --------",LD_ADDR_ABS_UPDATE= _V4) DEF_CLASS32(ICLASS_LD" 101- -------- PP1----- --------",LD_ADDR_POST_IMMED= _PRED_V2) @@ -308,18 +309,22 @@ DEF_FIELD32(ICLASS_LD" ---- --!----- PP------ -------= -",LD_UN,"Unsigned") =20 #define STD_LD_ENC(TAG,OPC) \ DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iii= ddddd")\ +DEF_ENC32(L2_load##TAG##_pci, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--0i iii= ddddd")\ DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iii= ddddd")\ DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -II= ddddd")\ DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--= ddddd")\ DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iII= ddddd")\ +DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--= ddddd")\ =20 =20 #define STD_LDX_ENC(TAG,OPC) \ DEF_ENC32(L2_load##TAG##_io, ICLASS_LD" 0 ii "OPC" sssss PPiiiiii iii= yyyyy")\ +DEF_ENC32(L2_load##TAG##_pci, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--0i iii= yyyyy")\ DEF_ENC32(L2_load##TAG##_pi, ICLASS_LD" 1 01 "OPC" xxxxx PP00---i iii= yyyyy")\ DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" eeeee PP01IIII -II= yyyyy")\ DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--= yyyyy")\ DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iII= yyyyy")\ +DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--= yyyyy")\ =20 =20 #define STD_PLD_ENC(TAG,OPC) \ @@ -351,6 +356,7 @@ STD_PLD_ENC(rd, "1 110") /* note dest reg field LSB=3D= 0, 1 is reserved */ =20 DEF_CLASS32( ICLASS_LD" 0--0 000----- PP------ --------",LD_MISC) DEF_ANTICLASS32(ICLASS_LD" 0--0 000----- PP------ --------",LD_ADDR_ROFFSE= T) +DEF_ANTICLASS32(ICLASS_LD" 1000 000----- PP------ --------",LD_ADDR_POST_C= IRC_IMMED) DEF_ANTICLASS32(ICLASS_LD" 1010 000----- PP------ --------",LD_ADDR_POST_I= MMED) DEF_ANTICLASS32(ICLASS_LD" 1100 000----- PP------ --------",LD_ADDR_POST_R= EG) DEF_ANTICLASS32(ICLASS_LD" 1110 000----- PP------ --------",LD_ADDR_POST_R= EG) @@ -397,6 +403,7 @@ DEF_FIELD32(ICLASS_ST" ---! !!------ PP------ --------"= ,ST_Type,"Type") DEF_FIELD32(ICLASS_ST" ---- --!----- PP------ --------",ST_UN,"Unsigned") =20 DEF_CLASS32(ICLASS_ST" 0--1 -------- PP------ --------",ST_ADDR_ROFFSET) +DEF_CLASS32(ICLASS_ST" 1001 -------- PP------ ------0-",ST_ADDR_POST_CIRC_= IMMED) DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 0-----0-",ST_ADDR_POST_IMMED) DEF_CLASS32(ICLASS_ST" 1011 -------- PP0----- 1-------",ST_ADDR_ABS_UPDATE= _V4) DEF_CLASS32(ICLASS_ST" 1011 -------- PP1----- --------",ST_ADDR_POST_IMMED= _PRED_V2) @@ -411,10 +418,12 @@ DEF_CLASS32(ICLASS_ST" 0--0 0------- PP------ -------= -",ST_MISC_CACHEOP) =20 #define STD_ST_ENC(TAG,OPC,SRC) \ DEF_ENC32(S2_store##TAG##_io, ICLASS_ST" 0 ii "OPC" sssss PPi"SRC" ii= iiiiii")\ +DEF_ENC32(S2_store##TAG##_pci, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0i= iii-0-")\ DEF_ENC32(S2_store##TAG##_pi, ICLASS_ST" 1 01 "OPC" xxxxx PP0"SRC" 0i= iii-0-")\ DEF_ENC32(S4_store##TAG##_ap, ICLASS_ST" 1 01 "OPC" eeeee PP0"SRC" 1-= IIIIII")\ DEF_ENC32(S2_store##TAG##_pr, ICLASS_ST" 1 10 "OPC" xxxxx PPu"SRC" 0-= ------")\ DEF_ENC32(S4_store##TAG##_ur, ICLASS_ST" 1 10 "OPC" uuuuu PPi"SRC" 1i= IIIIII")\ +DEF_ENC32(S2_store##TAG##_pcr, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0-= ----1-")\ =20 =20 #define STD_PST_ENC(TAG,OPC,SRC) \ diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index 78a2ea4..6ce0635 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -26,6 +26,8 @@ Q6INSN(L4_##TAG##_ur, OPER"(Rt32<<#u2+#U6)", = ATTRIB,DESCR,{fMUST_IM Q6INSN(L4_##TAG##_ap, OPER"(Re32=3D#U6)", ATTRIB,DESCR,{= fMUST_IMMEXT(UiV); fEA_IMM(UiV); SEMANTICS; ReV=3DUiV; })\ Q6INSN(L2_##TAG##_pr, OPER"(Rx32++Mu2)", ATTRIB,DESCR,{fE= A_REG(RxV); fPM_M(RxV,MuV); SEMANTICS;})\ Q6INSN(L2_##TAG##_pi, OPER"(Rx32++#s4:"SHFT")", ATTRIB,DESCR,{fE= A_REG(RxV); fPM_I(RxV,siV); SEMANTICS;})\ +Q6INSN(L2_##TAG##_pci, OPER"(Rx32++#s4:"SHFT":circ(Mu2))",ATTRIB,DESCR,{fE= A_REG(RxV); fPM_CIRI(RxV,siV,MuV); SEMANTICS;})\ +Q6INSN(L2_##TAG##_pcr, OPER"(Rx32++I:circ(Mu2))", ATTRIB,DESCR,{fEA_REG(R= xV); fPM_CIRR(RxV,fREAD_IREG(MuV)<>21) | ((VAL>>17)&0x7f) )), = /* behavior */ + () +) + +DEF_MACRO( fREAD_LR, /* read link register */ (READ_RREG(REG_LR)), /* behavior */ () @@ -307,6 +313,12 @@ DEF_MACRO( ) =20 DEF_MACRO( + fREAD_CSREG, /* read CS register */ + (READ_RREG(REG_CSA+N)), /* behavior */ + () +) + +DEF_MACRO( fREAD_LC0, /* read loop count */ (READ_RREG(REG_LC0)), /* behavior */ () @@ -825,6 +837,20 @@ DEF_MACRO( ) =20 DEF_MACRO( + fPM_CIRI, /* Post Modify Register using Circular arithmetic by Immedia= te */ + do { fcirc_add(REG,siV,MuV); } while (0), + () +) + +DEF_MACRO( + fPM_CIRR, /* Post Modify Register using Circular arithmetic by registe= r */ + do { fcirc_add(REG,VAL,MuV); } while (0), + () +) + + + +DEF_MACRO( fSCALE, /* scale by N */ (((size8s_t)(A))<mem_idx); \ } while (0) + +#define MEM_STORE1_FUNC(X) \ + __builtin_choose_expr(TYPE_INT(X), \ + gen_store1i, \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_store1, (void)0)) +#define MEM_STORE1(VA, DATA, SLOT) \ + MEM_STORE1_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) + +#define MEM_STORE2_FUNC(X) \ + __builtin_choose_expr(TYPE_INT(X), \ + gen_store2i, \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_store2, (void)0)) +#define MEM_STORE2(VA, DATA, SLOT) \ + MEM_STORE2_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) + +#define MEM_STORE4_FUNC(X) \ + __builtin_choose_expr(TYPE_INT(X), \ + gen_store4i, \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_store4, (void)0)) +#define MEM_STORE4(VA, DATA, SLOT) \ + MEM_STORE4_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) + +#define MEM_STORE8_FUNC(X) \ + __builtin_choose_expr(TYPE_INT(X), \ + gen_store8i, \ + __builtin_choose_expr(TYPE_TCGV_I64(X), \ + gen_store8, (void)0)) +#define MEM_STORE8(VA, DATA, SLOT) \ + MEM_STORE8_FUNC(DATA)(cpu_env, VA, DATA, ctx, SLOT) #else #define MEM_LOAD1s(VA) ((int8_t)mem_load1(env, slot, VA)) #define MEM_LOAD1u(VA) ((uint8_t)mem_load1(env, slot, VA)) @@ -293,12 +325,48 @@ static inline void gen_logical_not(TCGv dest, TCGv sr= c) =20 #define fPCALIGN(IMM) IMM =3D (IMM & ~PCALIGN_MASK) =20 +#ifdef QEMU_GENERATE +static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift) +{ + /* + * Section 2.2.4 of the Hexagon V67 Programmer's Reference Manual + * + * The "I" value from a modifier register is divided into two pieces + * LSB bits 23:17 + * MSB bits 31:28 + * At the end we shift the result according to the shift argument + */ + TCGv msb =3D tcg_temp_new(); + TCGv lsb =3D tcg_temp_new(); + + tcg_gen_extract_tl(lsb, val, 17, 7); + tcg_gen_extract_tl(msb, val, 28, 4); + tcg_gen_movi_tl(result, 0); + tcg_gen_deposit_tl(result, result, lsb, 0, 7); + tcg_gen_deposit_tl(result, result, msb, 7, 4); + + tcg_gen_shli_tl(result, result, shift); + + tcg_temp_free(msb); + tcg_temp_free(lsb); + + return result; +} +#define fREAD_IREG(VAL, SHIFT) gen_read_ireg(ireg, (VAL), (SHIFT)) +#else +#define fREAD_IREG(VAL) \ + (fSXTN(11, 64, (((VAL) & 0xf0000000) >> 21) | ((VAL >> 17) & 0x7f))) +#endif + #define fREAD_LR() (READ_REG(HEX_REG_LR)) =20 #define fWRITE_LR(A) WRITE_RREG(HEX_REG_LR, A) #define fWRITE_FP(A) WRITE_RREG(HEX_REG_FP, A) #define fWRITE_SP(A) WRITE_RREG(HEX_REG_SP, A) =20 +#ifdef QEMU_GENERATE +#define fREAD_CSREG(N) (READ_REG(tmp, HEX_REG_CS0 + N)) +#else #define fREAD_SP() (READ_REG(HEX_REG_SP)) #define fREAD_LC0 (READ_REG(HEX_REG_LC0)) #define fREAD_LC1 (READ_REG(HEX_REG_LC1)) @@ -313,6 +381,7 @@ static inline void gen_logical_not(TCGv dest, TCGv src) #define fREAD_GP() READ_REG(HEX_REG_GP) #endif #define fREAD_PC() (READ_REG(HEX_REG_PC)) +#endif =20 #define fREAD_NPC() (env->next_PC & (0xfffffffe)) =20 @@ -426,6 +495,14 @@ static inline void gen_logical_not(TCGv dest, TCGv src) #define fEA_REG(REG) tcg_gen_mov_tl(EA, REG) #define fPM_I(REG, IMM) tcg_gen_addi_tl(REG, REG, IMM) #define fPM_M(REG, MVAL) tcg_gen_add_tl(REG, REG, MVAL) +#define fPM_CIRI(REG, IMM, MVAL) \ + do { \ + TCGv tcgv_siV =3D tcg_const_tl(siV); \ + gen_helper_fcircadd(REG, REG, tcgv_siV, MuV, fREAD_CSREG(MuN)); \ + tcg_temp_free(tcgv_siV); \ + } while (0) +#define fPM_CIRR(REG, VAL, MVAL) \ + gen_helper_fcircadd(REG, REG, VAL, MuV, fREAD_CSREG(MuN)) #else #define fEA_IMM(IMM) do { EA =3D (IMM); } while (0) #define fEA_REG(REG) do { EA =3D (REG); } while (0) @@ -502,7 +579,11 @@ static inline void gen_logical_not(TCGv dest, TCGv src) gen_load_locked##SIZE##SIGN(DST, EA, ctx->mem_idx); #endif =20 +#ifdef QEMU_GENERATE +#define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, insn->slot) +#else #define fSTORE(NUM, SIZE, EA, SRC) MEM_STORE##SIZE(EA, SRC, slot) +#endif =20 #ifdef QEMU_GENERATE #define fSTORE_LOCKED(NUM, SIZE, EA, SRC, PRED) \ @@ -536,8 +617,14 @@ static inline void gen_logical_not(TCGv dest, TCGv src) (((uint64_t)((VAL) & 0x0ffLL)) << ((N) * 8)); \ } while (0) #endif + +#ifdef QEMU_GENERATE +#define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true) +#define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false) +#else #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) +#endif #define fSETHALF(N, DST, VAL) \ do { \ DST =3D (DST & ~(0x0ffffLL << ((N) * 16))) | \ diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 18218ad..81f73c0 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -41,6 +41,7 @@ HEX_TESTS +=3D preg_alias HEX_TESTS +=3D dual_stores HEX_TESTS +=3D multi_result HEX_TESTS +=3D mem_noshuf +HEX_TESTS +=3D circ HEX_TESTS +=3D atomics HEX_TESTS +=3D fpstuff =20 diff --git a/tests/tcg/hexagon/circ.c b/tests/tcg/hexagon/circ.c new file mode 100644 index 0000000..cffb910 --- /dev/null +++ b/tests/tcg/hexagon/circ.c @@ -0,0 +1,393 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include + +#define DEBUG 0 +#if DEBUG +#define DEBUG_PRINTF(...) printf(__VA_ARGS__) +#else +#define DEBUG_PRINTF(...) do { } while (0) +#endif + + +#define NBYTES (1 << 8) +#define NHALFS (NBYTES / sizeof(short)) +#define NWORDS (NBYTES / sizeof(int)) +#define NDOBLS (NBYTES / sizeof(long long)) + +long long dbuf[NDOBLS] __attribute__((aligned(1 << 12))) =3D {0}; +int wbuf[NWORDS] __attribute__((aligned(1 << 12))) =3D {0}; +short hbuf[NHALFS] __attribute__((aligned(1 << 12))) =3D {0}; +unsigned char bbuf[NBYTES] __attribute__((aligned(1 << 12))) =3D {0}; + +/* + * We use the C preporcessor to deal with the combinations of types + */ + +#define INIT(BUF, N) \ + void init_##BUF(void) \ + { \ + int i; \ + for (i =3D 0; i < N; i++) { \ + BUF[i] =3D i; \ + } \ + } \ + +INIT(bbuf, NBYTES) +INIT(hbuf, NHALFS) +INIT(wbuf, NWORDS) +INIT(dbuf, NDOBLS) + +/* + * Macros for performing circular load + * RES result + * ADDR address + * START start address of buffer + * LEN length of buffer (in bytes) + * INC address increment (in bytes for IMM, elements for REG) + */ +#define CIRC_LOAD_IMM(SIZE, RES, ADDR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %4\n\t" \ + "m0 =3D r4\n\t" \ + "cs0 =3D %3\n\t" \ + "%0 =3D mem" #SIZE "(%1++#" #INC ":circ(M0))\n\t" \ + : "=3Dr"(RES), "=3Dr"(ADDR) \ + : "1"(ADDR), "r"(START), "r"(LEN) \ + : "r4", "m0", "cs0") +#define CIRC_LOAD_IMM_b(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_IMM(b, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_IMM_ub(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_IMM(ub, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_IMM_h(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_IMM(h, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_IMM_uh(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_IMM(uh, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_IMM_w(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_IMM(w, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_IMM_d(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_IMM(d, RES, ADDR, START, LEN, INC) + +#define CIRC_LOAD_REG(SIZE, RES, ADDR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %3\n\t" \ + "m1 =3D r4\n\t" \ + "cs1 =3D %4\n\t" \ + "%0 =3D mem" #SIZE "(%1++I:circ(M1))\n\t" \ + : "=3Dr"(RES), "=3Dr"(ADDR) \ + : "1"(ADDR), "r"((((INC) & 0x7f) << 17) | ((LEN) & 0x1ffff)), \ + "r"(START) \ + : "r4", "m1", "cs1") +#define CIRC_LOAD_REG_b(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_REG(b, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_REG_ub(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_REG(ub, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_REG_h(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_REG(h, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_REG_uh(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_REG(uh, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_REG_w(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_REG(w, RES, ADDR, START, LEN, INC) +#define CIRC_LOAD_REG_d(RES, ADDR, START, LEN, INC) \ + CIRC_LOAD_REG(d, RES, ADDR, START, LEN, INC) + +/* + * Macros for performing circular store + * VAL value to store + * ADDR address + * START start address of buffer + * LEN length of buffer (in bytes) + * INC address increment (in bytes for IMM, elements for REG) + */ +#define CIRC_STORE_IMM(SIZE, PART, VAL, ADDR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %4\n\t" \ + "m0 =3D r4\n\t" \ + "cs0 =3D %2\n\t" \ + "mem" #SIZE "(%0++#" #INC ":circ(M0)) =3D %3" PART "\n\t" \ + : "=3Dr"(ADDR) \ + : "0"(ADDR), "r"(START), "r"(VAL), "r"(LEN) \ + : "r4", "m0", "cs0", "memory") +#define CIRC_STORE_IMM_b(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_IMM(b, "", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_IMM_h(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_IMM(h, "", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_IMM_f(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_IMM(h, ".H", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_IMM_w(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_IMM(w, "", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_IMM_d(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_IMM(d, "", VAL, ADDR, START, LEN, INC) + +#define CIRC_STORE_NEW_IMM(SIZE, VAL, ADDR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %4\n\t" \ + "m0 =3D r4\n\t" \ + "cs0 =3D %2\n\t" \ + "{\n\t" \ + " r5 =3D %3\n\t" \ + " mem" #SIZE "(%0++#" #INC ":circ(M0)) =3D r5.new\n\t" \ + "}\n\t" \ + : "=3Dr"(ADDR) \ + : "0"(ADDR), "r"(START), "r"(VAL), "r"(LEN) \ + : "r4", "r5", "m0", "cs0", "memory") +#define CIRC_STORE_IMM_bnew(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_NEW_IMM(b, VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_IMM_hnew(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_NEW_IMM(h, VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_IMM_wnew(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_NEW_IMM(w, VAL, ADDR, START, LEN, INC) + +#define CIRC_STORE_REG(SIZE, PART, VAL, ADDR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %2\n\t" \ + "m1 =3D r4\n\t" \ + "cs1 =3D %3\n\t" \ + "mem" #SIZE "(%0++I:circ(M1)) =3D %4" PART "\n\t" \ + : "=3Dr"(ADDR) \ + : "0"(ADDR), \ + "r"((((INC) & 0x7f) << 17) | ((LEN) & 0x1ffff)), \ + "r"(START), \ + "r"(VAL) \ + : "r4", "m1", "cs1", "memory") +#define CIRC_STORE_REG_b(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_REG(b, "", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_REG_h(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_REG(h, "", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_REG_f(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_REG(h, ".H", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_REG_w(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_REG(w, "", VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_REG_d(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_REG(d, "", VAL, ADDR, START, LEN, INC) + +#define CIRC_STORE_NEW_REG(SIZE, VAL, ADDR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %2\n\t" \ + "m1 =3D r4\n\t" \ + "cs1 =3D %3\n\t" \ + "{\n\t" \ + " r5 =3D %4\n\t" \ + " mem" #SIZE "(%0++I:circ(M1)) =3D r5.new\n\t" \ + "}\n\t" \ + : "=3Dr"(ADDR) \ + : "0"(ADDR), \ + "r"((((INC) & 0x7f) << 17) | ((LEN) & 0x1ffff)), \ + "r"(START), \ + "r"(VAL) \ + : "r4", "r5", "m1", "cs1", "memory") +#define CIRC_STORE_REG_bnew(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_NEW_REG(b, VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_REG_hnew(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_NEW_REG(h, VAL, ADDR, START, LEN, INC) +#define CIRC_STORE_REG_wnew(VAL, ADDR, START, LEN, INC) \ + CIRC_STORE_NEW_REG(w, VAL, ADDR, START, LEN, INC) + + +int err; + +void check_load(int i, long long result, int mod) +{ + if (result !=3D (i % mod)) { + printf("ERROR(%d): %lld !=3D %d\n", i, result, i % mod); + err++; + } +} + +#define TEST_LOAD_IMM(SZ, TYPE, BUF, BUFSIZE, INC, FMT) \ +void circ_test_load_imm_##SZ(void) \ +{ \ + TYPE *p =3D (TYPE *)BUF; \ + int size =3D 10; \ + int i; \ + for (i =3D 0; i < BUFSIZE; i++) { \ + TYPE element; \ + CIRC_LOAD_IMM_##SZ(element, p, BUF, size * sizeof(TYPE), INC); \ + DEBUG_PRINTF("i =3D %2d, p =3D 0x%p, element =3D %2" #FMT "\n", \ + i, p, element); \ + check_load(i, element, size); \ + } \ +} + +TEST_LOAD_IMM(b, char, bbuf, NBYTES, 1, d) +TEST_LOAD_IMM(ub, unsigned char, bbuf, NBYTES, 1, d) +TEST_LOAD_IMM(h, short, hbuf, NHALFS, 2, d) +TEST_LOAD_IMM(uh, unsigned short, hbuf, NHALFS, 2, d) +TEST_LOAD_IMM(w, int, wbuf, NWORDS, 4, d) +TEST_LOAD_IMM(d, long long, dbuf, NDOBLS, 8, lld) + +#define TEST_LOAD_REG(SZ, TYPE, BUF, BUFSIZE, FMT) \ +void circ_test_load_reg_##SZ(void) \ +{ \ + TYPE *p =3D (TYPE *)BUF; \ + int size =3D 13; \ + int i; \ + for (i =3D 0; i < BUFSIZE; i++) { \ + TYPE element; \ + CIRC_LOAD_REG_##SZ(element, p, BUF, size * sizeof(TYPE), 1); \ + DEBUG_PRINTF("i =3D %2d, p =3D 0x%p, element =3D %2" #FMT "\n", \ + i, p, element); \ + check_load(i, element, size); \ + } \ +} + +TEST_LOAD_REG(b, char, bbuf, NBYTES, d) +TEST_LOAD_REG(ub, unsigned char, bbuf, NBYTES, d) +TEST_LOAD_REG(h, short, hbuf, NHALFS, d) +TEST_LOAD_REG(uh, unsigned short, hbuf, NHALFS, d) +TEST_LOAD_REG(w, int, wbuf, NWORDS, d) +TEST_LOAD_REG(d, long long, dbuf, NDOBLS, lld) + +#define CIRC_VAL(SZ, TYPE, BUFSIZE) \ +TYPE circ_val_##SZ(int i, int size) \ +{ \ + int mod =3D BUFSIZE % size; \ + if (i < mod) { \ + return (i + BUFSIZE - mod); \ + } else { \ + return (i + BUFSIZE - size - mod); \ + } \ +} + +CIRC_VAL(b, unsigned char, NBYTES) +CIRC_VAL(h, short, NHALFS) +CIRC_VAL(w, int, NWORDS) +CIRC_VAL(d, long long, NDOBLS) + +#define CHECK_STORE(SZ, BUF, BUFSIZE, FMT) \ +void check_store_##SZ(int size) \ +{ \ + int i; \ + for (i =3D 0; i < size; i++) { \ + DEBUG_PRINTF(#BUF "[%3d] =3D 0x%02" #FMT ", guess =3D 0x%02" #FMT = "\n", \ + i, BUF[i], circ_val_##SZ(i, size)); \ + if (BUF[i] !=3D circ_val_##SZ(i, size)) { \ + printf("ERROR(%3d): 0x%02" #FMT " !=3D 0x%02" #FMT "\n", \ + i, BUF[i], circ_val_##SZ(i, size)); \ + err++; \ + } \ + } \ + for (i =3D size; i < BUFSIZE; i++) { \ + if (BUF[i] !=3D i) { \ + printf("ERROR(%3d): 0x%02" #FMT " !=3D 0x%02x\n", i, BUF[i], i= ); \ + err++; \ + } \ + } \ +} + +CHECK_STORE(b, bbuf, NBYTES, x) +CHECK_STORE(h, hbuf, NHALFS, x) +CHECK_STORE(w, wbuf, NWORDS, x) +CHECK_STORE(d, dbuf, NDOBLS, llx) + +#define CIRC_TEST_STORE_IMM(SZ, CHK, TYPE, BUF, BUFSIZE, SHIFT, INC) \ +void circ_test_store_imm_##SZ(void) \ +{ \ + unsigned int size =3D 27; \ + TYPE *p =3D BUF; \ + TYPE val =3D 0; \ + int i; \ + init_##BUF(); \ + for (i =3D 0; i < BUFSIZE; i++) { \ + CIRC_STORE_IMM_##SZ(val << SHIFT, p, BUF, size * sizeof(TYPE), INC= ); \ + val++; \ + } \ + check_store_##CHK(size); \ +} + +CIRC_TEST_STORE_IMM(b, b, unsigned char, bbuf, NBYTES, 0, 1) +CIRC_TEST_STORE_IMM(h, h, short, hbuf, NHALFS, 0, 2) +CIRC_TEST_STORE_IMM(f, h, short, hbuf, NHALFS, 16, 2) +CIRC_TEST_STORE_IMM(w, w, int, wbuf, NWORDS, 0, 4) +CIRC_TEST_STORE_IMM(d, d, long long, dbuf, NDOBLS, 0, 8) +CIRC_TEST_STORE_IMM(bnew, b, unsigned char, bbuf, NBYTES, 0, 1) +CIRC_TEST_STORE_IMM(hnew, h, short, hbuf, NHALFS, 0, 2) +CIRC_TEST_STORE_IMM(wnew, w, int, wbuf, NWORDS, 0, 4) + +#define CIRC_TEST_STORE_REG(SZ, CHK, TYPE, BUF, BUFSIZE, SHIFT) \ +void circ_test_store_reg_##SZ(void) \ +{ \ + TYPE *p =3D BUF; \ + unsigned int size =3D 19; \ + TYPE val =3D 0; \ + int i; \ + init_##BUF(); \ + for (i =3D 0; i < BUFSIZE; i++) { \ + CIRC_STORE_REG_##SZ(val << SHIFT, p, BUF, size * sizeof(TYPE), 1);= \ + val++; \ + } \ + check_store_##CHK(size); \ +} + +CIRC_TEST_STORE_REG(b, b, unsigned char, bbuf, NBYTES, 0) +CIRC_TEST_STORE_REG(h, h, short, hbuf, NHALFS, 0) +CIRC_TEST_STORE_REG(f, h, short, hbuf, NHALFS, 16) +CIRC_TEST_STORE_REG(w, w, int, wbuf, NWORDS, 0) +CIRC_TEST_STORE_REG(d, d, long long, dbuf, NDOBLS, 0) +CIRC_TEST_STORE_REG(bnew, b, unsigned char, bbuf, NBYTES, 0) +CIRC_TEST_STORE_REG(hnew, h, short, hbuf, NHALFS, 0) +CIRC_TEST_STORE_REG(wnew, w, int, wbuf, NWORDS, 0) + +int main() +{ + init_bbuf(); + init_hbuf(); + init_wbuf(); + init_dbuf(); + + DEBUG_PRINTF("NBYTES =3D %d\n", NBYTES); + DEBUG_PRINTF("Address of dbuf =3D 0x%p\n", dbuf); + DEBUG_PRINTF("Address of wbuf =3D 0x%p\n", wbuf); + DEBUG_PRINTF("Address of hbuf =3D 0x%p\n", hbuf); + DEBUG_PRINTF("Address of bbuf =3D 0x%p\n", bbuf); + + circ_test_load_imm_b(); + circ_test_load_imm_ub(); + circ_test_load_imm_h(); + circ_test_load_imm_uh(); + circ_test_load_imm_w(); + circ_test_load_imm_d(); + + circ_test_load_reg_b(); + circ_test_load_reg_ub(); + circ_test_load_reg_h(); + circ_test_load_reg_uh(); + circ_test_load_reg_w(); + circ_test_load_reg_d(); + + circ_test_store_imm_b(); + circ_test_store_imm_h(); + circ_test_store_imm_f(); + circ_test_store_imm_w(); + circ_test_store_imm_d(); + circ_test_store_imm_bnew(); + circ_test_store_imm_hnew(); + circ_test_store_imm_wnew(); + + circ_test_store_reg_b(); + circ_test_store_reg_h(); + circ_test_store_reg_f(); + circ_test_store_reg_w(); + circ_test_store_reg_d(); + circ_test_store_reg_bnew(); + circ_test_store_reg_hnew(); + circ_test_store_reg_wnew(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616641508; cv=none; d=zohomail.com; s=zohoarc; b=WOLXGyCSC3/l8spmhoQlIuFSvaY/9fc2w8x6Jk5ddMptwJWJac1Thp9bPl6ddPejK+digXR9Yi1bkpKfyforNJe890GEnDIkzmy85nD31PKFCqRz7tHl9oY9NEVLey+Tg8uQnVCec2eDBm4gtjPVVThiMeyOvxjmIfNr0fhsTcc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616641508; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Tvw1Ckr3Nha7ZjmlDUZ+vgFUv9bk1TM4e+hLvLAZwWc=; b=G+Ojz0niPQI5Ukp+eigjWEcMqCZV9cSr+0aLrkWG2GuqLzawWJvVW9xp /xtfp3wp4eYmZ36LFm0drTReHdq75mVPMqDxYeZFvLlqD3O0A+VEwxfDR b23boSH2KqxYOU6ueMC9y0RxI/wVLprt7oH71ez8oPcG8sDZwz/N54xHX I=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 12/15] Hexagon (target/hexagon) bit reverse (brev) addressing Date: Wed, 24 Mar 2021 21:50:07 -0500 Message-Id: <1616640610-17319-13-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The following instructions are added L2_loadrub_pbr Rd32 =3D memub(Rx32++Mu2:brev) L2_loadrb_pbr Rd32 =3D memb(Rx32++Mu2:brev) L2_loadruh_pbr Rd32 =3D memuh(Rx32++Mu2:brev) L2_loadrh_pbr Rd32 =3D memh(Rx32++Mu2:brev) L2_loadri_pbr Rd32 =3D memw(Rx32++Mu2:brev) L2_loadrd_pbr Rdd32 =3D memd(Rx32++Mu2:brev) S2_storerb_pbr memb(Rx32++Mu2:brev).=3D.Rt32 S2_storerh_pbr memh(Rx32++Mu2:brev).=3D.Rt32 S2_storerf_pbr memh(Rx32++Mu2:brev).=3D.Rt.H32 S2_storeri_pbr memw(Rx32++Mu2:brev).=3D.Rt32 S2_storerd_pbr memd(Rx32++Mu2:brev).=3D.Rt32 S2_storerinew_pbr memw(Rx32++Mu2:brev).=3D.Nt8.new S2_storerbnew_pbr memw(Rx32++Mu2:brev).=3D.Nt8.new S2_storerhnew_pbr memw(Rx32++Mu2:brev).=3D.Nt8.new Test cases in tests/tcg/hexagon/brev.c Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 28 +++++ target/hexagon/imported/encode_pp.def | 5 + target/hexagon/imported/ldst.idef | 2 + target/hexagon/imported/macros.def | 6 ++ target/hexagon/macros.h | 15 +++ tests/tcg/hexagon/Makefile.target | 1 + tests/tcg/hexagon/brev.c | 185 ++++++++++++++++++++++++++++++= ++++ 7 files changed, 242 insertions(+) create mode 100644 tests/tcg/hexagon/brev.c diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 2d64590..038e16e 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -37,6 +37,7 @@ * _sp stack pointer relative r0 =3D memw(r29+#12) * _ap absolute set r0 =3D memw(r1=3D##vari= able) * _pr post increment register r0 =3D memw(r1++m1) + * _pbr post increment bit reverse r0 =3D memw(r1++m1:brev) * _pi post increment immediate r0 =3D memb(r1++#1) * _pci post increment circular immediate r0 =3D memw(r1++#4:circ= (m0)) * _pcr post increment circular register r0 =3D memw(r1++I:circ(= m0)) @@ -53,6 +54,11 @@ fEA_REG(RxV); \ fPM_M(RxV, MuV); \ } while (0) +#define GET_EA_pbr \ + do { \ + fEA_BREVR(RxV); \ + fPM_M(RxV, MuV); \ + } while (0) #define GET_EA_pi \ do { \ fEA_REG(RxV); \ @@ -142,16 +148,22 @@ fGEN_TCG_PCR(3, fLOAD(1, 8, u, EA, RddV)) =20 #define fGEN_TCG_L2_loadrub_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrub_pbr(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrub_pi(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrb_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrb_pbr(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrb_pi(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadruh_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadruh_pbr(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadruh_pi(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrh_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrh_pbr(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrh_pi(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadri_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadri_pbr(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadri_pi(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrd_pr(SHORTCODE) SHORTCODE +#define fGEN_TCG_L2_loadrd_pbr(SHORTCODE) SHORTCODE #define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE =20 /* @@ -282,41 +294,57 @@ tcg_temp_free(tmp); \ } while (0) =20 +#define fGEN_TCG_S2_storerb_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerb_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerb_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, RtV))) =20 +#define fGEN_TCG_S2_storerh_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerh_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerh_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, RtV))) =20 +#define fGEN_TCG_S2_storerf_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerf_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerf_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(1, RtV))) =20 +#define fGEN_TCG_S2_storeri_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storeri_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storeri_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, RtV)) =20 +#define fGEN_TCG_S2_storerd_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerd_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerd_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(3, fSTORE(1, 8, EA, RttV)) =20 +#define fGEN_TCG_S2_storerbnew_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerbnew_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerbnew_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(0, fSTORE(1, 1, EA, fGETBYTE(0, NtN))) =20 +#define fGEN_TCG_S2_storerhnew_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerhnew_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerhnew_pcr(SHORTCODE) \ fGEN_TCG_STORE_pcr(1, fSTORE(1, 2, EA, fGETHALF(0, NtN))) =20 +#define fGEN_TCG_S2_storerinew_pbr(SHORTCODE) \ + fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerinew_pci(SHORTCODE) \ fGEN_TCG_STORE(SHORTCODE) #define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \ diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index c97219f..4464926 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -301,6 +301,7 @@ DEF_CLASS32(ICLASS_LD" 101- -------- PP1----- --------"= ,LD_ADDR_POST_IMMED_PRED_ DEF_CLASS32(ICLASS_LD" 110- -------- PP-0---- 0-------",LD_ADDR_POST_REG) DEF_CLASS32(ICLASS_LD" 110- -------- PP-1---- --------",LD_ADDR_ABS_PLUS_R= EG_V4) DEF_CLASS32(ICLASS_LD" 100- -------- PP----1- --------",LD_ADDR_POST_CREG_= V2) +DEF_CLASS32(ICLASS_LD" 111- -------- PP------ 0-------",LD_ADDR_POST_BREV_= REG) DEF_CLASS32(ICLASS_LD" 111- -------- PP------ 1-------",LD_ADDR_PRED_ABS_V= 4) =20 DEF_FIELD32(ICLASS_LD" !!!- -------- PP------ --------",LD_Amode,"Amode") @@ -315,6 +316,7 @@ DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" e= eeee PP01IIII -IIddddd" DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--= ddddd")\ DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iII= ddddd")\ DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--= ddddd")\ +DEF_ENC32(L2_load##TAG##_pbr, ICLASS_LD" 1 11 "OPC" xxxxx PPu0---- 0--= ddddd") =20 =20 #define STD_LDX_ENC(TAG,OPC) \ @@ -325,6 +327,7 @@ DEF_ENC32(L4_load##TAG##_ap, ICLASS_LD" 1 01 "OPC" e= eeee PP01IIII -IIyyyyy" DEF_ENC32(L2_load##TAG##_pr, ICLASS_LD" 1 10 "OPC" xxxxx PPu0---- 0--= yyyyy")\ DEF_ENC32(L4_load##TAG##_ur, ICLASS_LD" 1 10 "OPC" ttttt PPi1IIII iII= yyyyy")\ DEF_ENC32(L2_load##TAG##_pcr, ICLASS_LD" 1 00 "OPC" xxxxx PPu0--1- 0--= yyyyy")\ +DEF_ENC32(L2_load##TAG##_pbr, ICLASS_LD" 1 11 "OPC" xxxxx PPu0---- 0--= yyyyy") =20 =20 #define STD_PLD_ENC(TAG,OPC) \ @@ -411,6 +414,7 @@ DEF_CLASS32(ICLASS_ST" 1111 -------- PP------ 1-------"= ,ST_ADDR_PRED_ABS_V4) DEF_CLASS32(ICLASS_ST" 1101 -------- PP------ 0-------",ST_ADDR_POST_REG) DEF_CLASS32(ICLASS_ST" 1101 -------- PP------ 1-------",ST_ADDR_ABS_PLUS_R= EG_V4) DEF_CLASS32(ICLASS_ST" 1001 -------- PP------ ------1-",ST_ADDR_POST_CREG_= V2) +DEF_CLASS32(ICLASS_ST" 1111 -------- PP------ 0-------",ST_ADDR_POST_BREV_= REG) DEF_CLASS32(ICLASS_ST" 0--0 1------- PP------ --------",ST_MISC_STORELIKE) DEF_CLASS32(ICLASS_ST" 1--0 0------- PP------ --------",ST_MISC_BUSOP) DEF_CLASS32(ICLASS_ST" 0--0 0------- PP------ --------",ST_MISC_CACHEOP) @@ -424,6 +428,7 @@ DEF_ENC32(S4_store##TAG##_ap, ICLASS_ST" 1 01 "OPC" = eeeee PP0"SRC" 1-IIIIII DEF_ENC32(S2_store##TAG##_pr, ICLASS_ST" 1 10 "OPC" xxxxx PPu"SRC" 0-= ------")\ DEF_ENC32(S4_store##TAG##_ur, ICLASS_ST" 1 10 "OPC" uuuuu PPi"SRC" 1i= IIIIII")\ DEF_ENC32(S2_store##TAG##_pcr, ICLASS_ST" 1 00 "OPC" xxxxx PPu"SRC" 0-= ----1-")\ +DEF_ENC32(S2_store##TAG##_pbr, ICLASS_ST" 1 11 "OPC" xxxxx PPu"SRC" 0-= ------") =20 =20 #define STD_PST_ENC(TAG,OPC,SRC) \ diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index 6ce0635..fe7e018 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -25,6 +25,7 @@ Q6INSN(L2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")", = ATTRIB,DESCR,{fIMMEXT( Q6INSN(L4_##TAG##_ur, OPER"(Rt32<<#u2+#U6)", ATTRIB,DESCR,{fM= UST_IMMEXT(UiV); fEA_IRs(UiV,RtV,uiV); SEMANTICS;})\ Q6INSN(L4_##TAG##_ap, OPER"(Re32=3D#U6)", ATTRIB,DESCR,{= fMUST_IMMEXT(UiV); fEA_IMM(UiV); SEMANTICS; ReV=3DUiV; })\ Q6INSN(L2_##TAG##_pr, OPER"(Rx32++Mu2)", ATTRIB,DESCR,{fE= A_REG(RxV); fPM_M(RxV,MuV); SEMANTICS;})\ +Q6INSN(L2_##TAG##_pbr, OPER"(Rx32++Mu2:brev)", ATTRIB,DESCR,{fE= A_BREVR(RxV); fPM_M(RxV,MuV); SEMANTICS;})\ Q6INSN(L2_##TAG##_pi, OPER"(Rx32++#s4:"SHFT")", ATTRIB,DESCR,{fE= A_REG(RxV); fPM_I(RxV,siV); SEMANTICS;})\ Q6INSN(L2_##TAG##_pci, OPER"(Rx32++#s4:"SHFT":circ(Mu2))",ATTRIB,DESCR,{fE= A_REG(RxV); fPM_CIRI(RxV,siV,MuV); SEMANTICS;})\ Q6INSN(L2_##TAG##_pcr, OPER"(Rx32++I:circ(Mu2))", ATTRIB,DESCR,{fEA_REG(R= xV); fPM_CIRR(RxV,fREAD_IREG(MuV)<. + */ + +#include +#include + +#define NBITS 8 +#define SIZE (1 << NBITS) + +long long dbuf[SIZE] __attribute__((aligned(1 << 16))) =3D {0}; +int wbuf[SIZE] __attribute__((aligned(1 << 16))) =3D {0}; +short hbuf[SIZE] __attribute__((aligned(1 << 16))) =3D {0}; +unsigned char bbuf[SIZE] __attribute__((aligned(1 << 16))) =3D {0}; + +/* + * We use the C preporcessor to deal with the combinations of types + */ + +int err; + +#define BREV_LOAD(SZ, RES, ADDR, INC) \ + __asm__( \ + "m0 =3D %2\n\t" \ + "%0 =3D mem" #SZ "(%1++m0:brev)\n\t" \ + : "=3Dr"(RES), "+r"(ADDR) \ + : "r"(INC) \ + : "m0") + +#define BREV_LOAD_b(RES, ADDR, INC) \ + BREV_LOAD(b, RES, ADDR, INC) +#define BREV_LOAD_ub(RES, ADDR, INC) \ + BREV_LOAD(ub, RES, ADDR, INC) +#define BREV_LOAD_h(RES, ADDR, INC) \ + BREV_LOAD(h, RES, ADDR, INC) +#define BREV_LOAD_uh(RES, ADDR, INC) \ + BREV_LOAD(uh, RES, ADDR, INC) +#define BREV_LOAD_w(RES, ADDR, INC) \ + BREV_LOAD(w, RES, ADDR, INC) +#define BREV_LOAD_d(RES, ADDR, INC) \ + BREV_LOAD(d, RES, ADDR, INC) + +#define BREV_STORE(SZ, PART, ADDR, VAL, INC) \ + __asm__( \ + "m0 =3D %2\n\t" \ + "mem" #SZ "(%0++m0:brev) =3D %1" PART "\n\t" \ + : "+r"(ADDR) \ + : "r"(VAL), "r"(INC) \ + : "m0", "memory") + +#define BREV_STORE_b(ADDR, VAL, INC) \ + BREV_STORE(b, "", ADDR, VAL, INC) +#define BREV_STORE_h(ADDR, VAL, INC) \ + BREV_STORE(h, "", ADDR, VAL, INC) +#define BREV_STORE_f(ADDR, VAL, INC) \ + BREV_STORE(h, ".H", ADDR, VAL, INC) +#define BREV_STORE_w(ADDR, VAL, INC) \ + BREV_STORE(w, "", ADDR, VAL, INC) +#define BREV_STORE_d(ADDR, VAL, INC) \ + BREV_STORE(d, "", ADDR, VAL, INC) + +#define BREV_STORE_NEW(SZ, ADDR, VAL, INC) \ + __asm__( \ + "m0 =3D %2\n\t" \ + "{\n\t" \ + " r5 =3D %1\n\t" \ + " mem" #SZ "(%0++m0:brev) =3D r5.new\n\t" \ + "}\n\t" \ + : "+r"(ADDR) \ + : "r"(VAL), "r"(INC) \ + : "m0", "memory") + +#define BREV_STORE_bnew(ADDR, VAL, INC) \ + BREV_STORE_NEW(b, ADDR, VAL, INC) +#define BREV_STORE_hnew(ADDR, VAL, INC) \ + BREV_STORE_NEW(h, ADDR, VAL, INC) +#define BREV_STORE_wnew(ADDR, VAL, INC) \ + BREV_STORE_NEW(w, ADDR, VAL, INC) +#define BREV_STORE_dnew(ADDR, VAL, INC) \ + BREV_STORE_NEW(d, ADDR, VAL, INC) + +int bitreverse(int x) +{ + int result =3D 0; + int i; + for (i =3D 0; i < NBITS; i++) { + result <<=3D 1; + result |=3D x & 1; + x >>=3D 1; + } + return result; +} + +int sext8(int x) +{ + return (x << 24) >> 24; +} + +void check(int i, long long result, long long expect) +{ + if (result !=3D expect) { + printf("ERROR(%d): 0x%04llx !=3D 0x%04llx\n", i, result, expect); + err++; + } +} + +#define TEST_BREV_LOAD(SZ, TYPE, BUF, SHIFT, EXP) \ + do { \ + p =3D BUF; \ + for (i =3D 0; i < SIZE; i++) { \ + TYPE result; \ + BREV_LOAD_##SZ(result, p, 1 << (SHIFT - NBITS)); \ + check(i, result, EXP); \ + } \ + } while (0) + +#define TEST_BREV_STORE(SZ, TYPE, BUF, SH, SHIFT) \ + do { \ + p =3D BUF; \ + memset(BUF, 0xff, sizeof(BUF)); \ + for (i =3D 0; i < SIZE; i++) { \ + BREV_STORE_##SZ(p, (TYPE)i << SH, 1 << (SHIFT - NBITS)); \ + } \ + for (i =3D 0; i < SIZE; i++) { \ + check(i, BUF[i], bitreverse(i)); \ + } \ + } while (0) + +#define TEST_BREV_STORE_NEW(SZ, TYPE, BUF, SHIFT) \ + do { \ + p =3D BUF; \ + memset(BUF, 0xff, sizeof(BUF)); \ + for (i =3D 0; i < SIZE; i++) { \ + BREV_STORE_##SZ(p, (TYPE)i, 1 << (SHIFT - NBITS)); \ + } \ + for (i =3D 0; i < SIZE; i++) { \ + check(i, BUF[i], bitreverse(i)); \ + } \ + } while (0) + +int main() +{ + void *p; + int i; + + for (i =3D 0; i < SIZE; i++) { + bbuf[i] =3D bitreverse(i); + hbuf[i] =3D bitreverse(i); + wbuf[i] =3D bitreverse(i); + dbuf[i] =3D bitreverse(i); + } + + TEST_BREV_LOAD(b, signed char, bbuf, 16, sext8(i)); + TEST_BREV_LOAD(ub, unsigned char, bbuf, 16, i); + TEST_BREV_LOAD(h, short, hbuf, 15, i); + TEST_BREV_LOAD(uh, unsigned short, hbuf, 15, i); + TEST_BREV_LOAD(w, int, wbuf, 14, i); + TEST_BREV_LOAD(d, long long, dbuf, 13, i); + + TEST_BREV_STORE(b, char, bbuf, 0, 16); + TEST_BREV_STORE(h, short, hbuf, 0, 15); + TEST_BREV_STORE(f, short, hbuf, 16, 15); + TEST_BREV_STORE(w, int, wbuf, 0, 14); + TEST_BREV_STORE(d, long long, dbuf, 0, 13); + + TEST_BREV_STORE_NEW(bnew, char, bbuf, 16); + TEST_BREV_STORE_NEW(hnew, short, hbuf, 15); + TEST_BREV_STORE_NEW(wnew, int, wbuf, 14); + + puts(err ? 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X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 13/15] Hexagon (target/hexagon) load and unpack bytes instructions Date: Wed, 24 Mar 2021 21:50:08 -0500 Message-Id: <1616640610-17319-14-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.39; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-02.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The following instructions are added L2_loadbzw2_io Rd32 =3D memubh(Rs32+#s11:1) L2_loadbzw4_io Rdd32 =3D memubh(Rs32+#s11:1) L2_loadbsw2_io Rd32 =3D membh(Rs32+#s11:1) L2_loadbsw4_io Rdd32 =3D membh(Rs32+#s11:1) L4_loadbzw2_ur Rd32 =3D memubh(Rt32<<#u2+#U6) L4_loadbzw4_ur Rdd32 =3D memubh(Rt32<<#u2+#U6) L4_loadbsw2_ur Rd32 =3D membh(Rt32<<#u2+#U6) L4_loadbsw4_ur Rdd32 =3D membh(Rt32<<#u2+#U6) L4_loadbzw2_ap Rd32 =3D memubh(Re32=3D#U6) L4_loadbzw4_ap Rdd32 =3D memubh(Re32=3D#U6) L4_loadbsw2_ap Rd32 =3D membh(Re32=3D#U6) L4_loadbsw4_ap Rdd32 =3D membh(Re32=3D#U6) L2_loadbzw2_pr Rd32 =3D memubh(Rx32++Mu2) L2_loadbzw4_pr Rdd32 =3D memubh(Rx32++Mu2) L2_loadbsw2_pr Rd32 =3D membh(Rx32++Mu2) L2_loadbsw4_pr Rdd32 =3D membh(Rx32++Mu2) L2_loadbzw2_pbr Rd32 =3D memubh(Rx32++Mu2:brev) L2_loadbzw4_pbr Rdd32 =3D memubh(Rx32++Mu2:brev) L2_loadbsw2_pbr Rd32 =3D membh(Rx32++Mu2:brev) L2_loadbsw4_pbr Rdd32 =3D membh(Rx32++Mu2:brev) L2_loadbzw2_pi Rd32 =3D memubh(Rx32++#s4:1) L2_loadbzw4_pi Rdd32 =3D memubh(Rx32++#s4:1) L2_loadbsw2_pi Rd32 =3D membh(Rx32++#s4:1) L2_loadbsw4_pi Rdd32 =3D membh(Rx32++#s4:1) L2_loadbzw2_pci Rd32 =3D memubh(Rx32++#s4:1:circ(Mu2)) L2_loadbzw4_pci Rdd32 =3D memubh(Rx32++#s4:1:circ(Mu2)) L2_loadbsw2_pci Rd32 =3D membh(Rx32++#s4:1:circ(Mu2)) L2_loadbsw4_pci Rdd32 =3D membh(Rx32++#s4:1:circ(Mu2)) L2_loadbzw2_pcr Rd32 =3D memubh(Rx32++I:circ(Mu2)) L2_loadbzw4_pcr Rdd32 =3D memubh(Rx32++I:circ(Mu2)) L2_loadbsw2_pcr Rd32 =3D membh(Rx32++I:circ(Mu2)) L2_loadbsw4_pcr Rdd32 =3D membh(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_unpack.c Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 118 +++++++++ target/hexagon/genptr.c | 13 + target/hexagon/imported/encode_pp.def | 6 + target/hexagon/imported/ldst.idef | 43 +++ target/hexagon/macros.h | 27 +- tests/tcg/hexagon/Makefile.target | 1 + tests/tcg/hexagon/load_unpack.c | 474 ++++++++++++++++++++++++++++++= ++++ 7 files changed, 681 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/hexagon/load_unpack.c diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 038e16e..55ba5f2 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -167,6 +167,124 @@ #define fGEN_TCG_L2_loadrd_pi(SHORTCODE) SHORTCODE =20 /* + * These instructions load 2 bytes and places them in + * two halves of the destination register. + * The GET_EA macro determines the addressing mode. + * The fGB macro determines whether to zero-extend or + * sign-extend. + */ +#define fGEN_TCG_loadbXw2(GET_EA, fGB) \ + do { \ + TCGv ireg =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + TCGv tmpV =3D tcg_temp_new(); \ + TCGv BYTE =3D tcg_temp_new(); \ + int i; \ + GET_EA; \ + fLOAD(1, 2, u, EA, tmpV); \ + tcg_gen_movi_tl(RdV, 0); \ + for (i =3D 0; i < 2; i++) { \ + fSETHALF(i, RdV, fGB(i, tmpV)); \ + } \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free(BYTE); \ + } while (0) + +#define fGEN_TCG_L2_loadbzw2_io(SHORTCODE) \ + fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), fGETUBYTE) +#define fGEN_TCG_L4_loadbzw2_ur(SHORTCODE) \ + fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), fGETUBYTE) +#define fGEN_TCG_L2_loadbsw2_io(SHORTCODE) \ + fGEN_TCG_loadbXw2(fEA_RI(RsV, siV), fGETBYTE) +#define fGEN_TCG_L4_loadbsw2_ur(SHORTCODE) \ + fGEN_TCG_loadbXw2(fEA_IRs(UiV, RtV, uiV), fGETBYTE) +#define fGEN_TCG_L4_loadbzw2_ap(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_ap, fGETUBYTE) +#define fGEN_TCG_L2_loadbzw2_pr(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pr, fGETUBYTE) +#define fGEN_TCG_L2_loadbzw2_pbr(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pbr, fGETUBYTE) +#define fGEN_TCG_L2_loadbzw2_pi(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pi, fGETUBYTE) +#define fGEN_TCG_L4_loadbsw2_ap(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_ap, fGETBYTE) +#define fGEN_TCG_L2_loadbsw2_pr(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pr, fGETBYTE) +#define fGEN_TCG_L2_loadbsw2_pbr(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pbr, fGETBYTE) +#define fGEN_TCG_L2_loadbsw2_pi(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pi, fGETBYTE) +#define fGEN_TCG_L2_loadbzw2_pci(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pci, fGETUBYTE) +#define fGEN_TCG_L2_loadbsw2_pci(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pci, fGETBYTE) +#define fGEN_TCG_L2_loadbzw2_pcr(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pcr(1), fGETUBYTE) +#define fGEN_TCG_L2_loadbsw2_pcr(SHORTCODE) \ + fGEN_TCG_loadbXw2(GET_EA_pcr(1), fGETBYTE) + +/* + * These instructions load 4 bytes and places them in + * four halves of the destination register pair. + * The GET_EA macro determines the addressing mode. + * The fGB macro determines whether to zero-extend or + * sign-extend. + */ +#define fGEN_TCG_loadbXw4(GET_EA, fGB) \ + do { \ + TCGv ireg =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + TCGv tmpV =3D tcg_temp_new(); \ + TCGv BYTE =3D tcg_temp_new(); \ + int i; \ + GET_EA; \ + fLOAD(1, 4, u, EA, tmpV); \ + tcg_gen_movi_i64(RddV, 0); \ + for (i =3D 0; i < 4; i++) { \ + fSETHALF(i, RddV, fGB(i, tmpV)); \ + } \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free(BYTE); \ + } while (0) + +#define fGEN_TCG_L2_loadbzw4_io(SHORTCODE) \ + fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), fGETUBYTE) +#define fGEN_TCG_L4_loadbzw4_ur(SHORTCODE) \ + fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), fGETUBYTE) +#define fGEN_TCG_L2_loadbsw4_io(SHORTCODE) \ + fGEN_TCG_loadbXw4(fEA_RI(RsV, siV), fGETBYTE) +#define fGEN_TCG_L4_loadbsw4_ur(SHORTCODE) \ + fGEN_TCG_loadbXw4(fEA_IRs(UiV, RtV, uiV), fGETBYTE) +#define fGEN_TCG_L2_loadbzw4_pci(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pci, fGETUBYTE) +#define fGEN_TCG_L2_loadbsw4_pci(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pci, fGETBYTE) +#define fGEN_TCG_L2_loadbzw4_pcr(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pcr(2), fGETUBYTE) +#define fGEN_TCG_L2_loadbsw4_pcr(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pcr(2), fGETBYTE) +#define fGEN_TCG_L4_loadbzw4_ap(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_ap, fGETUBYTE) +#define fGEN_TCG_L2_loadbzw4_pr(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pr, fGETUBYTE) +#define fGEN_TCG_L2_loadbzw4_pbr(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pbr, fGETUBYTE) +#define fGEN_TCG_L2_loadbzw4_pi(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pi, fGETUBYTE) +#define fGEN_TCG_L4_loadbsw4_ap(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_ap, fGETBYTE) +#define fGEN_TCG_L2_loadbsw4_pr(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pr, fGETBYTE) +#define fGEN_TCG_L2_loadbsw4_pbr(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pbr, fGETBYTE) +#define fGEN_TCG_L2_loadbsw4_pi(SHORTCODE) \ + fGEN_TCG_loadbXw4(GET_EA_pi, fGETBYTE) + +/* * Predicated loads * Here is a primer to understand the tag names * diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index aaa2901..3e1d7ba 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -308,6 +308,19 @@ static inline TCGv gen_get_half(TCGv result, int N, TC= Gv src, bool sign) return result; } =20 +static inline void gen_set_half(int N, TCGv result, TCGv src) +{ + tcg_gen_deposit_tl(result, result, src, N * 16, 16); +} + +static inline void gen_set_half_i64(int N, TCGv_i64 result, TCGv src) +{ + TCGv_i64 src64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(src64, src); + tcg_gen_deposit_i64(result, result, src64, N * 16, 16); + tcg_temp_free_i64(src64); +} + static inline void gen_set_byte(int N, TCGv result, TCGv src) { tcg_gen_deposit_tl(result, result, src, N * 8, 8); diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index 4464926..e3582eb 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -342,6 +342,12 @@ DEF_ENC32(L4_pload##TAG##fnew_abs,ICLASS_LD" 1 11 "OPC= " iiiii PP111tti 1--ddd =20 =20 /* 0 000 misc: dealloc,loadw_locked,dcfetch */ +STD_LD_ENC(bzw4,"0 101") +STD_LD_ENC(bzw2,"0 011") + +STD_LD_ENC(bsw4,"0 111") +STD_LD_ENC(bsw2,"0 001") + STD_LD_ENC(rb, "1 000") STD_LD_ENC(rub, "1 001") STD_LD_ENC(rh, "1 010") diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index fe7e018..95c0470 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -38,6 +38,49 @@ STD_LD_AMODES(loadrh, "Rd32=3Dmemh", "Load signed Half i= nteger",ATTRIBS(A_LOAD),"1 STD_LD_AMODES(loadri, "Rd32=3Dmemw", "Load Word",ATTRIBS(A_LOAD),"2",fLOAD= (1,4,u,EA,RdV),2) STD_LD_AMODES(loadrd, "Rdd32=3Dmemd","Load Double integer",ATTRIBS(A_LOAD)= ,"3",fLOAD(1,8,u,EA,RddV),3) =20 +/* These instructions do a load an unpack */ +STD_LD_AMODES(loadbzw2, "Rd32=3Dmemubh", "Load Bytes and Vector Zero-Exten= d (unpack)", +ATTRIBS(A_LOAD),"1", +{fHIDE(size2u_t tmpV; int i;) + fLOAD(1,2,u,EA,tmpV); + for (i=3D0;i<2;i++) { + fSETHALF(i,RdV,fGETUBYTE(i,tmpV)); + } +},1) + +STD_LD_AMODES(loadbzw4, "Rdd32=3Dmemubh", "Load Bytes and Vector Zero-Exte= nd (unpack)", +ATTRIBS(A_LOAD),"2", +{fHIDE(size4u_t tmpV; int i;) + fLOAD(1,4,u,EA,tmpV); + for (i=3D0;i<4;i++) { + fSETHALF(i,RddV,fGETUBYTE(i,tmpV)); + } +},2) + + + +/* These instructions do a load an unpack */ +STD_LD_AMODES(loadbsw2, "Rd32=3Dmembh", "Load Bytes and Vector Sign-Extend= (unpack)", +ATTRIBS(A_LOAD),"1", +{fHIDE(size2u_t tmpV; int i;) + fLOAD(1,2,u,EA,tmpV); + for (i=3D0;i<2;i++) { + fSETHALF(i,RdV,fGETBYTE(i,tmpV)); + } +},1) + +STD_LD_AMODES(loadbsw4, "Rdd32=3Dmembh", "Load Bytes and Vector Sign-Exten= d (unpack)", +ATTRIBS(A_LOAD),"2", +{fHIDE(size4u_t tmpV; int i;) + fLOAD(1,4,u,EA,tmpV); + for (i=3D0;i<4;i++) { + fSETHALF(i,RddV,fGETBYTE(i,tmpV)); + } +},2) + + + + /* The set of addressing modes standard to all Store instructions */ #define STD_ST_AMODES(TAG,DEST,OPER,DESCR,ATTRIB,SHFT,SEMANTICS,SCALE)\ Q6INSN(S2_##TAG##_io, OPER"(Rs32+#s11:"SHFT")=3D"DEST, ATTRIB,DESCR,{= fIMMEXT(siV); fEA_RI(RsV,siV); SEMANTICS; })\ diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index ce2b3d2..e4aec8d 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -477,6 +477,21 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val= , int shift) #define fCAST8S_16S(A) (int128_exts64(A)) #define fCAST16S_8S(A) (int128_getlo(A)) =20 +#ifdef QEMU_GENERATE +#define fEA_RI(REG, IMM) tcg_gen_addi_tl(EA, REG, IMM) +#define fEA_RRs(REG, REG2, SCALE) \ + do { \ + TCGv tmp =3D tcg_temp_new(); \ + tcg_gen_shli_tl(tmp, REG2, SCALE); \ + tcg_gen_add_tl(EA, REG, tmp); \ + tcg_temp_free(tmp); \ + } while (0) +#define fEA_IRs(IMM, REG, SCALE) \ + do { \ + tcg_gen_shli_tl(EA, REG, SCALE); \ + tcg_gen_addi_tl(EA, EA, IMM); \ + } while (0) +#else #define fEA_RI(REG, IMM) \ do { \ EA =3D REG + IMM; \ @@ -489,6 +504,7 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val,= int shift) do { \ EA =3D IMM + (REG << SCALE); \ } while (0) +#endif =20 #ifdef QEMU_GENERATE #define fEA_IMM(IMM) tcg_gen_movi_tl(EA, IMM) @@ -636,10 +652,18 @@ static inline void gen_fbrev(TCGv result, TCGv src) #ifdef QEMU_GENERATE #define fGETHALF(N, SRC) gen_get_half(HALF, N, SRC, true) #define fGETUHALF(N, SRC) gen_get_half(HALF, N, SRC, false) + +#define SETHALF_FUNC(X) \ + __builtin_choose_expr(TYPE_TCGV(X), \ + gen_set_half, \ + __builtin_choose_expr(TYPE_TCGV_I64(X), \ + gen_set_half_i64, (void)0)) +#define fSETHALF(N, DST, VAL) SETHALF_FUNC(DST)(N, DST, VAL) +#define fSETHALFw(N, DST, VAL) gen_set_half(N, DST, VAL) +#define fSETHALFd(N, DST, VAL) gen_set_half_i64(N, DST, VAL) #else #define fGETHALF(N, SRC) ((int16_t)((SRC >> ((N) * 16)) & 0xffff)) #define fGETUHALF(N, SRC) ((uint16_t)((SRC >> ((N) * 16)) & 0xffff)) -#endif #define fSETHALF(N, DST, VAL) \ do { \ DST =3D (DST & ~(0x0ffffLL << ((N) * 16))) | \ @@ -647,6 +671,7 @@ static inline void gen_fbrev(TCGv result, TCGv src) } while (0) #define fSETHALFw fSETHALF #define fSETHALFd fSETHALF +#endif =20 #ifdef QEMU_GENERATE #define GETWORD_FUNC(X) \ diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 98cd4ab..5411eee 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -43,6 +43,7 @@ HEX_TESTS +=3D multi_result HEX_TESTS +=3D mem_noshuf HEX_TESTS +=3D circ HEX_TESTS +=3D brev +HEX_TESTS +=3D load_unpack HEX_TESTS +=3D atomics HEX_TESTS +=3D fpstuff =20 diff --git a/tests/tcg/hexagon/load_unpack.c b/tests/tcg/hexagon/load_unpac= k.c new file mode 100644 index 0000000..3575a37 --- /dev/null +++ b/tests/tcg/hexagon/load_unpack.c @@ -0,0 +1,474 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * Test load unpack instructions + * + * Example + * r0 =3D memubh(r1+#0) + * loads a half word from memory and zero-extends the 2 bytes to form a wo= rd + * + * For each addressing mode, there are 4 tests + * bzw2 unsigned 2 elements + * bsw2 signed 2 elements + * bzw4 unsigned 4 elements + * bsw4 signed 4 elements + * There are 8 addressing modes, for a total of 32 instructions to test + */ + +#include +#include + +int err; + +char buf[16] __attribute__((aligned(1 << 16))); + +void init_buf(void) +{ + int i; + for (i =3D 0; i < 16; i++) { + int sign =3D i % 2 =3D=3D 0 ? 0x80 : 0; + buf[i] =3D sign | (i + 1); + } +} + +void __check(int line, long long result, long long expect) +{ + if (result !=3D expect) { + printf("ERROR at line %d: 0x%08llx !=3D 0x%08llx\n", + line, result, expect); + err++; + } +} + +#define check(RES, EXP) __check(__LINE__, RES, EXP) + +void __checkp(int line, void *p, void *expect) +{ + if (p !=3D expect) { + printf("ERROR at line %d: 0x%p !=3D 0x%p\n", line, p, expect); + err++; + } +} + +#define checkp(RES, EXP) __checkp(__LINE__, RES, EXP) + +/* + *************************************************************************= *** + * _io addressing mode (addr + offset) + */ +#define BxW_LOAD_io(SZ, RES, ADDR, OFF) \ + __asm__( \ + "%0 =3D mem" #SZ "(%1+#" #OFF ")\n\t" \ + : "=3Dr"(RES) \ + : "r"(ADDR)) +#define BxW_LOAD_io_Z(RES, ADDR, OFF) \ + BxW_LOAD_io(ubh, RES, ADDR, OFF) +#define BxW_LOAD_io_S(RES, ADDR, OFF) \ + BxW_LOAD_io(bh, RES, ADDR, OFF) + +#define TEST_io(NAME, TYPE, SIGN, SIZE, EXT, EXP1, EXP2, EXP3, EXP4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + init_buf(); \ + BxW_LOAD_io_##SIGN(result, buf, 0 * (SIZE)); \ + check(result, (EXP1) | (EXT)); \ + BxW_LOAD_io_##SIGN(result, buf, 1 * (SIZE)); \ + check(result, (EXP2) | (EXT)); \ + BxW_LOAD_io_##SIGN(result, buf, 2 * (SIZE)); \ + check(result, (EXP3) | (EXT)); \ + BxW_LOAD_io_##SIGN(result, buf, 3 * (SIZE)); \ + check(result, (EXP4) | (EXT)); \ +} + + +TEST_io(loadbzw2_io, int, Z, 2, 0x00000000, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_io(loadbsw2_io, int, S, 2, 0x0000ff00, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_io(loadbzw4_io, long long, Z, 4, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) +TEST_io(loadbsw4_io, long long, S, 4, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) + +/* + *************************************************************************= *** + * _ur addressing mode (index << offset + base) + */ +#define BxW_LOAD_ur(SZ, RES, SHIFT, IDX) \ + __asm__( \ + "%0 =3D mem" #SZ "(%1<<#" #SHIFT " + ##buf)\n\t" \ + : "=3Dr"(RES) \ + : "r"(IDX)) +#define BxW_LOAD_ur_Z(RES, SHIFT, IDX) \ + BxW_LOAD_ur(ubh, RES, SHIFT, IDX) +#define BxW_LOAD_ur_S(RES, SHIFT, IDX) \ + BxW_LOAD_ur(bh, RES, SHIFT, IDX) + +#define TEST_ur(NAME, TYPE, SIGN, SHIFT, EXT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + init_buf(); \ + BxW_LOAD_ur_##SIGN(result, (SHIFT), 0); \ + check(result, (RES1) | (EXT)); \ + BxW_LOAD_ur_##SIGN(result, (SHIFT), 1); \ + check(result, (RES2) | (EXT)); \ + BxW_LOAD_ur_##SIGN(result, (SHIFT), 2); \ + check(result, (RES3) | (EXT)); \ + BxW_LOAD_ur_##SIGN(result, (SHIFT), 3); \ + check(result, (RES4) | (EXT)); \ +} \ + +TEST_ur(loadbzw2_ur, int, Z, 1, 0x00000000, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_ur(loadbsw2_ur, int, S, 1, 0x0000ff00, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_ur(loadbzw4_ur, long long, Z, 2, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) +TEST_ur(loadbsw4_ur, long long, S, 2, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) + +/* + *************************************************************************= *** + * _ap addressing mode (addr =3D base) + */ +#define BxW_LOAD_ap(SZ, RES, PTR, ADDR) \ + __asm__( \ + "%0 =3D mem" #SZ "(%1 =3D ##" #ADDR ")\n\t" \ + : "=3Dr"(RES), "=3Dr"(PTR)) +#define BxW_LOAD_ap_Z(RES, PTR, ADDR) \ + BxW_LOAD_ap(ubh, RES, PTR, ADDR) +#define BxW_LOAD_ap_S(RES, PTR, ADDR) \ + BxW_LOAD_ap(bh, RES, PTR, ADDR) + +#define TEST_ap(NAME, TYPE, SIGN, SIZE, EXT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + void *ptr; \ + init_buf(); \ + BxW_LOAD_ap_##SIGN(result, ptr, (buf + 0 * (SIZE))); \ + check(result, (RES1) | (EXT)); \ + checkp(ptr, &buf[0 * (SIZE)]); \ + BxW_LOAD_ap_##SIGN(result, ptr, (buf + 1 * (SIZE))); \ + check(result, (RES2) | (EXT)); \ + checkp(ptr, &buf[1 * (SIZE)]); \ + BxW_LOAD_ap_##SIGN(result, ptr, (buf + 2 * (SIZE))); \ + check(result, (RES3) | (EXT)); \ + checkp(ptr, &buf[2 * (SIZE)]); \ + BxW_LOAD_ap_##SIGN(result, ptr, (buf + 3 * (SIZE))); \ + check(result, (RES4) | (EXT)); \ + checkp(ptr, &buf[3 * (SIZE)]); \ +} + +TEST_ap(loadbzw2_ap, int, Z, 2, 0x00000000, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_ap(loadbsw2_ap, int, S, 2, 0x0000ff00, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_ap(loadbzw4_ap, long long, Z, 4, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) +TEST_ap(loadbsw4_ap, long long, S, 4, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) + +/* + *************************************************************************= *** + * _rp addressing mode (addr ++ modifer-reg) + */ +#define BxW_LOAD_pr(SZ, RES, PTR, INC) \ + __asm__( \ + "m0 =3D %2\n\t" \ + "%0 =3D mem" #SZ "(%1++m0)\n\t" \ + : "=3Dr"(RES), "+r"(PTR) \ + : "r"(INC) \ + : "m0") +#define BxW_LOAD_pr_Z(RES, PTR, INC) \ + BxW_LOAD_pr(ubh, RES, PTR, INC) +#define BxW_LOAD_pr_S(RES, PTR, INC) \ + BxW_LOAD_pr(bh, RES, PTR, INC) + +#define TEST_pr(NAME, TYPE, SIGN, SIZE, EXT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + void *ptr =3D buf; \ + init_buf(); \ + BxW_LOAD_pr_##SIGN(result, ptr, (SIZE)); \ + check(result, (RES1) | (EXT)); \ + checkp(ptr, &buf[1 * (SIZE)]); \ + BxW_LOAD_pr_##SIGN(result, ptr, (SIZE)); \ + check(result, (RES2) | (EXT)); \ + checkp(ptr, &buf[2 * (SIZE)]); \ + BxW_LOAD_pr_##SIGN(result, ptr, (SIZE)); \ + check(result, (RES3) | (EXT)); \ + checkp(ptr, &buf[3 * (SIZE)]); \ + BxW_LOAD_pr_##SIGN(result, ptr, (SIZE)); \ + check(result, (RES4) | (EXT)); \ + checkp(ptr, &buf[4 * (SIZE)]); \ +} + +TEST_pr(loadbzw2_pr, int, Z, 2, 0x00000000, + 0x00020081, 0x0040083, 0x00060085, 0x00080087) +TEST_pr(loadbsw2_pr, int, S, 2, 0x0000ff00, + 0x00020081, 0x0040083, 0x00060085, 0x00080087) +TEST_pr(loadbzw4_pr, long long, Z, 4, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) +TEST_pr(loadbsw4_pr, long long, S, 4, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) + +/* + *************************************************************************= *** + * _pbr addressing mode (addr ++ modifer-reg:brev) + */ +#define BxW_LOAD_pbr(SZ, RES, PTR) \ + __asm__( \ + "r4 =3D #(1 << (16 - 3))\n\t" \ + "m0 =3D r4\n\t" \ + "%0 =3D mem" #SZ "(%1++m0:brev)\n\t" \ + : "=3Dr"(RES), "+r"(PTR) \ + : \ + : "r4", "m0") +#define BxW_LOAD_pbr_Z(RES, PTR) \ + BxW_LOAD_pbr(ubh, RES, PTR) +#define BxW_LOAD_pbr_S(RES, PTR) \ + BxW_LOAD_pbr(bh, RES, PTR) + +#define TEST_pbr(NAME, TYPE, SIGN, EXT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + void *ptr =3D buf; \ + init_buf(); \ + BxW_LOAD_pbr_##SIGN(result, ptr); \ + check(result, (RES1) | (EXT)); \ + BxW_LOAD_pbr_##SIGN(result, ptr); \ + check(result, (RES2) | (EXT)); \ + BxW_LOAD_pbr_##SIGN(result, ptr); \ + check(result, (RES3) | (EXT)); \ + BxW_LOAD_pbr_##SIGN(result, ptr); \ + check(result, (RES4) | (EXT)); \ +} + +TEST_pbr(loadbzw2_pbr, int, Z, 0x00000000, + 0x00020081, 0x00060085, 0x00040083, 0x00080087) +TEST_pbr(loadbsw2_pbr, int, S, 0x0000ff00, + 0x00020081, 0x00060085, 0x00040083, 0x00080087) +TEST_pbr(loadbzw4_pbr, long long, Z, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x0006008500040083LL, 0x000a008900080087LL) +TEST_pbr(loadbsw4_pbr, long long, S, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x0006008500040083LL, 0x000a008900080087LL) + +/* + *************************************************************************= *** + * _pi addressing mode (addr ++ inc) + */ +#define BxW_LOAD_pi(SZ, RES, PTR, INC) \ + __asm__( \ + "%0 =3D mem" #SZ "(%1++#" #INC ")\n\t" \ + : "=3Dr"(RES), "+r"(PTR)) +#define BxW_LOAD_pi_Z(RES, PTR, INC) \ + BxW_LOAD_pi(ubh, RES, PTR, INC) +#define BxW_LOAD_pi_S(RES, PTR, INC) \ + BxW_LOAD_pi(bh, RES, PTR, INC) + +#define TEST_pi(NAME, TYPE, SIGN, INC, EXT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + void *ptr =3D buf; \ + init_buf(); \ + BxW_LOAD_pi_##SIGN(result, ptr, (INC)); \ + check(result, (RES1) | (EXT)); \ + checkp(ptr, &buf[1 * (INC)]); \ + BxW_LOAD_pi_##SIGN(result, ptr, (INC)); \ + check(result, (RES2) | (EXT)); \ + checkp(ptr, &buf[2 * (INC)]); \ + BxW_LOAD_pi_##SIGN(result, ptr, (INC)); \ + check(result, (RES3) | (EXT)); \ + checkp(ptr, &buf[3 * (INC)]); \ + BxW_LOAD_pi_##SIGN(result, ptr, (INC)); \ + check(result, (RES4) | (EXT)); \ + checkp(ptr, &buf[4 * (INC)]); \ +} + +TEST_pi(loadbzw2_pi, int, Z, 2, 0x00000000, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_pi(loadbsw2_pi, int, S, 2, 0x0000ff00, + 0x00020081, 0x00040083, 0x00060085, 0x00080087) +TEST_pi(loadbzw4_pi, long long, Z, 4, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) +TEST_pi(loadbsw4_pi, long long, S, 4, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x000c008b000a0089LL, 0x0010008f000e008dLL) + +/* + *************************************************************************= *** + * _pci addressing mode (addr ++ inc:circ) + */ +#define BxW_LOAD_pci(SZ, RES, PTR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %3\n\t" \ + "m0 =3D r4\n\t" \ + "cs0 =3D %2\n\t" \ + "%0 =3D mem" #SZ "(%1++#" #INC ":circ(m0))\n\t" \ + : "=3Dr"(RES), "+r"(PTR) \ + : "r"(START), "r"(LEN) \ + : "r4", "m0", "cs0") +#define BxW_LOAD_pci_Z(RES, PTR, START, LEN, INC) \ + BxW_LOAD_pci(ubh, RES, PTR, START, LEN, INC) +#define BxW_LOAD_pci_S(RES, PTR, START, LEN, INC) \ + BxW_LOAD_pci(bh, RES, PTR, START, LEN, INC) + +#define TEST_pci(NAME, TYPE, SIGN, LEN, INC, EXT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + void *ptr =3D buf; \ + init_buf(); \ + BxW_LOAD_pci_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES1) | (EXT)); \ + checkp(ptr, &buf[(1 * (INC)) % (LEN)]); \ + BxW_LOAD_pci_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES2) | (EXT)); \ + checkp(ptr, &buf[(2 * (INC)) % (LEN)]); \ + BxW_LOAD_pci_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES3) | (EXT)); \ + checkp(ptr, &buf[(3 * (INC)) % (LEN)]); \ + BxW_LOAD_pci_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES4) | (EXT)); \ + checkp(ptr, &buf[(4 * (INC)) % (LEN)]); \ +} + +TEST_pci(loadbzw2_pci, int, Z, 6, 2, 0x00000000, + 0x00020081, 0x00040083, 0x00060085, 0x00020081) +TEST_pci(loadbsw2_pci, int, S, 6, 2, 0x0000ff00, + 0x00020081, 0x00040083, 0x00060085, 0x00020081) +TEST_pci(loadbzw4_pci, long long, Z, 8, 4, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x0004008300020081LL, 0x0008008700060085LL) +TEST_pci(loadbsw4_pci, long long, S, 8, 4, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x0004008300020081LL, 0x0008008700060085LL) + +/* + *************************************************************************= *** + * _pcr addressing mode (addr ++ I:circ(modifier-reg)) + */ +#define BxW_LOAD_pcr(SZ, RES, PTR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %2\n\t" \ + "m1 =3D r4\n\t" \ + "cs1 =3D %3\n\t" \ + "%0 =3D mem" #SZ "(%1++I:circ(m1))\n\t" \ + : "=3Dr"(RES), "+r"(PTR) \ + : "r"((((INC) & 0x7f) << 17) | ((LEN) & 0x1ffff)), \ + "r"(START) \ + : "r4", "m1", "cs1") +#define BxW_LOAD_pcr_Z(RES, PTR, START, LEN, INC) \ + BxW_LOAD_pcr(ubh, RES, PTR, START, LEN, INC) +#define BxW_LOAD_pcr_S(RES, PTR, START, LEN, INC) \ + BxW_LOAD_pcr(bh, RES, PTR, START, LEN, INC) + +#define TEST_pcr(NAME, TYPE, SIGN, SIZE, LEN, INC, \ + EXT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + TYPE result; \ + void *ptr =3D buf; \ + init_buf(); \ + BxW_LOAD_pcr_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES1) | (EXT)); \ + checkp(ptr, &buf[(1 * (INC) * (SIZE)) % (LEN)]); \ + BxW_LOAD_pcr_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES2) | (EXT)); \ + checkp(ptr, &buf[(2 * (INC) * (SIZE)) % (LEN)]); \ + BxW_LOAD_pcr_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES3) | (EXT)); \ + checkp(ptr, &buf[(3 * (INC) * (SIZE)) % (LEN)]); \ + BxW_LOAD_pcr_##SIGN(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES4) | (EXT)); \ + checkp(ptr, &buf[(4 * (INC) * (SIZE)) % (LEN)]); \ +} + +TEST_pcr(loadbzw2_pcr, int, Z, 2, 8, 2, 0x00000000, + 0x00020081, 0x00060085, 0x00020081, 0x00060085) +TEST_pcr(loadbsw2_pcr, int, S, 2, 8, 2, 0x0000ff00, + 0x00020081, 0x00060085, 0x00020081, 0x00060085) +TEST_pcr(loadbzw4_pcr, long long, Z, 4, 8, 1, 0x0000000000000000LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x0004008300020081LL, 0x0008008700060085LL) +TEST_pcr(loadbsw4_pcr, long long, S, 4, 8, 1, 0x0000ff000000ff00LL, + 0x0004008300020081LL, 0x0008008700060085LL, + 0x0004008300020081LL, 0x0008008700060085LL) + +int main() +{ + test_loadbzw2_io(); + test_loadbsw2_io(); + test_loadbzw4_io(); + test_loadbsw4_io(); + + test_loadbzw2_ur(); + test_loadbsw2_ur(); + test_loadbzw4_ur(); + test_loadbsw4_ur(); + + test_loadbzw2_ap(); + test_loadbsw2_ap(); + test_loadbzw4_ap(); + test_loadbsw4_ap(); + + test_loadbzw2_pr(); + test_loadbsw2_pr(); + test_loadbzw4_pr(); + test_loadbsw4_pr(); + + test_loadbzw2_pbr(); + test_loadbsw2_pbr(); + test_loadbzw4_pbr(); + test_loadbsw4_pbr(); + + test_loadbzw2_pi(); + test_loadbsw2_pi(); + test_loadbzw4_pi(); + test_loadbsw4_pi(); + + test_loadbzw2_pci(); + test_loadbsw2_pci(); + test_loadbzw4_pci(); + test_loadbsw4_pci(); + + test_loadbzw2_pcr(); + test_loadbsw2_pcr(); + test_loadbzw4_pcr(); + test_loadbsw4_pcr(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616641687; cv=none; d=zohomail.com; s=zohoarc; b=aSPr+LYUdijsyg4d2UkwibONuHeiWg7lsxP0+kYNmNfxXkNOG4z5VSCQkVjDgGZhOr7XFzVNe7MKF6Cp1t8nlheLxiTI5VwcCCPQv4IJJh7CPiE9Z7TMp2kEYSgNjSZxec0sAIp5TbMp5CWn3E8kfNkFvUuDyu4a8TG3IOrrJOA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616641687; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=G+mz8UQf41sUEEpu3Bzg2q7B8uxbRx8/aRlqsCBoDzw=; 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X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 14/15] Hexagon (target/hexagon) load into shifted register instructions Date: Wed, 24 Mar 2021 21:50:09 -0500 Message-Id: <1616640610-17319-15-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The following instructions are added L2_loadalignb_io Ryy32 =3D memb_fifo(Rs32+#s11:1) L2_loadalignh_io Ryy32 =3D memh_fifo(Rs32+#s11:1) L4_loadalignb_ur Ryy32 =3D memb_fifo(Rt32<<#u2+#U6) L4_loadalignh_ur Ryy32 =3D memh_fifo(Rt32<<#u2+#U6) L4_loadalignb_ap Ryy32 =3D memb_fifo(Re32=3D#U6) L4_loadalignh_ap Ryy32 =3D memh_fifo(Re32=3D#U6) L2_loadalignb_pr Ryy32 =3D memb_fifo(Rx32++Mu2) L2_loadalignh_pr Ryy32 =3D memh_fifo(Rx32++Mu2) L2_loadalignb_pbr Ryy32 =3D memb_fifo(Rx32++Mu2:brev) L2_loadalignh_pbr Ryy32 =3D memh_fifo(Rx32++Mu2:brev) L2_loadalignb_pi Ryy32 =3D memb_fifo(Rx32++#s4:1) L2_loadalignh_pi Ryy32 =3D memh_fifo(Rx32++#s4:1) L2_loadalignb_pci Ryy32 =3D memb_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignh_pci Ryy32 =3D memh_fifo(Rx32++#s4:1:circ(Mu2)) L2_loadalignb_pcr Ryy32 =3D memb_fifo(Rx32++I:circ(Mu2)) L2_loadalignh_pcr Ryy32 =3D memh_fifo(Rx32++I:circ(Mu2)) Test cases in tests/tcg/hexagon/load_align.c Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 78 +++++++ target/hexagon/imported/encode_pp.def | 3 + target/hexagon/imported/ldst.idef | 19 ++ tests/tcg/hexagon/Makefile.target | 1 + tests/tcg/hexagon/load_align.c | 415 ++++++++++++++++++++++++++++++= ++++ 5 files changed, 516 insertions(+) create mode 100644 tests/tcg/hexagon/load_align.c diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 55ba5f2..79ec060 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -285,6 +285,84 @@ fGEN_TCG_loadbXw4(GET_EA_pi, fGETBYTE) =20 /* + * These instructions load a half word, shift the destination right by 16 = bits + * and place the loaded value in the high half word of the destination pai= r. + * The GET_EA macro determines the addressing mode. + */ +#define fGEN_TCG_loadalignh(GET_EA) \ + do { \ + TCGv ireg =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + TCGv tmpV =3D tcg_temp_new(); \ + TCGv_i64 tmp_i64 =3D tcg_temp_new_i64(); \ + tcg_gen_concat_i32_i64(RyyV, hex_gpr[RyyN], hex_gpr[RyyN + 1]); \ + GET_EA; \ + fLOAD(1, 2, u, EA, tmpV); \ + tcg_gen_extu_i32_i64(tmp_i64, tmpV); \ + tcg_gen_shli_i64(tmp_i64, tmp_i64, 48); \ + tcg_gen_shri_i64(RyyV, RyyV, 16); \ + tcg_gen_or_i64(RyyV, RyyV, tmp_i64); \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free_i64(tmp_i64); \ + } while (0) + +#define fGEN_TCG_L4_loadalignh_ur(SHORTCODE) \ + fGEN_TCG_loadalignh(fEA_IRs(UiV, RtV, uiV)) +#define fGEN_TCG_L2_loadalignh_io(SHORTCODE) \ + fGEN_TCG_loadalignh(fEA_RI(RsV, siV)) +#define fGEN_TCG_L2_loadalignh_pci(SHORTCODE) \ + fGEN_TCG_loadalignh(GET_EA_pci) +#define fGEN_TCG_L2_loadalignh_pcr(SHORTCODE) \ + fGEN_TCG_loadalignh(GET_EA_pcr(1)) +#define fGEN_TCG_L4_loadalignh_ap(SHORTCODE) \ + fGEN_TCG_loadalignh(GET_EA_ap) +#define fGEN_TCG_L2_loadalignh_pr(SHORTCODE) \ + fGEN_TCG_loadalignh(GET_EA_pr) +#define fGEN_TCG_L2_loadalignh_pbr(SHORTCODE) \ + fGEN_TCG_loadalignh(GET_EA_pbr) +#define fGEN_TCG_L2_loadalignh_pi(SHORTCODE) \ + fGEN_TCG_loadalignh(GET_EA_pi) + +/* Same as above, but loads a byte instead of half word */ +#define fGEN_TCG_loadalignb(GET_EA) \ + do { \ + TCGv ireg =3D tcg_temp_new(); \ + TCGv tmp =3D tcg_temp_new(); \ + TCGv tmpV =3D tcg_temp_new(); \ + TCGv_i64 tmp_i64 =3D tcg_temp_new_i64(); \ + tcg_gen_concat_i32_i64(RyyV, hex_gpr[RyyN], hex_gpr[RyyN + 1]); \ + GET_EA; \ + fLOAD(1, 1, u, EA, tmpV); \ + tcg_gen_extu_i32_i64(tmp_i64, tmpV); \ + tcg_gen_shli_i64(tmp_i64, tmp_i64, 56); \ + tcg_gen_shri_i64(RyyV, RyyV, 8); \ + tcg_gen_or_i64(RyyV, RyyV, tmp_i64); \ + tcg_temp_free(ireg); \ + tcg_temp_free(tmp); \ + tcg_temp_free(tmpV); \ + tcg_temp_free_i64(tmp_i64); \ + } while (0) + +#define fGEN_TCG_L2_loadalignb_io(SHORTCODE) \ + fGEN_TCG_loadalignb(fEA_RI(RsV, siV)) +#define fGEN_TCG_L4_loadalignb_ur(SHORTCODE) \ + fGEN_TCG_loadalignb(fEA_IRs(UiV, RtV, uiV)) +#define fGEN_TCG_L2_loadalignb_pci(SHORTCODE) \ + fGEN_TCG_loadalignb(GET_EA_pci) +#define fGEN_TCG_L2_loadalignb_pcr(SHORTCODE) \ + fGEN_TCG_loadalignb(GET_EA_pcr(0)) +#define fGEN_TCG_L4_loadalignb_ap(SHORTCODE) \ + fGEN_TCG_loadalignb(GET_EA_ap) +#define fGEN_TCG_L2_loadalignb_pr(SHORTCODE) \ + fGEN_TCG_loadalignb(GET_EA_pr) +#define fGEN_TCG_L2_loadalignb_pbr(SHORTCODE) \ + fGEN_TCG_loadalignb(GET_EA_pbr) +#define fGEN_TCG_L2_loadalignb_pi(SHORTCODE) \ + fGEN_TCG_loadalignb(GET_EA_pi) + +/* * Predicated loads * Here is a primer to understand the tag names * diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index e3582eb..dc4eba4 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -348,6 +348,9 @@ STD_LD_ENC(bzw2,"0 011") STD_LD_ENC(bsw4,"0 111") STD_LD_ENC(bsw2,"0 001") =20 +STD_LDX_ENC(alignh,"0 010") +STD_LDX_ENC(alignb,"0 100") + STD_LD_ENC(rb, "1 000") STD_LD_ENC(rub, "1 001") STD_LD_ENC(rh, "1 010") diff --git a/target/hexagon/imported/ldst.idef b/target/hexagon/imported/ld= st.idef index 95c0470..359d3b7 100644 --- a/target/hexagon/imported/ldst.idef +++ b/target/hexagon/imported/ldst.idef @@ -80,6 +80,25 @@ ATTRIBS(A_LOAD),"2", =20 =20 =20 +STD_LD_AMODES(loadalignh, "Ryy32=3Dmemh_fifo", "Load Half-word into shifte= d vector", +ATTRIBS(A_LOAD),"1", +{ + fHIDE(size8u_t tmpV;) + fLOAD(1,2,u,EA,tmpV); + RyyV =3D (((size8u_t)RyyV)>>16)|(tmpV<<48); +},1) + + +STD_LD_AMODES(loadalignb, "Ryy32=3Dmemb_fifo", "Load byte into shifted vec= tor", +ATTRIBS(A_LOAD),"0", +{ + fHIDE(size8u_t tmpV;) + fLOAD(1,1,u,EA,tmpV); + RyyV =3D (((size8u_t)RyyV)>>8)|(tmpV<<56); +},0) + + + =20 /* The set of addressing modes standard to all Store instructions */ #define STD_ST_AMODES(TAG,DEST,OPER,DESCR,ATTRIB,SHFT,SEMANTICS,SCALE)\ diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index 5411eee..124b729 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -44,6 +44,7 @@ HEX_TESTS +=3D mem_noshuf HEX_TESTS +=3D circ HEX_TESTS +=3D brev HEX_TESTS +=3D load_unpack +HEX_TESTS +=3D load_align HEX_TESTS +=3D atomics HEX_TESTS +=3D fpstuff =20 diff --git a/tests/tcg/hexagon/load_align.c b/tests/tcg/hexagon/load_align.c new file mode 100644 index 0000000..12fc9cb --- /dev/null +++ b/tests/tcg/hexagon/load_align.c @@ -0,0 +1,415 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * Test load align instructions + * + * Example + * r1:0 =3D memh_fifo(r1+#0) + * loads a half word from memory, shifts the destination register + * right by one half word and inserts the loaded value into the high + * half word of the destination. + * + * There are 8 addressing modes and byte and half word variants, for a + * total of 16 instructions to test + */ + +#include +#include + +int err; + +char buf[16] __attribute__((aligned(1 << 16))); + +void init_buf(void) +{ + int i; + for (i =3D 0; i < 16; i++) { + buf[i] =3D i + 1; + } +} + +void __check(int line, long long result, long long expect) +{ + if (result !=3D expect) { + printf("ERROR at line %d: 0x%016llx !=3D 0x%016llx\n", + line, result, expect); + err++; + } +} + +#define check(RES, EXP) __check(__LINE__, RES, EXP) + +void __checkp(int line, void *p, void *expect) +{ + if (p !=3D expect) { + printf("ERROR at line %d: 0x%p !=3D 0x%p\n", line, p, expect); + err++; + } +} + +#define checkp(RES, EXP) __checkp(__LINE__, RES, EXP) + +/* + *************************************************************************= *** + * _io addressing mode (addr + offset) + */ +#define LOAD_io(SZ, RES, ADDR, OFF) \ + __asm__( \ + "%0 =3D mem" #SZ "_fifo(%1+#" #OFF ")\n\t" \ + : "+r"(RES) \ + : "r"(ADDR)) +#define LOAD_io_b(RES, ADDR, OFF) \ + LOAD_io(b, RES, ADDR, OFF) +#define LOAD_io_h(RES, ADDR, OFF) \ + LOAD_io(h, RES, ADDR, OFF) + +#define TEST_io(NAME, SZ, SIZE, EXP1, EXP2, EXP3, EXP4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + LOAD_io_##SZ(result, buf, 0 * (SIZE)); \ + check(result, (EXP1)); \ + LOAD_io_##SZ(result, buf, 1 * (SIZE)); \ + check(result, (EXP2)); \ + LOAD_io_##SZ(result, buf, 2 * (SIZE)); \ + check(result, (EXP3)); \ + LOAD_io_##SZ(result, buf, 3 * (SIZE)); \ + check(result, (EXP4)); \ +} + +TEST_io(loadalignb_io, b, 1, + 0x01ffffffffffffffLL, 0x0201ffffffffffffLL, + 0x030201ffffffffffLL, 0x04030201ffffffffLL) +TEST_io(loadalignh_io, h, 2, + 0x0201ffffffffffffLL, 0x04030201ffffffffLL, + 0x060504030201ffffLL, 0x0807060504030201LL) + +/* + *************************************************************************= *** + * _ur addressing mode (index << offset + base) + */ +#define LOAD_ur(SZ, RES, SHIFT, IDX) \ + __asm__( \ + "%0 =3D mem" #SZ "_fifo(%1<<#" #SHIFT " + ##buf)\n\t" \ + : "+r"(RES) \ + : "r"(IDX)) +#define LOAD_ur_b(RES, SHIFT, IDX) \ + LOAD_ur(b, RES, SHIFT, IDX) +#define LOAD_ur_h(RES, SHIFT, IDX) \ + LOAD_ur(h, RES, SHIFT, IDX) + +#define TEST_ur(NAME, SZ, SHIFT, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + LOAD_ur_##SZ(result, (SHIFT), 0); \ + check(result, (RES1)); \ + LOAD_ur_##SZ(result, (SHIFT), 1); \ + check(result, (RES2)); \ + LOAD_ur_##SZ(result, (SHIFT), 2); \ + check(result, (RES3)); \ + LOAD_ur_##SZ(result, (SHIFT), 3); \ + check(result, (RES4)); \ +} + +TEST_ur(loadalignb_ur, b, 1, + 0x01ffffffffffffffLL, 0x0301ffffffffffffLL, + 0x050301ffffffffffLL, 0x07050301ffffffffLL) +TEST_ur(loadalignh_ur, h, 1, + 0x0201ffffffffffffLL, 0x04030201ffffffffLL, + 0x060504030201ffffLL, 0x0807060504030201LL) + +/* + *************************************************************************= *** + * _ap addressing mode (addr =3D base) + */ +#define LOAD_ap(SZ, RES, PTR, ADDR) \ + __asm__( \ + "%0 =3D mem" #SZ "_fifo(%1 =3D ##" #ADDR ")\n\t" \ + : "+r"(RES), "=3Dr"(PTR)) +#define LOAD_ap_b(RES, PTR, ADDR) \ + LOAD_ap(b, RES, PTR, ADDR) +#define LOAD_ap_h(RES, PTR, ADDR) \ + LOAD_ap(h, RES, PTR, ADDR) + +#define TEST_ap(NAME, SZ, SIZE, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + void *ptr; \ + LOAD_ap_##SZ(result, ptr, (buf + 0 * (SIZE))); \ + check(result, (RES1)); \ + checkp(ptr, &buf[0 * (SIZE)]); \ + LOAD_ap_##SZ(result, ptr, (buf + 1 * (SIZE))); \ + check(result, (RES2)); \ + checkp(ptr, &buf[1 * (SIZE)]); \ + LOAD_ap_##SZ(result, ptr, (buf + 2 * (SIZE))); \ + check(result, (RES3)); \ + checkp(ptr, &buf[2 * (SIZE)]); \ + LOAD_ap_##SZ(result, ptr, (buf + 3 * (SIZE))); \ + check(result, (RES4)); \ + checkp(ptr, &buf[3 * (SIZE)]); \ +} + +TEST_ap(loadalignb_ap, b, 1, + 0x01ffffffffffffffLL, 0x0201ffffffffffffLL, + 0x030201ffffffffffLL, 0x04030201ffffffffLL) +TEST_ap(loadalignh_ap, h, 2, + 0x0201ffffffffffffLL, 0x04030201ffffffffLL, + 0x060504030201ffffLL, 0x0807060504030201LL) + +/* + *************************************************************************= *** + * _rp addressing mode (addr ++ modifer-reg) + */ +#define LOAD_pr(SZ, RES, PTR, INC) \ + __asm__( \ + "m0 =3D %2\n\t" \ + "%0 =3D mem" #SZ "_fifo(%1++m0)\n\t" \ + : "+r"(RES), "+r"(PTR) \ + : "r"(INC) \ + : "m0") +#define LOAD_pr_b(RES, PTR, INC) \ + LOAD_pr(b, RES, PTR, INC) +#define LOAD_pr_h(RES, PTR, INC) \ + LOAD_pr(h, RES, PTR, INC) + +#define TEST_pr(NAME, SZ, SIZE, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + void *ptr =3D buf; \ + LOAD_pr_##SZ(result, ptr, (SIZE)); \ + check(result, (RES1)); \ + checkp(ptr, &buf[1 * (SIZE)]); \ + LOAD_pr_##SZ(result, ptr, (SIZE)); \ + check(result, (RES2)); \ + checkp(ptr, &buf[2 * (SIZE)]); \ + LOAD_pr_##SZ(result, ptr, (SIZE)); \ + check(result, (RES3)); \ + checkp(ptr, &buf[3 * (SIZE)]); \ + LOAD_pr_##SZ(result, ptr, (SIZE)); \ + check(result, (RES4)); \ + checkp(ptr, &buf[4 * (SIZE)]); \ +} + +TEST_pr(loadalignb_pr, b, 1, + 0x01ffffffffffffffLL, 0x0201ffffffffffffLL, + 0x030201ffffffffffLL, 0x04030201ffffffffLL) +TEST_pr(loadalignh_pr, h, 2, + 0x0201ffffffffffffLL, 0x04030201ffffffffLL, + 0x060504030201ffffLL, 0x0807060504030201LL) + +/* + *************************************************************************= *** + * _pbr addressing mode (addr ++ modifer-reg:brev) + */ +#define LOAD_pbr(SZ, RES, PTR) \ + __asm__( \ + "r4 =3D #(1 << (16 - 3))\n\t" \ + "m0 =3D r4\n\t" \ + "%0 =3D mem" #SZ "_fifo(%1++m0:brev)\n\t" \ + : "+r"(RES), "+r"(PTR) \ + : \ + : "r4", "m0") +#define LOAD_pbr_b(RES, PTR) \ + LOAD_pbr(b, RES, PTR) +#define LOAD_pbr_h(RES, PTR) \ + LOAD_pbr(h, RES, PTR) + +#define TEST_pbr(NAME, SZ, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + void *ptr =3D buf; \ + LOAD_pbr_##SZ(result, ptr); \ + check(result, (RES1)); \ + LOAD_pbr_##SZ(result, ptr); \ + check(result, (RES2)); \ + LOAD_pbr_##SZ(result, ptr); \ + check(result, (RES3)); \ + LOAD_pbr_##SZ(result, ptr); \ + check(result, (RES4)); \ +} + +TEST_pbr(loadalignb_pbr, b, + 0x01ffffffffffffffLL, 0x0501ffffffffffffLL, + 0x030501ffffffffffLL, 0x07030501ffffffffLL) +TEST_pbr(loadalignh_pbr, h, + 0x0201ffffffffffffLL, 0x06050201ffffffffLL, + 0x040306050201ffffLL, 0x0807040306050201LL) + +/* + *************************************************************************= *** + * _pi addressing mode (addr ++ inc) + */ +#define LOAD_pi(SZ, RES, PTR, INC) \ + __asm__( \ + "%0 =3D mem" #SZ "_fifo(%1++#" #INC ")\n\t" \ + : "+r"(RES), "+r"(PTR)) +#define LOAD_pi_b(RES, PTR, INC) \ + LOAD_pi(b, RES, PTR, INC) +#define LOAD_pi_h(RES, PTR, INC) \ + LOAD_pi(h, RES, PTR, INC) + +#define TEST_pi(NAME, SZ, INC, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + void *ptr =3D buf; \ + LOAD_pi_##SZ(result, ptr, (INC)); \ + check(result, (RES1)); \ + checkp(ptr, &buf[1 * (INC)]); \ + LOAD_pi_##SZ(result, ptr, (INC)); \ + check(result, (RES2)); \ + checkp(ptr, &buf[2 * (INC)]); \ + LOAD_pi_##SZ(result, ptr, (INC)); \ + check(result, (RES3)); \ + checkp(ptr, &buf[3 * (INC)]); \ + LOAD_pi_##SZ(result, ptr, (INC)); \ + check(result, (RES4)); \ + checkp(ptr, &buf[4 * (INC)]); \ +} + +TEST_pi(loadalignb_pi, b, 1, + 0x01ffffffffffffffLL, 0x0201ffffffffffffLL, + 0x030201ffffffffffLL, 0x04030201ffffffffLL) +TEST_pi(loadalignh_pi, h, 2, + 0x0201ffffffffffffLL, 0x04030201ffffffffLL, + 0x060504030201ffffLL, 0x0807060504030201LL) + +/* + *************************************************************************= *** + * _pci addressing mode (addr ++ inc:circ) + */ +#define LOAD_pci(SZ, RES, PTR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %3\n\t" \ + "m0 =3D r4\n\t" \ + "cs0 =3D %2\n\t" \ + "%0 =3D mem" #SZ "_fifo(%1++#" #INC ":circ(m0))\n\t" \ + : "+r"(RES), "+r"(PTR) \ + : "r"(START), "r"(LEN) \ + : "r4", "m0", "cs0") +#define LOAD_pci_b(RES, PTR, START, LEN, INC) \ + LOAD_pci(b, RES, PTR, START, LEN, INC) +#define LOAD_pci_h(RES, PTR, START, LEN, INC) \ + LOAD_pci(h, RES, PTR, START, LEN, INC) + +#define TEST_pci(NAME, SZ, LEN, INC, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + void *ptr =3D buf; \ + LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES1)); \ + checkp(ptr, &buf[(1 * (INC)) % (LEN)]); \ + LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES2)); \ + checkp(ptr, &buf[(2 * (INC)) % (LEN)]); \ + LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES3)); \ + checkp(ptr, &buf[(3 * (INC)) % (LEN)]); \ + LOAD_pci_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES4)); \ + checkp(ptr, &buf[(4 * (INC)) % (LEN)]); \ +} + +TEST_pci(loadalignb_pci, b, 2, 1, + 0x01ffffffffffffffLL, 0x0201ffffffffffffLL, + 0x010201ffffffffffLL, 0x02010201ffffffffLL) +TEST_pci(loadalignh_pci, h, 4, 2, + 0x0201ffffffffffffLL, 0x04030201ffffffffLL, + 0x020104030201ffffLL, 0x0403020104030201LL) + +/* + *************************************************************************= *** + * _pcr addressing mode (addr ++ I:circ(modifier-reg)) + */ +#define LOAD_pcr(SZ, RES, PTR, START, LEN, INC) \ + __asm__( \ + "r4 =3D %2\n\t" \ + "m1 =3D r4\n\t" \ + "cs1 =3D %3\n\t" \ + "%0 =3D mem" #SZ "_fifo(%1++I:circ(m1))\n\t" \ + : "+r"(RES), "+r"(PTR) \ + : "r"((((INC) & 0x7f) << 17) | ((LEN) & 0x1ffff)), \ + "r"(START) \ + : "r4", "m1", "cs1") +#define LOAD_pcr_b(RES, PTR, START, LEN, INC) \ + LOAD_pcr(b, RES, PTR, START, LEN, INC) +#define LOAD_pcr_h(RES, PTR, START, LEN, INC) \ + LOAD_pcr(h, RES, PTR, START, LEN, INC) + +#define TEST_pcr(NAME, SZ, SIZE, LEN, INC, RES1, RES2, RES3, RES4) \ +void test_##NAME(void) \ +{ \ + long long result =3D ~0LL; \ + void *ptr =3D buf; \ + LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES1)); \ + checkp(ptr, &buf[(1 * (INC) * (SIZE)) % (LEN)]); \ + LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES2)); \ + checkp(ptr, &buf[(2 * (INC) * (SIZE)) % (LEN)]); \ + LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES3)); \ + checkp(ptr, &buf[(3 * (INC) * (SIZE)) % (LEN)]); \ + LOAD_pcr_##SZ(result, ptr, buf, (LEN), (INC)); \ + check(result, (RES4)); \ + checkp(ptr, &buf[(4 * (INC) * (SIZE)) % (LEN)]); \ +} + +TEST_pcr(loadalignb_pcr, b, 1, 2, 1, + 0x01ffffffffffffffLL, 0x0201ffffffffffffLL, + 0x010201ffffffffffLL, 0x02010201ffffffffLL) +TEST_pcr(loadalignh_pcr, h, 2, 4, 1, + 0x0201ffffffffffffLL, 0x04030201ffffffffLL, + 0x020104030201ffffLL, 0x0403020104030201LL) + +int main() +{ + init_buf(); + + test_loadalignb_io(); + test_loadalignh_io(); + + test_loadalignb_ur(); + test_loadalignh_ur(); + + test_loadalignb_ap(); + test_loadalignh_ap(); + + test_loadalignb_pr(); + test_loadalignh_pr(); + + test_loadalignb_pbr(); + test_loadalignh_pbr(); + + test_loadalignb_pi(); + test_loadalignh_pi(); + + test_loadalignb_pci(); + test_loadalignh_pci(); + + test_loadalignb_pcr(); + test_loadalignh_pcr(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} --=20 2.7.4 From nobody Sun May 19 20:29:54 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1616641569; cv=none; d=zohomail.com; s=zohoarc; b=D3Yc7O5MbKrcMuFmcUGwWS5prWGTPylRNYFq8t7tQaacEgz4z12kzq6QTd3R95CVrcuXTbNHjJLDcYpdlNBqpXBj8pMq36n/uljlkGZTjPb0qAbeUzeIZMxtByCt8QQh2zqR64zUQDGqGUi+D3DVLXy2blEyKQVHH0KbGJYphog= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1616641569; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kJpQiNLTFtGwq0jmQb1TXGT3+in24QiVduUMfJap6AU=; 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X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH 15/15] Hexagon (target/hexagon) CABAC decode bin Date: Wed, 24 Mar 2021 21:50:10 -0500 Message-Id: <1616640610-17319-16-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> References: <1616640610-17319-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, philmd@redhat.com, tsimpson@quicinc.com, richard.henderson@linaro.org, bcain@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The following instruction is added S2_cabacdecbin Rdd32=3Ddecbin(Rss32,Rtt32) Test cases added to tests/tcg/hexagon/misc.c Signed-off-by: Taylor Simpson --- target/hexagon/arch.c | 91 +++++++++++++++++++++++++++++++= ++++ target/hexagon/arch.h | 4 ++ target/hexagon/imported/encode_pp.def | 1 + target/hexagon/imported/macros.def | 15 ++++++ target/hexagon/imported/shift.idef | 47 ++++++++++++++++++ target/hexagon/macros.h | 4 ++ tests/tcg/hexagon/misc.c | 28 +++++++++++ 7 files changed, 190 insertions(+) diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c index d756dfa..35fdcba 100644 --- a/target/hexagon/arch.c +++ b/target/hexagon/arch.c @@ -27,6 +27,97 @@ #define SF_MANTBITS 23 #define float32_nan make_float32(0xffffffff) =20 +/* + * These three tables are used by the cabacdecbin instruction + */ +const uint8_t rLPS_table_64x4[64][4] =3D { + {128, 176, 208, 240}, + {128, 167, 197, 227}, + {128, 158, 187, 216}, + {123, 150, 178, 205}, + {116, 142, 169, 195}, + {111, 135, 160, 185}, + {105, 128, 152, 175}, + {100, 122, 144, 166}, + {95, 116, 137, 158}, + {90, 110, 130, 150}, + {85, 104, 123, 142}, + {81, 99, 117, 135}, + {77, 94, 111, 128}, + {73, 89, 105, 122}, + {69, 85, 100, 116}, + {66, 80, 95, 110}, + {62, 76, 90, 104}, + {59, 72, 86, 99}, + {56, 69, 81, 94}, + {53, 65, 77, 89}, + {51, 62, 73, 85}, + {48, 59, 69, 80}, + {46, 56, 66, 76}, + {43, 53, 63, 72}, + {41, 50, 59, 69}, + {39, 48, 56, 65}, + {37, 45, 54, 62}, + {35, 43, 51, 59}, + {33, 41, 48, 56}, + {32, 39, 46, 53}, + {30, 37, 43, 50}, + {29, 35, 41, 48}, + {27, 33, 39, 45}, + {26, 31, 37, 43}, + {24, 30, 35, 41}, + {23, 28, 33, 39}, + {22, 27, 32, 37}, + {21, 26, 30, 35}, + {20, 24, 29, 33}, + {19, 23, 27, 31}, + {18, 22, 26, 30}, + {17, 21, 25, 28}, + {16, 20, 23, 27}, + {15, 19, 22, 25}, + {14, 18, 21, 24}, + {14, 17, 20, 23}, + {13, 16, 19, 22}, + {12, 15, 18, 21}, + {12, 14, 17, 20}, + {11, 14, 16, 19}, + {11, 13, 15, 18}, + {10, 12, 15, 17}, + {10, 12, 14, 16}, + {9, 11, 13, 15}, + {9, 11, 12, 14}, + {8, 10, 12, 14}, + {8, 9, 11, 13}, + {7, 9, 11, 12}, + {7, 9, 10, 12}, + {7, 8, 10, 11}, + {6, 8, 9, 11}, + {6, 7, 9, 10}, + {6, 7, 8, 9}, + {2, 2, 2, 2} +}; + +const uint8_t AC_next_state_MPS_64[64] =3D { + 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, + 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, + 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, + 61, 62, 62, 63 +}; + + +const uint8_t AC_next_state_LPS_64[64] =3D { + 0, 0, 1, 2, 2, 4, 4, 5, 6, 7, + 8, 9, 9, 11, 11, 12, 13, 13, 15, 15, + 16, 16, 18, 18, 19, 19, 21, 21, 22, 22, + 23, 24, 24, 25, 26, 26, 27, 27, 28, 29, + 29, 30, 30, 30, 31, 32, 32, 33, 33, 33, + 34, 34, 35, 35, 35, 36, 36, 36, 37, 37, + 37, 38, 38, 63 +}; + #define BITS_MASK_8 0x5555555555555555ULL #define PAIR_MASK_8 0x3333333333333333ULL #define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h index 544288e..f6fdd88 100644 --- a/target/hexagon/arch.h +++ b/target/hexagon/arch.h @@ -20,6 +20,10 @@ =20 #include "qemu/int128.h" =20 +extern const uint8_t rLPS_table_64x4[64][4]; +extern const uint8_t AC_next_state_MPS_64[64]; +extern const uint8_t AC_next_state_LPS_64[64]; + uint64_t interleave(uint32_t odd, uint32_t even); uint64_t deinterleave(uint64_t src); int32_t conv_round(int32_t a, int n); diff --git a/target/hexagon/imported/encode_pp.def b/target/hexagon/importe= d/encode_pp.def index dc4eba4..35ae3d2 100644 --- a/target/hexagon/imported/encode_pp.def +++ b/target/hexagon/imported/encode_pp.def @@ -1767,6 +1767,7 @@ SH_RRR_ENC(S4_vxsubaddh, "0001","01-","-","110= ","ddddd") SH_RRR_ENC(S4_vxaddsubhr, "0001","11-","-","00-","ddddd") SH_RRR_ENC(S4_vxsubaddhr, "0001","11-","-","01-","ddddd") SH_RRR_ENC(S4_extractp_rp, "0001","11-","-","10-","ddddd") +SH_RRR_ENC(S2_cabacdecbin, "0001","11-","-","11-","ddddd") /* implici= t P0 write */ =20 =20 DEF_FIELDROW_DESC32(ICLASS_S3op" 0010 -------- PP------ --------","[#2] Rd= d=3D(Rss,Rtt,Pu)") diff --git a/target/hexagon/imported/macros.def b/target/hexagon/imported/m= acros.def index 56c99b1..32ed3bf 100755 --- a/target/hexagon/imported/macros.def +++ b/target/hexagon/imported/macros.def @@ -92,6 +92,21 @@ DEF_MACRO( /* attribs */ ) =20 + +DEF_MACRO( + fINSERT_RANGE, + { + int offset=3DLOWBIT; + int width=3DHIBIT-LOWBIT+1; + /* clear bits where new bits go */ + INREG &=3D ~(((fCONSTLL(1)<>29)&3]; + rLPS =3D rLPS << 23; /* left aligned */ + + /* calculate rMPS */ + rMPS=3D (range&0xff800000) - rLPS; + + /* most probable region */ + if (offset < rMPS) { + RddV =3D AC_next_state_MPS_64[state]; + fINSERT_RANGE(RddV,8,8,valMPS); + fINSERT_RANGE(RddV,31,23,(rMPS>>23)); + fSETWORD(1,RddV,offset); + fWRITE_P0(valMPS); + + + } + /* least probable region */ + else { + RddV =3D AC_next_state_LPS_64[state]; + fINSERT_RANGE(RddV,8,8,((!state)?(1-valMPS):(valMPS))); + fINSERT_RANGE(RddV,31,23,(rLPS>>23)); + fSETWORD(1,RddV,(offset-rMPS)); + fWRITE_P0((valMPS^1)); + } +}) + + Q6INSN(S2_clb,"Rd32=3Dclb(Rs32)",ATTRIBS(), "Count leading bits", {RdV =3D fMAX(fCL1_4(RsV),fCL1_4(~RsV));}) =20 diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h index e4aec8d..d2597ae 100644 --- a/target/hexagon/macros.h +++ b/target/hexagon/macros.h @@ -226,6 +226,10 @@ static inline void gen_pred_cancel(TCGv pred, int slot= _num) (((HIBIT) - (LOWBIT) + 1) ? \ extract64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1)) : \ 0LL) +#define fINSERT_RANGE(INREG, HIBIT, LOWBIT, INVAL) \ + INREG =3D (((HIBIT) - (LOWBIT) - 1) ? \ + deposit64((INREG), (LOWBIT), ((HIBIT) - (LOWBIT) + 1), (INVAL)) : \ + INREG) =20 #ifdef QEMU_GENERATE #define f8BITSOF(RES, VAL) gen_8bitsof(RES, VAL) diff --git a/tests/tcg/hexagon/misc.c b/tests/tcg/hexagon/misc.c index e5d78b4..17c3919 100644 --- a/tests/tcg/hexagon/misc.c +++ b/tests/tcg/hexagon/misc.c @@ -231,6 +231,14 @@ static void check(int val, int expect) } } =20 +static void check64(long long val, long long expect) +{ + if (val !=3D expect) { + printf("ERROR: 0x%016llx !=3D 0x%016llx\n", val, expect); + err++; + } +} + uint32_t init[10] =3D { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; uint32_t array[10]; =20 @@ -264,6 +272,16 @@ static long long creg_pair(int x, int y) return retval; } =20 +static long long decbin(long long x, long long y, int *pred) +{ + long long retval; + asm ("%0 =3D decbin(%2, %3)\n\t" + "%1 =3D p0\n\t" + : "=3Dr"(retval), "=3Dr"(*pred) + : "r"(x), "r"(y)); + return retval; +} + /* Check that predicates are auto-and'ed in a packet */ static int auto_and(void) { @@ -282,6 +300,8 @@ static int auto_and(void) =20 int main() { + long long res64; + int pred; =20 memcpy(array, init, sizeof(array)); S4_storerhnew_rr(array, 4, 0xffff); @@ -391,6 +411,14 @@ int main() res =3D test_clrtnew(2, 7); check(res, 7); =20 + res64 =3D decbin(0xf0f1f2f3f4f5f6f7LL, 0x7f6f5f4f3f2f1f0fLL, &pred); + check64(res64, 0x357980003700010cLL); + check(pred, 0); + + res64 =3D decbin(0xfLL, 0x1bLL, &pred); + check64(res64, 0x78000100LL); + check(pred, 1); + res =3D auto_and(); check(res, 0); =20 --=20 2.7.4