From nobody Wed Nov 19 00:15:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613921778; cv=none; d=zohomail.com; s=zohoarc; b=i36Hxhu11hxHGQk4dEduLC6tEUGGZHOzpnXhJboIDvbMVlYP8lGgzZXNJvpm0KzUT0J5G9naASVdc0kBGBh+8VQ00ThJas9EOp23tGVBYw5JOuNrUbG7VHKt6qaDPcdINUVnOfymKGWBK+uVZBnHjXn/nO5L2du2Cm6aeSPXvWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613921778; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LxoazvL8m6DChl4MAeYfV1MQGAobS6p7mIHmBXUMWrE=; b=i94/6Pl61lsuv0NmSfozragE7HHfEhlbPW9tZDvxmpSjVFpEVxkHVMWAKw/JgKnu8YQ/FFPMKhccUC8NCZtvj+qFjx55JeslDJD8qZhW81vtNX7elUZsdfw/WkR5jQaR5IRE6VqaaufjVoxtJGJ5xAW/MiSsdJ37mf1GRGAIJOw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613921777882556.742909516354; Sun, 21 Feb 2021 07:36:17 -0800 (PST) Received: from localhost ([::1]:47022 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lDqmO-0007dA-Oz for importer@patchew.org; Sun, 21 Feb 2021 10:36:16 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55996) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lDpJo-0005m9-Cf; Sun, 21 Feb 2021 09:02:40 -0500 Received: from atcsqr.andestech.com ([60.248.187.195]:10477) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lDpJl-00057Z-4U; Sun, 21 Feb 2021 09:02:40 -0500 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 11LDumfr062688; Sun, 21 Feb 2021 21:56:48 +0800 (GMT-8) (envelope-from cwshu@andestech.com) Received: from ubuntu1604.andestech.com (10.0.12.177) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.487.0; Sun, 21 Feb 2021 22:02:17 +0800 From: Jim Shu To: , Subject: [PATCH 1/3] target/riscv: propagate PMP permission to TLB page Date: Sun, 21 Feb 2021 22:01:20 +0800 Message-ID: <1613916082-19528-2-git-send-email-cwshu@andestech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613916082-19528-1-git-send-email-cwshu@andestech.com> References: <1613916082-19528-1-git-send-email-cwshu@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.12.177] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 11LDumfr062688 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=cwshu@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 21 Feb 2021 10:29:58 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , Jim Shu , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, PMP permission checking of TLB page is bypassed if TLB hits Fix it by propagating PMP permission to TLB page permission. PMP permission checking also use MMU-style API to change TLB permission and size. Signed-off-by: Jim Shu Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 84 +++++++++++++++++++++++++++++---------- target/riscv/pmp.c | 80 +++++++++++++++++++++++++++---------- target/riscv/pmp.h | 4 +- 3 files changed, 125 insertions(+), 43 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 2f43939fb6..f6ac63bf0e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -280,6 +280,49 @@ void riscv_cpu_set_mode(CPURISCVState *env, target_ulo= ng newpriv) env->load_res =3D -1; } =20 +/* + * get_physical_address_pmp - check PMP permission for this physical addre= ss + * + * Match the PMP region and check permission for this physical address and= it's + * TLB page. Returns 0 if the permission checking was successful + * + * @env: CPURISCVState + * @prot: The returned protection attributes + * @tlb_size: TLB page size containing addr. It could be modified after PMP + * permission checking. NULL if not set TLB page for addr. + * @addr: The physical address to be checked permission + * @access_type: The type of MMU access + * @mode: Indicates current privilege level. + */ +static int get_physical_address_pmp(CPURISCVState *env, int *prot, + target_ulong *tlb_size, hwaddr addr, + int size, MMUAccessType access_type, + int mode) +{ + pmp_priv_t pmp_priv; + target_ulong tlb_size_pmp =3D 0; + + if (!riscv_feature(env, RISCV_FEATURE_PMP)) { + *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + } + + if (!pmp_hart_has_privs(env, addr, size, 1 << access_type, &pmp_priv, + mode)) { + *prot =3D 0; + return TRANSLATE_PMP_FAIL; + } + + *prot =3D pmp_priv_to_page_prot(pmp_priv); + if (tlb_size !=3D NULL) { + if (pmp_is_range_in_tlb(env, addr & ~(*tlb_size - 1), &tlb_size_pm= p)) { + *tlb_size =3D tlb_size_pmp; + } + } + + return TRANSLATE_SUCCESS; +} + /* get_physical_address - get the physical address for this virtual address * * Do a page table walk to obtain the physical address corresponding to a @@ -442,9 +485,11 @@ restart: pte_addr =3D base + idx * ptesize; } =20 - if (riscv_feature(env, RISCV_FEATURE_PMP) && - !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), - 1 << MMU_DATA_LOAD, PRV_S)) { + int pmp_prot; + int pmp_ret =3D get_physical_address_pmp(env, &pmp_prot, NULL, pte= _addr, + sizeof(target_ulong), + MMU_DATA_LOAD, PRV_S); + if (pmp_ret !=3D TRANSLATE_SUCCESS) { return TRANSLATE_PMP_FAIL; } =20 @@ -682,13 +727,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, #ifndef CONFIG_USER_ONLY vaddr im_address; hwaddr pa =3D 0; - int prot, prot2; + int prot, prot2, prot_pmp; bool pmp_violation =3D false; bool first_stage_error =3D true; bool two_stage_lookup =3D false; int ret =3D TRANSLATE_FAIL; int mode =3D mmu_idx; - target_ulong tlb_size =3D 0; + /* default TLB page size */ + target_ulong tlb_size =3D TARGET_PAGE_SIZE; =20 env->guest_phys_fault_addr =3D 0; =20 @@ -745,10 +791,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, =20 prot &=3D prot2; =20 - if (riscv_feature(env, RISCV_FEATURE_PMP) && - (ret =3D=3D TRANSLATE_SUCCESS) && - !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)= ) { - ret =3D TRANSLATE_PMP_FAIL; + if (ret =3D=3D TRANSLATE_SUCCESS) { + ret =3D get_physical_address_pmp(env, &prot_pmp, &tlb_size= , pa, + size, access_type, mode); + prot &=3D prot_pmp; } =20 if (ret !=3D TRANSLATE_SUCCESS) { @@ -771,25 +817,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, "%s address=3D%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx " prot %d\n", __func__, address, ret, pa, prot); - } =20 - if (riscv_feature(env, RISCV_FEATURE_PMP) && - (ret =3D=3D TRANSLATE_SUCCESS) && - !pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) { - ret =3D TRANSLATE_PMP_FAIL; + if (ret =3D=3D TRANSLATE_SUCCESS) { + ret =3D get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, + size, access_type, mode); + prot &=3D prot_pmp; + } } + if (ret =3D=3D TRANSLATE_PMP_FAIL) { pmp_violation =3D true; } =20 if (ret =3D=3D TRANSLATE_SUCCESS) { - if (pmp_is_range_in_tlb(env, pa & TARGET_PAGE_MASK, &tlb_size)) { - tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - = 1), - prot, mmu_idx, tlb_size); - } else { - tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_= MASK, - prot, mmu_idx, TARGET_PAGE_SIZE); - } + tlb_set_page(cs, address & ~(tlb_size - 1), pa & ~(tlb_size - 1), + prot, mmu_idx, tlb_size); return true; } else if (probe) { return false; diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 80d0334e1b..ebd874cde3 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -217,6 +217,35 @@ static int pmp_is_in_range(CPURISCVState *env, int pmp= _index, target_ulong addr) return result; } =20 +/* + * Check if the address has required RWX privs when no PMP entry is matche= d. + */ +static bool pmp_hart_has_privs_default(CPURISCVState *env, target_ulong ad= dr, + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, + target_ulong mode) +{ + bool ret; + + if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode =3D=3D PRV_M)) { + /* + * Privileged spec v1.10 states if HW doesn't implement any PMP en= try + * or no PMP entry matches an M-Mode access, the access succeeds. + */ + ret =3D true; + *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC; + } else { + /* + * Other modes are not allowed to succeed if they don't * match a = rule, + * but there are rules. We've checked for no rule earlier in this + * function. + */ + ret =3D false; + *allowed_privs =3D 0; + } + + return ret; +} + =20 /* * Public Interface @@ -226,18 +255,19 @@ static int pmp_is_in_range(CPURISCVState *env, int pm= p_index, target_ulong addr) * Check if the address has required RWX privs to complete desired operati= on */ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t privs, target_ulong mode) + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, + target_ulong mode) { int i =3D 0; int ret =3D -1; int pmp_size =3D 0; target_ulong s =3D 0; target_ulong e =3D 0; - pmp_priv_t allowed_privs =3D 0; =20 /* Short cut if no rules */ if (0 =3D=3D pmp_get_num_rules(env)) { - return (env->priv =3D=3D PRV_M) ? true : false; + return pmp_hart_has_privs_default(env, addr, size, privs, + allowed_privs, mode); } =20 if (size =3D=3D 0) { @@ -277,37 +307,25 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ul= ong addr, * check */ if (((s + e) =3D=3D 2) && (PMP_AMATCH_OFF !=3D a_field)) { - allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC; + *allowed_privs =3D PMP_READ | PMP_WRITE | PMP_EXEC; if ((mode !=3D PRV_M) || pmp_is_locked(env, i)) { - allowed_privs &=3D env->pmp_state.pmp[i].cfg_reg; + *allowed_privs &=3D env->pmp_state.pmp[i].cfg_reg; } =20 - if ((privs & allowed_privs) =3D=3D privs) { - ret =3D 1; - break; - } else { - ret =3D 0; - break; - } + ret =3D ((privs & *allowed_privs) =3D=3D privs); + break; } } =20 /* No rule matched */ if (ret =3D=3D -1) { - if (mode =3D=3D PRV_M) { - ret =3D 1; /* Privileged spec v1.10 states if no PMP entry mat= ches an - * M-Mode access, the access succeeds */ - } else { - ret =3D 0; /* Other modes are not allowed to succeed if they d= on't - * match a rule, but there are rules. We've checked = for - * no rule earlier in this function. */ - } + return pmp_hart_has_privs_default(env, addr, size, privs, + allowed_privs, mode); } =20 return ret =3D=3D 1 ? true : false; } =20 - /* * Handle a write to a pmpcfg CSP */ @@ -442,3 +460,23 @@ bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tl= b_sa, =20 return false; } + +/* + * Convert PMP privilege to TLB page privilege. + */ +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv) +{ + int prot =3D 0; + + if (pmp_priv & PMP_READ) { + prot |=3D PAGE_READ; + } + if (pmp_priv & PMP_WRITE) { + prot |=3D PAGE_WRITE; + } + if (pmp_priv & PMP_EXEC) { + prot |=3D PAGE_EXEC; + } + + return prot; +} diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index c8d5ef4a69..b82a30f0d5 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -59,11 +59,13 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t add= r_index, target_ulong val); target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, - target_ulong size, pmp_priv_t priv, target_ulong mode); + target_ulong size, pmp_priv_t privs, pmp_priv_t *allowed_privs, + target_ulong mode); bool pmp_is_range_in_tlb(CPURISCVState *env, hwaddr tlb_sa, target_ulong *tlb_size); void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index); void pmp_update_rule_nums(CPURISCVState *env); uint32_t pmp_get_num_rules(CPURISCVState *env); +int pmp_priv_to_page_prot(pmp_priv_t pmp_priv); =20 #endif --=20 2.30.1 From nobody Wed Nov 19 00:15:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613921501; cv=none; d=zohomail.com; s=zohoarc; b=RO17Heq8f157AYZfZv1+ZR1sAygxOSJ0JwPCe9xqvZg6SjmJCzVUtZm/IS9hI2og5oWFnSbWnZWYuPfPRSXQPp2/q8riXqzzoUSc/oVTBnt8+pWrLmzYhruJ51gS1kqjGvXuLFstWgiVp8jGLpupI+CULmxLi6WHytzr3QOy5xo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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Sun, 21 Feb 2021 09:02:41 -0500 Received: from exmail.andestech.com ([60.248.187.195]:10481 helo=ATCSQR.andestech.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lDpJl-00058q-V1; Sun, 21 Feb 2021 09:02:40 -0500 Received: from mail.andestech.com (atcpcs16.andestech.com [10.0.1.222]) by ATCSQR.andestech.com with ESMTP id 11LDurVW062705; Sun, 21 Feb 2021 21:56:53 +0800 (GMT-8) (envelope-from cwshu@andestech.com) Received: from ubuntu1604.andestech.com (10.0.12.177) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.487.0; Sun, 21 Feb 2021 22:02:24 +0800 From: Jim Shu To: , Subject: [PATCH 2/3] target/riscv: add log of PMP permission checking Date: Sun, 21 Feb 2021 22:01:21 +0800 Message-ID: <1613916082-19528-3-git-send-email-cwshu@andestech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613916082-19528-1-git-send-email-cwshu@andestech.com> References: <1613916082-19528-1-git-send-email-cwshu@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.12.177] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 11LDurVW062705 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=cwshu@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 21 Feb 2021 10:29:58 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , Jim Shu , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Like MMU translation, add qemu log of PMP permission checking for debugging. Signed-off-by: Jim Shu --- target/riscv/cpu_helper.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f6ac63bf0e..c1ecb8a710 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -794,6 +794,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (ret =3D=3D TRANSLATE_SUCCESS) { ret =3D get_physical_address_pmp(env, &prot_pmp, &tlb_size= , pa, size, access_type, mode); + + qemu_log_mask(CPU_LOG_MMU, + "%s PMP address=3D" TARGET_FMT_plx " ret %d = prot" + " %d tlb_size " TARGET_FMT_lu "\n", + __func__, pa, ret, prot_pmp, tlb_size); + prot &=3D prot_pmp; } =20 @@ -821,6 +827,12 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, if (ret =3D=3D TRANSLATE_SUCCESS) { ret =3D get_physical_address_pmp(env, &prot_pmp, &tlb_size, pa, size, access_type, mode); + + qemu_log_mask(CPU_LOG_MMU, + "%s PMP address=3D" TARGET_FMT_plx " ret %d prot" + " %d tlb_size " TARGET_FMT_lu "\n", + __func__, pa, ret, prot_pmp, tlb_size); + prot &=3D prot_pmp; } } --=20 2.30.1 From nobody Wed Nov 19 00:15:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1613921501; cv=none; d=zohomail.com; s=zohoarc; b=iDird/3uEhW7L1pSrHkCai48XjU6+9kBufPgoJyqyVfIQ1ipL5081UxMt6pA4sAGe7kGwdWozmPLvuCtg3z6X2NcrSzGVKkCArtHw8HUYGL6dzAL5gDnmBcvsCIGkBucsECY61cxWWBhup/XRmm8j1mN2WZV8LEHUKCsTVsfWrw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613921501; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lczgGvFiS2buguKodiHZL9mlIFs+SxVE3vXJ/CK9d4k=; b=Df7qYOvbBQHN502Rz+NqDazpiIrU/lgDRt05tXSwB6txgeaeJ5HF7DOmeXnggpXpXGEHxpx5MZS1K0lTJee2wan5XJvjw6XW2FU1q94oRM1a2+Dt9A7i9E3vI28y6fof9V/41bCRNI5TgoOjWYvm47fRvmpkI5w0PKEgYULcs78= ARC-Authentication-Results: i=1; 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Sun, 21 Feb 2021 21:56:58 +0800 (GMT-8) (envelope-from cwshu@andestech.com) Received: from ubuntu1604.andestech.com (10.0.12.177) by ATCPCS16.andestech.com (10.0.1.222) with Microsoft SMTP Server id 14.3.487.0; Sun, 21 Feb 2021 22:02:27 +0800 From: Jim Shu To: , Subject: [PATCH 3/3] target/riscv: flush TLB pages if PMP permission has been changed Date: Sun, 21 Feb 2021 22:01:22 +0800 Message-ID: <1613916082-19528-4-git-send-email-cwshu@andestech.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613916082-19528-1-git-send-email-cwshu@andestech.com> References: <1613916082-19528-1-git-send-email-cwshu@andestech.com> MIME-Version: 1.0 X-Originating-IP: [10.0.12.177] X-DNSRBL: X-MAIL: ATCSQR.andestech.com 11LDuwh4062723 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=60.248.187.195; envelope-from=cwshu@andestech.com; helo=ATCSQR.andestech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Sun, 21 Feb 2021 10:29:58 -0500 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Palmer Dabbelt , Jim Shu , Sagar Karandikar , Bastian Koppelmann Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" If PMP permission of any address has been changed by updating PMP entry, flush all TLB pages to prevent from getting old permission. Signed-off-by: Jim Shu Reviewed-by: Alistair Francis --- target/riscv/pmp.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index ebd874cde3..cff020122a 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -28,6 +28,7 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" +#include "exec/exec-all.h" =20 static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); @@ -347,6 +348,9 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_= index, cfg_val =3D (val >> 8 * i) & 0xff; pmp_write_cfg(env, (reg_index * 4) + i, cfg_val); } + + /* If PMP permission of any addr has been changed, flush TLB pages. */ + tlb_flush(env_cpu(env)); } =20 =20 --=20 2.30.1