From nobody Mon May 13 08:58:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613750208; cv=none; d=zohomail.com; s=zohoarc; b=Bg1EsFsQffRTiMA0InzLVKGhM9ltjnOoVdt6yuLuGQGn54rUV6Fgdk/evEin8qDIInKoWgLrsrbQwHPe5y74/zel1dNQ0YSvMe8RvkJE6ovgZ8iH8wL+jYi/K6wEpAxEGggl7R4+A+5oNf7eMT9ono7MShp+xKnVDTECGdDqPCg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613750208; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=j6/N7irNLGiWvStxDpMpN01vsIaBwaRHYvGzLGmNrs8=; b=e7XDnK4xJvAP064iMmMgj+Y6FUN1UoR0QiieF/PKrt6T9a/t8tVckVFOig15rBANFjA2CspbqU3wpRaFhV64Jm8SCl88AR38vPCAeY4KehaofPI6OnNgD+QrfEO5qxjHdjnuO0loHxT/F720phDB6yXymI2fN5BokHGPE/RUasA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613750208383325.64977363950334; Fri, 19 Feb 2021 07:56:48 -0800 (PST) Received: from localhost ([::1]:45378 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD899-0004Gb-1e for importer@patchew.org; Fri, 19 Feb 2021 10:56:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD7sV-0000CQ-CT; Fri, 19 Feb 2021 10:39:35 -0500 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]:38715) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD7sT-0008NC-4L; Fri, 19 Feb 2021 10:39:35 -0500 Received: by mail-ed1-x532.google.com with SMTP id s11so10687802edd.5; Fri, 19 Feb 2021 07:39:32 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id t9sm4580314ejc.51.2021.02.19.07.39.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Feb 2021 07:39:30 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j6/N7irNLGiWvStxDpMpN01vsIaBwaRHYvGzLGmNrs8=; b=ZK1mDzKegkT2GrczXVdffqxh/V9pfVDMokWnXbo3WI7AklrHCuaOhdnA/f96c0FiHY XpwDrausSW2aixxd0vQ4nEvliUpxAfJnmd4/ELH0TJeI+8kAcLtSnpf41RLUEVO0Tmlj y+8qUJy0FfOPAA6T+/ZdB53q8iTRE43MUBz41g/8vCjqPZNhTUv+xvj3Y0rOvZ+UZxBG D38PIuHmGXHOcDlNbdO8Jd63Bj03M9CQJIzIaS19gIH8P46af91qCFVJ2h2EJGHHQilu MAUQeOL61dzPZad8qfPS4mIEoWsyavHJ8+ilkPK2tLEGTu1twC0AmkiY2C73oX4f1VYV TFlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j6/N7irNLGiWvStxDpMpN01vsIaBwaRHYvGzLGmNrs8=; b=IT4GJP9ObAPZYma62FeMR2T2frRH89ycfIzqLCGuKwFZ1YbUWW7iLkEySOlZPSJvTH d/ceB3zxAorEu0YRnc9prUR5998Gmb2BW2NIm3jHYqtvp2D/yK4rZ2L2fexq3ddqKNp1 6O0qZNllsTHkIwWnPtm3wvkkONRNdSHNAqqE7J71uaMvX9GCJhlqZhkUyGPP4nY7sXg/ lhVYbWksaVWiYSHL3S8Tjn0VRhspCw0LxNvW1AAVG17qkXvrvjuhfl1ITtEbORwMjLJ3 5oKHp/Xr5gG7O3+8G7ztQC+f5eJ6DSZdO4w8/HINPlxDc3WZgYtXcX7xIO+V6epuLu1R R3Qw== X-Gm-Message-State: AOAM531X5sfmGaGymCBFJLnDQ+AO18xkFYePXSomMpuylvGvq3upldqu cpj1WN72isz2CpUzU/Xm8IQ= X-Google-Smtp-Source: ABdhPJx22le9Hsu4evTSVFMhkxjFA+jv4eOg+/MScAR7Gmkp6xnXb4LSjNmxlSt+BGPBmg4pYegxtQ== X-Received: by 2002:aa7:cdd2:: with SMTP id h18mr7374000edw.38.1613749171348; Fri, 19 Feb 2021 07:39:31 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 1/4] hw/riscv: Drop 'struct MemmapEntry' Date: Fri, 19 Feb 2021 23:39:12 +0800 Message-Id: <1613749155-84250-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> References: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) From: Bin Meng There is already a MemMapEntry type defined in hwaddr.h. Let's drop the RISC-V defined `struct MemmapEntry` and use the existing one. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- (no changes since v1) hw/riscv/microchip_pfsoc.c | 9 +++------ hw/riscv/opentitan.c | 9 +++------ hw/riscv/sifive_e.c | 9 +++------ hw/riscv/sifive_u.c | 11 ++++------- hw/riscv/spike.c | 9 +++------ hw/riscv/virt.c | 9 +++------ 6 files changed, 19 insertions(+), 37 deletions(-) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index e952b49..266f1c3 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -86,10 +86,7 @@ * - Register Map/PF_SoC_RegMap_V1_1/MPFS250T/mpfs250t_ioscb_memmap_dri.= htm * describes the complete IOSCB modules memory maps */ -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} microchip_pfsoc_memmap[] =3D { +static const MemMapEntry microchip_pfsoc_memmap[] =3D { [MICROCHIP_PFSOC_RSVD0] =3D { 0x0, 0x100 }, [MICROCHIP_PFSOC_DEBUG] =3D { 0x100, 0xf00 }, [MICROCHIP_PFSOC_E51_DTIM] =3D { 0x1000000, 0x2000 }, @@ -182,7 +179,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); MicrochipPFSoCState *s =3D MICROCHIP_PFSOC(dev); - const struct MemmapEntry *memmap =3D microchip_pfsoc_memmap; + const MemMapEntry *memmap =3D microchip_pfsoc_memmap; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *rsvd0_mem =3D g_new(MemoryRegion, 1); MemoryRegion *e51_dtim_mem =3D g_new(MemoryRegion, 1); @@ -451,7 +448,7 @@ type_init(microchip_pfsoc_soc_register_types) static void microchip_icicle_kit_machine_init(MachineState *machine) { MachineClass *mc =3D MACHINE_GET_CLASS(machine); - const struct MemmapEntry *memmap =3D microchip_pfsoc_memmap; + const MemMapEntry *memmap =3D microchip_pfsoc_memmap; MicrochipIcicleKitState *s =3D MICROCHIP_ICICLE_KIT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mem_low =3D g_new(MemoryRegion, 1); diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index af34569..e168bff 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -28,10 +28,7 @@ #include "qemu/units.h" #include "sysemu/sysemu.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} ibex_memmap[] =3D { +static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_ROM] =3D { 0x00008000, 16 * KiB }, [IBEX_DEV_RAM] =3D { 0x10000000, 0x10000 }, [IBEX_DEV_FLASH] =3D { 0x20000000, 0x80000 }, @@ -66,7 +63,7 @@ static const struct MemmapEntry { =20 static void opentitan_board_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D ibex_memmap; + const MemMapEntry *memmap =3D ibex_memmap; OpenTitanState *s =3D g_new0(OpenTitanState, 1); MemoryRegion *sys_mem =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); @@ -114,7 +111,7 @@ static void lowrisc_ibex_soc_init(Object *obj) =20 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) { - const struct MemmapEntry *memmap =3D ibex_memmap; + const MemMapEntry *memmap =3D ibex_memmap; MachineState *ms =3D MACHINE(qdev_get_machine()); LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(dev_soc); MemoryRegion *sys_mem =3D get_system_memory(); diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 59bac4c..f939bcf 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -50,10 +50,7 @@ #include "sysemu/sysemu.h" #include "exec/address-spaces.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} sifive_e_memmap[] =3D { +static MemMapEntry sifive_e_memmap[] =3D { [SIFIVE_E_DEV_DEBUG] =3D { 0x0, 0x1000 }, [SIFIVE_E_DEV_MROM] =3D { 0x1000, 0x2000 }, [SIFIVE_E_DEV_OTP] =3D { 0x20000, 0x2000 }, @@ -77,7 +74,7 @@ static const struct MemmapEntry { =20 static void sifive_e_machine_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D sifive_e_memmap; + const MemMapEntry *memmap =3D sifive_e_memmap; =20 SiFiveEState *s =3D RISCV_E_MACHINE(machine); MemoryRegion *sys_mem =3D get_system_memory(); @@ -187,7 +184,7 @@ static void sifive_e_soc_init(Object *obj) static void sifive_e_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); - const struct MemmapEntry *memmap =3D sifive_e_memmap; + const MemMapEntry *memmap =3D sifive_e_memmap; SiFiveESoCState *s =3D RISCV_E_SOC(dev); MemoryRegion *sys_mem =3D get_system_memory(); =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6c1158a..7b59942 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -63,10 +63,7 @@ =20 #include =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} sifive_u_memmap[] =3D { +static const MemMapEntry sifive_u_memmap[] =3D { [SIFIVE_U_DEV_DEBUG] =3D { 0x0, 0x100 }, [SIFIVE_U_DEV_MROM] =3D { 0x1000, 0xf000 }, [SIFIVE_U_DEV_CLINT] =3D { 0x2000000, 0x10000 }, @@ -91,7 +88,7 @@ static const struct MemmapEntry { #define OTP_SERIAL 1 #define GEM_REVISION 0x10070109 =20 -static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, +static void create_fdt(SiFiveUState *s, const MemMapEntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { MachineState *ms =3D MACHINE(qdev_get_machine()); @@ -484,7 +481,7 @@ static void sifive_u_machine_reset(void *opaque, int n,= int level) =20 static void sifive_u_machine_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D sifive_u_memmap; + const MemMapEntry *memmap =3D sifive_u_memmap; SiFiveUState *s =3D RISCV_U_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); @@ -766,7 +763,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) { MachineState *ms =3D MACHINE(qdev_get_machine()); SiFiveUSoCState *s =3D RISCV_U_SOC(dev); - const struct MemmapEntry *memmap =3D sifive_u_memmap; + const MemMapEntry *memmap =3D sifive_u_memmap; MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); MemoryRegion *l2lim_mem =3D g_new(MemoryRegion, 1); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 56986ec..ed4ca98 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -43,16 +43,13 @@ #include "sysemu/qtest.h" #include "sysemu/sysemu.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} spike_memmap[] =3D { +static const MemMapEntry spike_memmap[] =3D { [SPIKE_MROM] =3D { 0x1000, 0xf000 }, [SPIKE_CLINT] =3D { 0x2000000, 0x10000 }, [SPIKE_DRAM] =3D { 0x80000000, 0x0 }, }; =20 -static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, +static void create_fdt(SpikeState *s, const MemMapEntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { void *fdt; @@ -179,7 +176,7 @@ static void create_fdt(SpikeState *s, const struct Memm= apEntry *memmap, =20 static void spike_board_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D spike_memmap; + const MemMapEntry *memmap =3D spike_memmap; SpikeState *s =3D SPIKE_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2299b3a..cfd52bc 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -43,10 +43,7 @@ #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" =20 -static const struct MemmapEntry { - hwaddr base; - hwaddr size; -} virt_memmap[] =3D { +static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, [VIRT_MROM] =3D { 0x1000, 0xf000 }, [VIRT_TEST] =3D { 0x100000, 0x1000 }, @@ -170,7 +167,7 @@ static void create_pcie_irq_map(void *fdt, char *nodena= me, 0x1800, 0, 0, 0x7); } =20 -static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, +static void create_fdt(RISCVVirtState *s, const MemMapEntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { void *fdt; @@ -490,7 +487,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion = *sys_mem, =20 static void virt_machine_init(MachineState *machine) { - const struct MemmapEntry *memmap =3D virt_memmap; + const MemMapEntry *memmap =3D virt_memmap; RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); --=20 2.7.4 From nobody Mon May 13 08:58:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613749940; cv=none; d=zohomail.com; s=zohoarc; b=Y33XXt7gLl0WJnFoqYNwrg0Bvkv74PD4vqrN0aHQT3iPrCja6QY1OxjP+UTnPVeBiyWzICGDj/gNNUyMTnSYfBf2XISX/dfLTB21NCyNRMgGMhql20QQuLyAIXHtX2kV8jHVPdW69FqyTpjTPWI145m5mWazv/C9y12Lj2XRfUQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613749940; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=sWVSQN365y4RrwajNe3ilvA3SGaPN96YcYwIQ7DCO9k=; b=WZuc/GhmgMgix53qAEJMJoK24W9NAnOKyXlVlqAdr5TsgDj/33E02xCgilCiiIIvnqHb87oujFiC661/m1KFSEeWgh/aA39i9v4D9SdwoIp8Aw5/PWBOX2+hnVTQ/lRJ/OZlbAin6KWiUVnA9bZCyTgO8pU/ZWPmy41+SUb1834= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613749939988626.007002043919; Fri, 19 Feb 2021 07:52:19 -0800 (PST) Received: from localhost ([::1]:60298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD84n-0006xf-5E for importer@patchew.org; Fri, 19 Feb 2021 10:52:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD7sa-0000IP-VD; Fri, 19 Feb 2021 10:39:42 -0500 Received: from mail-ej1-x636.google.com ([2a00:1450:4864:20::636]:40333) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD7sW-0008Oc-Cp; Fri, 19 Feb 2021 10:39:40 -0500 Received: by mail-ej1-x636.google.com with SMTP id u20so13474251ejb.7; Fri, 19 Feb 2021 07:39:35 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id t9sm4580314ejc.51.2021.02.19.07.39.31 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Feb 2021 07:39:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=sWVSQN365y4RrwajNe3ilvA3SGaPN96YcYwIQ7DCO9k=; b=orfUTAaAHV/l+d5pCEp0F4a+d/sndvF/WAjPKlj9DMqAoOaZ9XgYGAsvnZUpguRUFL RaggNViwAceiSGNhaTp6iGIGzdn2YPhAY4EPieJV04z13Nx9BO6O+qV4okTkkg5JBRkE IP0WzO+NXT8JZrlv9Dtr6iuZwqf8Zugf/UYlnPXmEC85+nkwyCRqocuN2Rt8A+zdxWD7 02eddxZM50zgwmxM1ajepcrALitVvj+Ki75d5nCdZvTm6sCXQaHXIKrZcnCuefuYAlW1 3GsFpTPXR9m2JyNHMrys1JrlPwX5BNRfQcnYIwKsfbv+lE6evCEa1vDJ5c12Q3wlqF4b uK9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=sWVSQN365y4RrwajNe3ilvA3SGaPN96YcYwIQ7DCO9k=; b=CozK5SDtmb3334D/sfGab/zo5fr0cUMFBD9AI8wdEKhj6yvtSkILmfxl/I2OJNXqw3 qvLfjpU6G+3G1/7ybdZvQYGof3ms3PddZL4CsfGl9zVfe5Xo3DTnDV6bjZ3N5lTbtJTJ tMDN/+dqAWgWU/ecGEPDsYbi9PrMwSWmmGN5oDrDA/BM6YfSGUYOVsBbGVR1UIM/xFY1 fQDLWq1/+7r43sx4VWP1FSaCJwqJB+jVqxkbUrjjxhlyXK+Vvh3UyT/HNGl5OnRZ/fQ2 LtJ435ibsgKkMKS7AAOWQSDnU6J06jEDoYufOaYvcloArpvKjqD7L3mdBwWXZYk8pgnT puRw== X-Gm-Message-State: AOAM530gDvQCrFZo912YXYaXnM6jxHfKs+n4pediDrVbObcG4HMlcslB 6qvUc/j4Ppm3QhllAmM5vgw= X-Google-Smtp-Source: ABdhPJwdDp8QkLJtuqYk/soiHIV31Dpw8/vR2aNld9kKe8utJXFvNJqYLiChSsp5sHDjMqFVjMYQdw== X-Received: by 2002:a17:906:9147:: with SMTP id y7mr7982366ejw.243.1613749174795; Fri, 19 Feb 2021 07:39:34 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 2/4] hw/riscv: virt: Drop the 'link_up' parameter of gpex_pcie_init() Date: Fri, 19 Feb 2021 23:39:13 +0800 Message-Id: <1613749155-84250-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> References: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng `link_up` is never used in gpex_pcie_init(). Drop it. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/virt.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index cfd52bc..1d05bb3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -449,7 +449,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion = *sys_mem, hwaddr ecam_base, hwaddr ecam_si= ze, hwaddr mmio_base, hwaddr mmio_si= ze, hwaddr pio_base, - DeviceState *plic, bool link_up) + DeviceState *plic) { DeviceState *dev; MemoryRegion *ecam_alias, *ecam_reg; @@ -669,12 +669,12 @@ static void virt_machine_init(MachineState *machine) } =20 gpex_pcie_init(system_memory, - memmap[VIRT_PCIE_ECAM].base, - memmap[VIRT_PCIE_ECAM].size, - memmap[VIRT_PCIE_MMIO].base, - memmap[VIRT_PCIE_MMIO].size, - memmap[VIRT_PCIE_PIO].base, - DEVICE(pcie_plic), true); + memmap[VIRT_PCIE_ECAM].base, + memmap[VIRT_PCIE_ECAM].size, + memmap[VIRT_PCIE_MMIO].base, + memmap[VIRT_PCIE_MMIO].size, + memmap[VIRT_PCIE_PIO].base, + DEVICE(pcie_plic)); =20 serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, --=20 2.7.4 From nobody Mon May 13 08:58:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613750956; cv=none; d=zohomail.com; s=zohoarc; b=JmYy6nKEmRogQnH2iIRiq4dndFZMtzcVDdagAucKgn4Kwx4wH+OQS4oDPZ+nOIi5kTjt/yK8m89WxjfxBZYA/Ov5dohToI/hjwcn5Ok8uHihfv1Pd1kYabyb+QY1s0ziS7SIrSOhvMe7Yv0vTned3/Caei3PJY4p+8ez4le/cGM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613750956; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=Osdk42GnHmUXWlOf+Jf1ywxYiD4+Y49aj/UgdhJyXDY=; b=FRRdM595EFZLMRv4oA0GWzI5Aucmm28/2r1HgaW4d8YGUN3iyFXRJSQKTCANyGuDEyrG/F8+Yk5IIP4GVwyxKPCQeEyThu1B179+IHHW8IdrKc7mL8HpGvynNUtODdyz1uwg7pudX/NBYIhcUEmKjNHMEbkRO0DKEymnJXU3wU0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613750956724649.770477878086; Fri, 19 Feb 2021 08:09:16 -0800 (PST) Received: from localhost ([::1]:44466 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD8LD-0000PN-UB for importer@patchew.org; Fri, 19 Feb 2021 11:09:15 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD7se-0000KK-HX; Fri, 19 Feb 2021 10:39:44 -0500 Received: from mail-ej1-x633.google.com ([2a00:1450:4864:20::633]:40331) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD7sb-0008PO-0q; Fri, 19 Feb 2021 10:39:44 -0500 Received: by mail-ej1-x633.google.com with SMTP id u20so13474709ejb.7; Fri, 19 Feb 2021 07:39:39 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id t9sm4580314ejc.51.2021.02.19.07.39.35 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Feb 2021 07:39:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Osdk42GnHmUXWlOf+Jf1ywxYiD4+Y49aj/UgdhJyXDY=; b=Pcj5rYQy0HD3D0hHfuSazRQ5znm7DSrMH6VJrxRqtFc8brQuysvMx3nzoU0VEiMu0L G+QgKoPxmEPdl7fTQY0i6gP6mRNe3cvkefBp/sod6OZrxJkUyRPtIq4Y8Z2D3WnOMP9F SfIFkuRci0vsEWhtqVRSnae6mnNo9XIPOJPI3YDg8ymoSDVDZznsYSmc+Qv7ppYLIBzv j1W5SyU3jwZ23uZe1D/uhZfxnbAPCsjx/WYGJHs+xH8azKBFY394c1v7Q2L0jzGhADxo dQ8xIgPJu2I5rLrnj426jlDnLdpLa5wdIKa3U+VpzGtWVtYyEoaI/OXGqch6+oWV0EfO y48Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Osdk42GnHmUXWlOf+Jf1ywxYiD4+Y49aj/UgdhJyXDY=; b=Hc5nIQdelNPjdfw1U0vYlvGEWdoNxeSxmZysLBXYlMDStBMXZ5a5IzHDAvPYfGcqlX HCyZ8EQEfyNOv7DqppbkF60+dI4IJ35drp6Er1zic3UxSm0Kqh15xvzqGKGmmZxsNOpt B3U2FXo1AM/OwkVthy811+xkfK2YJmjy3Ncfl1FWDOQ2RZPLQM+/xJvhsx3QoLMvd2pb dCH+a00VlTBmQ0kgqkAQ0JEr9OuWqSdzjuYhEPre3zrwnbkZe4rFIVdEKxLn691B77a7 dV4QtAwUv/0gRO6dpSDWAnwdD0s6M+E4pj8NfgezTjxL6N9yGlUawY5Ytp9iJTkPc+h5 N/pA== X-Gm-Message-State: AOAM532ENelyTKxrbKTOeA6iau6coP0GsWbFf3nFfPqry5m4Xrq2u9dr D6vO9NlOEP7XWVu2gZD93Z4= X-Google-Smtp-Source: ABdhPJxsslC0Yc5Wa6qR9mKc6sxOLj8h/CN8isO1ZyuxNMw9dZKLRptfeBT20jwlN5sPXVmjR5/Fkg== X-Received: by 2002:a17:906:34c3:: with SMTP id h3mr9326292ejb.132.1613749178267; Fri, 19 Feb 2021 07:39:38 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 3/4] hw/riscv: virt: Limit RAM size in a 32-bit system Date: Fri, 19 Feb 2021 23:39:14 +0800 Message-Id: <1613749155-84250-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> References: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng RV32 supports 34-bit physical address hence the maximum RAM size should be limitted. Limit the RAM size to 10 GiB, which leaves some room for PCIe high mmio space. For 32-bit host, this is not needed as machine->ram_size cannot represent a RAM size that big. Use a #if size test to only do the size limitation for the 64-bit host. Signed-off-by: Bin Meng --- Changes in v2: - Use a #if size test to only do the size limitation for the 64-bit host hw/riscv/virt.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 1d05bb3..fc90bc8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -590,6 +590,16 @@ static void virt_machine_init(MachineState *machine) } } =20 + if (riscv_is_32bit(&s->soc[0])) { +#if HOST_LONG_BITS =3D=3D 64 + /* limit RAM size in a 32-bit system */ + if (machine->ram_size > 10 * GiB) { + machine->ram_size =3D 10 * GiB; + error_report("Limitting RAM size to 10 GiB"); + } +#endif + } + /* register system main memory (actual RAM) */ memory_region_init_ram(main_mem, NULL, "riscv_virt_board.ram", machine->ram_size, &error_fatal); --=20 2.7.4 From nobody Mon May 13 08:58:25 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1613751101; cv=none; d=zohomail.com; s=zohoarc; b=PGpMehfT8FoBLuX5MjENvPFPUpNPC4saxUVFH3g+PMq4SXhqMUglXHQKF/tKH2xkACtHtvDTrZH6CJvZffHOrGt51AEO+sVkP0kotTBnxYVS8/1n/2vntLkXt/9lx9qjFD6zOFcQoyAoKfAEgCkeKUsAIU3Q4An/dNSJDOrh1Sk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1613751101; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=5sgojbwknwegM5rdWeI9P72ym0q49TeKTS3uF5AnARY=; b=Y/amQyJtRsmHBpEe2oo4sIyBxKJTfKyOGVPDa9JysRuL2duuXYMWYbRQ/X74i0ct0T1769lg5MtgiJhmfTHiJCCmzLEReFQKvQ/Dk98aPzvv7SsVAvjaIpnPVAb+FbSo+Z47QiWhz4vFV6NLxiIo0g8EPVUV2y4KWvDOTfP6Dhk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1613751100996556.7055579475484; Fri, 19 Feb 2021 08:11:40 -0800 (PST) Received: from localhost ([::1]:50772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lD8NY-0003Ks-7H for importer@patchew.org; Fri, 19 Feb 2021 11:11:40 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:46682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lD7sh-0000Lq-DS; Fri, 19 Feb 2021 10:39:47 -0500 Received: from mail-ej1-x62f.google.com ([2a00:1450:4864:20::62f]:34933) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1lD7se-0008Qq-JM; Fri, 19 Feb 2021 10:39:47 -0500 Received: by mail-ej1-x62f.google.com with SMTP id g5so14239307ejt.2; Fri, 19 Feb 2021 07:39:43 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id t9sm4580314ejc.51.2021.02.19.07.39.38 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Fri, 19 Feb 2021 07:39:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=5sgojbwknwegM5rdWeI9P72ym0q49TeKTS3uF5AnARY=; b=RFXWheITJ3vdxNIzb4mVYDefidGoKiJmrzEu9BnStGFOSEi9I+3yhYK8XqOSUxA9/H GjuS6ZeBRgOuJCkyND1+VB0AKGk20YNKDizC8Q+zPB/Sm6T8d0eFsga4TSznM+fO/o86 PIXvVxoFiX68/xq4epnTnl+v38TVvUra07SB0QI6XCOt4HUqECtSWuqtDIR0PaHhr1Vu RPC0KTLpEzh/SWaBivzDVllAx1cpvET207lyg4UO91Gn/XXWfNohwKN4HjtVSe6cAMrs THeo92HUZ/pM+eIY1ntYv6ifcj+VGSHbHsWFX7snZl4xqqwefKRMQHcy2ZSfHWLIigbA EAOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=5sgojbwknwegM5rdWeI9P72ym0q49TeKTS3uF5AnARY=; b=Yn7WyySec1hbSg4Wh2bub17ABUKtsoKEmrsFnomquf72cNUzZqpDqoxGUjVvwDhWYc 6l1rEaI9xtmmjhDF7QFIjlmnrvd8chZbF/taANVOpa4R+2fjFvyA2L57ScCqhkycWJlU q4kHAcUtvdn6wyxt173Qimr8hLuqrP2CQWNQrCWkLAr45uvm64gyxH9kQH8IkHDIaYt3 v82svmOVEaybGJSj/psjgN90HAffDNycDp34x2Tc6cI/vzZ1RHuzcu0v95JZmT3lvkYB mJ2CizbflNIA9rWsHsaCnSbzkbA023RkwWvFCXYou1a9jG/eR6ftUlso/wFgiV7vI5Ah PQWw== X-Gm-Message-State: AOAM531mT4EBpg9Yw3ax1mvnu6EeDJbMUcB6NTzHprXbbrkEnlEXgpw5 FdZPee1PS9dZwfnBgIhsDcREhqzaLFQ= X-Google-Smtp-Source: ABdhPJwGgrt8PZuuwijNy+3+voYilP3EDkqgn7Wt5EuSaXl2Xgm4eZqFvarlAXr90YZY0hPYewJREw== X-Received: by 2002:a17:906:f0c3:: with SMTP id dk3mr9207844ejb.540.1613749182159; Fri, 19 Feb 2021 07:39:42 -0800 (PST) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 4/4] hw/riscv: virt: Map high mmio for PCIe Date: Fri, 19 Feb 2021 23:39:15 +0800 Message-Id: <1613749155-84250-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> References: <1613749155-84250-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Some peripherals require 64-bit PCI address, so let's map the high mmio space for PCIe. For RV32, the address is hardcoded to below 4 GiB from the highest accessible physical address. For RV64, the base address depends on top of RAM and is aligned to its size which is using 16 GiB for now. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/virt.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index fc90bc8..972cdc2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -59,6 +59,15 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_DRAM] =3D { 0x80000000, 0x0 }, }; =20 +/* PCIe high mmio is fixed for RV32 */ +#define VIRT32_HIGH_PCIE_MMIO_BASE 0x300000000ULL +#define VIRT32_HIGH_PCIE_MMIO_SIZE (4 * GiB) + +/* PCIe high mmio for RV64, size is fixed but base depends on top of RAM */ +#define VIRT64_HIGH_PCIE_MMIO_SIZE (16 * GiB) + +static MemMapEntry virt_high_pcie_memmap; + #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) =20 static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, @@ -371,7 +380,11 @@ static void create_fdt(RISCVVirtState *s, const MemMap= Entry *memmap, 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, 1, FDT_PCI_RANGE_MMIO, 2, memmap[VIRT_PCIE_MMIO].base, - 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); + 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size, + 1, FDT_PCI_RANGE_MMIO_64BIT, + 2, virt_high_pcie_memmap.base, + 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); + create_pcie_irq_map(fdt, name, plic_pcie_phandle); g_free(name); =20 @@ -448,12 +461,14 @@ update_bootargs: static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, hwaddr ecam_base, hwaddr ecam_si= ze, hwaddr mmio_base, hwaddr mmio_si= ze, + hwaddr high_mmio_base, + hwaddr high_mmio_size, hwaddr pio_base, DeviceState *plic) { DeviceState *dev; MemoryRegion *ecam_alias, *ecam_reg; - MemoryRegion *mmio_alias, *mmio_reg; + MemoryRegion *mmio_alias, *high_mmio_alias, *mmio_reg; qemu_irq irq; int i; =20 @@ -473,6 +488,13 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion= *sys_mem, mmio_reg, mmio_base, mmio_size); memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias= ); =20 + /* Map high MMIO space */ + high_mmio_alias =3D g_new0(MemoryRegion, 1); + memory_region_init_alias(high_mmio_alias, OBJECT(dev), "pcie-mmio-high= ", + mmio_reg, high_mmio_base, high_mmio_size); + memory_region_add_subregion(get_system_memory(), high_mmio_base, + high_mmio_alias); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { @@ -598,6 +620,13 @@ static void virt_machine_init(MachineState *machine) error_report("Limitting RAM size to 10 GiB"); } #endif + virt_high_pcie_memmap.base =3D VIRT32_HIGH_PCIE_MMIO_BASE; + virt_high_pcie_memmap.size =3D VIRT32_HIGH_PCIE_MMIO_SIZE; + } else { + virt_high_pcie_memmap.size =3D VIRT64_HIGH_PCIE_MMIO_SIZE; + virt_high_pcie_memmap.base =3D memmap[VIRT_DRAM].base + machine->r= am_size; + virt_high_pcie_memmap.base =3D + ROUND_UP(virt_high_pcie_memmap.base, virt_high_pcie_memmap.siz= e); } =20 /* register system main memory (actual RAM) */ @@ -683,6 +712,8 @@ static void virt_machine_init(MachineState *machine) memmap[VIRT_PCIE_ECAM].size, memmap[VIRT_PCIE_MMIO].base, memmap[VIRT_PCIE_MMIO].size, + virt_high_pcie_memmap.base, + virt_high_pcie_memmap.size, memmap[VIRT_PCIE_PIO].base, DEVICE(pcie_plic)); =20 --=20 2.7.4