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Iglesias" , Peter Maydell Subject: [PATCH v3 1/5] hw/dma: xlnx_csu_dma: Implement a basic XLNX CSU DMA model Date: Wed, 10 Feb 2021 18:10:09 +0800 Message-Id: <1612951813-50542-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> References: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::534; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng ZynqMP QSPI supports SPI transfer using DMA mode, but currently this is unimplemented. When QSPI is programmed to use DMA mode, QEMU will crash. This is observed when testing VxWorks 7. This adds a basic CSU DMA model and the implementation is based on https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c The model implements only the basic DMA transfer function of the DST part, verified along with ZynqMP GQSPI model. Other advanced features are not implemented. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- Changes in v3: - Implement DMA as a separate CSU DMA model Changes in v2: - Remove unconnected TYPE_STREAM_SINK link property - Add a TYPE_MEMORY_REGION link property, to allow board codes to tell the device what its view of the world that it is doing DMA to is - Replace cpu_physical_memory_write() with address_space_write() include/hw/dma/xlnx_csu_dma.h | 39 ++++ hw/dma/xlnx_csu_dma.c | 444 ++++++++++++++++++++++++++++++++++++++= ++++ hw/dma/Kconfig | 4 + hw/dma/meson.build | 1 + 4 files changed, 488 insertions(+) create mode 100644 include/hw/dma/xlnx_csu_dma.h create mode 100644 hw/dma/xlnx_csu_dma.c diff --git a/include/hw/dma/xlnx_csu_dma.h b/include/hw/dma/xlnx_csu_dma.h new file mode 100644 index 0000000..bd87ee7 --- /dev/null +++ b/include/hw/dma/xlnx_csu_dma.h @@ -0,0 +1,39 @@ +/* + * ZynqMP Platform CSU Stream DMA emulation + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef XLNX_CSU_DMA_H +#define XLNX_CSU_DMA_H + +#define TYPE_XLNX_CSU_DMA "xlnx.csu_dma" + +#define XLNX_CSU_DMA_REGS_MAX ((0x28 / 4) + 1) + +typedef struct XlnxCSUDMA { + SysBusDevice busdev; + MemoryRegion iomem; + MemoryRegion *dma_mr; + AddressSpace *dma_as; + qemu_irq irq; + StreamSink *tx; + uint32_t regs[XLNX_CSU_DMA_REGS_MAX]; + RegisterInfo regs_info[XLNX_CSU_DMA_REGS_MAX]; +} XlnxCSUDMA; + +#define XLNX_CSU_DMA(obj) \ + OBJECT_CHECK(XlnxCSUDMA, (obj), TYPE_XLNX_CSU_DMA) + +#endif diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c new file mode 100644 index 0000000..6f237ca --- /dev/null +++ b/hw/dma/xlnx_csu_dma.c @@ -0,0 +1,444 @@ +/* + * ZynqMP Platform CSU Stream DMA emulation + * + * This implements only the basic DMA transfer function of the DST part, + * other advanced features are not implemented. + * + * This implementation is based on + * https://github.com/Xilinx/qemu/blob/master/hw/dma/csu_stream_dma.c + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "sysemu/dma.h" +#include "hw/ptimer.h" +#include "hw/stream.h" +#include "hw/register.h" +#include "hw/dma/xlnx_csu_dma.h" + +/* + * Ref: UG1087 (v1.7) February 8, 2019 + * https://www.xilinx.com/html_docs/registers/ug1087/ + * ug1087-zynq-ultrascale-registers.html + */ +REG32(ADDR, 0x0) + FIELD(ADDR, ADDR, 2, 30) /* wo */ +REG32(SIZE, 0x4) + FIELD(SIZE, SIZE, 2, 27) /* wo */ +REG32(STATUS, 0x8) + FIELD(STATUS, DONE_CNT, 13, 3) /* wtc */ + FIELD(STATUS, BUSY, 0, 1) /* ro */ +REG32(CTRL, 0xc) + FIELD(CTRL, FIFO_LVL_HIT_THRESH, 25, 7) /* rw, reset: 0x40 */ + FIELD(CTRL, APB_ERR_RESP, 24, 1) /* rw */ + FIELD(CTRL, ENDIANNESS, 23, 1) /* rw */ + FIELD(CTRL, AXI_BRST_TYPE, 22, 1) /* rw */ + FIELD(CTRL, TIMEOUT_VAL, 10, 12) /* rw, reset: 0xFFE */ + FIELD(CTRL, FIFO_THRESH, 2, 8) /* rw, reset: 0x80 */ + FIELD(CTRL, PAUSE_STRM, 1, 1) /* rw */ + FIELD(CTRL, PAUSE_MEM, 0, 1) /* rw */ +REG32(RES, 0x10) +REG32(INT_STATUS, 0x14) + FIELD(INT_STATUS, FIFO_OVERFLOW, 7, 1) /* wtc */ + FIELD(INT_STATUS, INVALID_APB, 6, 1) /* wtc */ + FIELD(INT_STATUS, THRESH_HIT, 5, 1) /* wtc */ + FIELD(INT_STATUS, TIMEOUT_MEM, 4, 1) /* wtc */ + FIELD(INT_STATUS, TIMEOUT_STRM, 3, 1) /* wtc */ + FIELD(INT_STATUS, AXI_BRESP_ERR, 2, 1) /* wtc */ + FIELD(INT_STATUS, DONE, 1, 1) /* wtc */ +REG32(INT_ENABLE, 0x18) + FIELD(INT_ENABLE, FIFO_OVERFLOW, 7, 1) /* wtc */ + FIELD(INT_ENABLE, INVALID_APB, 6, 1) /* wtc */ + FIELD(INT_ENABLE, THRESH_HIT, 5, 1) /* wtc */ + FIELD(INT_ENABLE, TIMEOUT_MEM, 4, 1) /* wtc */ + FIELD(INT_ENABLE, TIMEOUT_STRM, 3, 1) /* wtc */ + FIELD(INT_ENABLE, AXI_BRESP_ERR, 2, 1) /* wtc */ + FIELD(INT_ENABLE, DONE, 1, 1) /* wtc */ +REG32(INT_DISABLE, 0x1c) + FIELD(INT_DISABLE, FIFO_OVERFLOW, 7, 1) /* wtc */ + FIELD(INT_DISABLE, INVALID_APB, 6, 1) /* wtc */ + FIELD(INT_DISABLE, THRESH_HIT, 5, 1) /* wtc */ + FIELD(INT_DISABLE, TIMEOUT_MEM, 4, 1) /* wtc */ + FIELD(INT_DISABLE, TIMEOUT_STRM, 3, 1) /* wtc */ + FIELD(INT_DISABLE, AXI_BRESP_ERR, 2, 1) /* wtc */ + FIELD(INT_DISABLE, DONE, 1, 1) /* wtc */ +REG32(INT_MASK, 0x20) /* reset: 0xFE */ + FIELD(INT_MASK, FIFO_OVERFLOW, 7, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, INVALID_APB, 6, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, THRESH_HIT, 5, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, TIMEOUT_MEM, 4, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, TIMEOUT_STRM, 3, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, AXI_BRESP_ERR, 2, 1) /* ro, reset: 0x1 */ + FIELD(INT_MASK, DONE, 1, 1) /* ro, reset: 0x1 */ +REG32(CTRL2, 0x24) /* reset: 0xFFF8 */ + FIELD(CTRL2, ARCACHE, 24, 3) /* rw */ + FIELD(CTRL2, TIMEOUT_EN, 22, 1) /* rw */ + FIELD(CTRL2, TIMEOUT_PRE, 4, 12) /* rw, reset: 0xFFF */ + FIELD(CTRL2, MAX_OUTS_CMDS, 0, 4) /* rw, reset: 0x8 */ +REG32(ADDR_MSB, 0x28) + FIELD(ADDR_MSB, ADDR_MSB, 0, 12) /* wo */ + +#define CSU_DMA_INT_REGS_MASK 0xfe + +static uint64_t addr_pre_write(RegisterInfo *reg, uint64_t val) +{ + return val & R_ADDR_ADDR_MASK; +} + +static uint64_t size_pre_write(RegisterInfo *reg, uint64_t val) +{ + return val & R_SIZE_SIZE_MASK; +} + +static uint64_t status_pre_write(RegisterInfo *reg, uint64_t val) +{ + return val & (R_STATUS_DONE_CNT_MASK | R_STATUS_BUSY_MASK); +} + +static uint64_t addr_msb_pre_write(RegisterInfo *reg, uint64_t val) +{ + return val & R_ADDR_MSB_ADDR_MSB_MASK; +} + +static void csu_dma_done(XlnxCSUDMA *s) +{ + int cnt; + + s->regs[R_STATUS] &=3D ~R_STATUS_BUSY_MASK; + s->regs[R_INT_STATUS] |=3D R_INT_STATUS_DONE_MASK; + + cnt =3D ARRAY_FIELD_EX32(s->regs, STATUS, DONE_CNT) + 1; + ARRAY_FIELD_DP32(s->regs, STATUS, DONE_CNT, cnt); +} + +static void csu_dma_update_irq(XlnxCSUDMA *s) +{ + qemu_set_irq(s->irq, !!(s->regs[R_INT_STATUS] & ~s->regs[R_INT_MASK])); +} + +static uint64_t int_enable_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + /* + * 1: Enable this interrupt field (The mask bit will be cleared to 0) + * 0: No effect + * Reads to this register will return 0 + */ + uint32_t ret =3D s->regs[R_INT_ENABLE] | (val & CSU_DMA_INT_REGS_MASK); + + s->regs[R_INT_MASK] &=3D ~ret; + + /* The field in int_disable should also be cleared */ + s->regs[R_INT_DISABLE] &=3D ~ret; + + return ret; +} + +static void int_enable_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + csu_dma_update_irq(s); + return; +} + +static void int_disable_post_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + csu_dma_update_irq(s); + + /* Clear int_status when disable DMA interrupt */ + s->regs[R_INT_STATUS] &=3D 0; + return; +} + +static uint64_t int_disable_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + /* + * 1: Disable this interrupt field (The mask bit will be set to 1) + * 0: No effect + * Reads to this register will return 0 + */ + uint32_t ret =3D s->regs[R_INT_DISABLE] | (val & CSU_DMA_INT_REGS_MASK= ); + + s->regs[R_INT_MASK] |=3D ret; + + /* The field in int_enable should also be cleared */ + s->regs[R_INT_ENABLE] &=3D ~ret; + return ret; +} + +static uint64_t int_status_pre_write(RegisterInfo *reg, uint64_t val) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(reg->opaque); + + /* Write 1: clear status bit */ + return s->regs[R_INT_STATUS] & ~(val & CSU_DMA_INT_REGS_MASK); +} + +static RegisterAccessInfo xlnx_csu_dma_regs_info[] =3D { + { .name =3D "CSU_DMA_ADDR", + .addr =3D A_ADDR, + .pre_write =3D addr_pre_write + }, { + .name =3D "CSU_DMA_SIZE", + .addr =3D A_SIZE, + .pre_write =3D size_pre_write + }, { + .name =3D "CSU_DMA_STATUS", + .addr =3D A_STATUS, + .pre_write =3D status_pre_write, + .ro =3D R_STATUS_BUSY_MASK + }, { + .name =3D "CSU_DMA_CTRL", + .addr =3D A_CTRL, + .reset =3D 0x803FFA00 + }, { + .name =3D "CSU_DMA_RES", + .addr =3D A_RES, + }, { + .name =3D "CSU_DMA_INT_STATUS", + .addr =3D A_INT_STATUS, + .pre_write =3D int_status_pre_write + }, { + .name =3D "CSU_DMA_INT_ENABLE", + .addr =3D A_INT_ENABLE, + .pre_write =3D int_enable_pre_write, + .post_write =3D int_enable_post_write + }, { + .name =3D "CSU_DMA_INT_DISABLE", + .addr =3D A_INT_DISABLE, + .pre_write =3D int_disable_pre_write, + .post_write =3D int_disable_post_write + }, { + .name =3D "CSU_DMA_INT_MASK", + .addr =3D A_INT_MASK, + .ro =3D ~0, + .reset =3D CSU_DMA_INT_REGS_MASK + }, { + .name =3D "CSU_DMA_CTRL2", + .addr =3D A_CTRL2, + .reset =3D 0x081BFFF8 + }, { + .name =3D "CSU_DMA_ADDR_MSB", + .addr =3D A_ADDR_MSB, + .pre_write =3D addr_msb_pre_write + } +}; + +static uint32_t csu_dma_advance(XlnxCSUDMA *s, uint32_t len, hwaddr dst) +{ + uint32_t size =3D s->regs[R_SIZE]; + + size -=3D len; + size &=3D R_SIZE_SIZE_MASK; + dst +=3D len; + + s->regs[R_SIZE] =3D size; + s->regs[R_ADDR] =3D (uint32_t) dst; + s->regs[R_ADDR_MSB] =3D dst >> 32; + + return size; +} + +static size_t xlnx_csu_dma_stream_push(StreamSink *obj, uint8_t *buf, + size_t len, bool eop) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(obj); + hwaddr dst =3D (hwaddr)s->regs[R_ADDR_MSB] << 32 | s->regs[R_ADDR]; + uint32_t size =3D s->regs[R_SIZE]; + uint32_t mlen =3D MIN(size, len) & (~3); /* Size is word aligned */ + + if (size =3D=3D 0 || len <=3D 0) { + return 0; + } + + if (address_space_write(s->dma_as, dst, MEMTXATTRS_UNSPECIFIED, buf, m= len) + !=3D MEMTX_OK) { + return 0; + } + + size =3D csu_dma_advance(s, mlen, dst); + + if (size =3D=3D 0) { + csu_dma_done(s); + csu_dma_update_irq(s); + } + + return mlen; +} + +static bool xlnx_csu_dma_stream_can_push(StreamSink *obj, + StreamCanPushNotifyFn notify, + void *notify_opaque) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(obj); + + return s->regs[R_SIZE] ? true : false; +} + +static uint64_t xlnx_csu_dma_read(void *opaque, hwaddr offset, unsigned si= ze) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(opaque); + RegisterInfo *r =3D &s->regs_info[offset / 4]; + uint64_t ret =3D 0; + + if (!r->data) { + char *path =3D object_get_canonical_path(OBJECT(s)); + qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n", + path, offset); + g_free(path); + return 0; + } + + ret =3D register_read(r, ~0, NULL, false); + return ret; +} + +static void xlnx_csu_dma_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(opaque); + uint32_t reg =3D offset / 4; + RegisterInfo *r =3D &s->regs_info[reg]; + + if (!r->data) { + char *path =3D object_get_canonical_path(OBJECT(s)); + qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n", + path, offset); + g_free(path); + return; + } + + register_write(r, value, ~0, NULL, false); +} + +static const MemoryRegionOps xlnx_csu_dma_ops =3D { + .read =3D xlnx_csu_dma_read, + .write =3D xlnx_csu_dma_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + } +}; + +static void xlnx_csu_dma_reset(DeviceState *dev) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void xlnx_csu_dma_realize(DeviceState *dev, Error **errp) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(dev); + unsigned int i =3D 0; + + memory_region_init_io(&s->iomem, OBJECT(dev), &xlnx_csu_dma_ops, s, + TYPE_XLNX_CSU_DMA, XLNX_CSU_DMA_REGS_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq); + + for (i =3D 0; i < ARRAY_SIZE(xlnx_csu_dma_regs_info); i++) { + RegisterInfo *r =3D &s->regs_info[xlnx_csu_dma_regs_info[i].addr /= 4]; + r->data =3D (uint8_t *)&s->regs[xlnx_csu_dma_regs_info[i].addr / 4= ]; + r->data_size =3D sizeof(uint32_t); + r->access =3D (const RegisterAccessInfo *)&xlnx_csu_dma_regs_info[= i]; + r->opaque =3D s; + } + + if (s->dma_mr) { + s->dma_as =3D g_malloc0(sizeof(AddressSpace)); + address_space_init(s->dma_as, s->dma_mr, NULL); + } else { + s->dma_as =3D &address_space_memory; + } +} + +static void xlnx_csu_dma_init(Object *obj) +{ + XlnxCSUDMA *s =3D XLNX_CSU_DMA(obj); + + object_property_add_link(obj, "stream-connected-dma", TYPE_STREAM_SINK, + (Object **)&s->tx, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + object_property_add_link(obj, "xlnx-csu-dma-mr", TYPE_MEMORY_REGION, + (Object **)&s->dma_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); +} + +static const VMStateDescription vmstate_xlnx_csu_dma =3D { + .name =3D TYPE_XLNX_CSU_DMA, + .version_id =3D 0, + .minimum_version_id =3D 0, + .minimum_version_id_old =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxCSUDMA, XLNX_CSU_DMA_REGS_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + StreamSinkClass *ssc =3D STREAM_SINK_CLASS(klass); + + dc->reset =3D xlnx_csu_dma_reset; + dc->realize =3D xlnx_csu_dma_realize; + dc->vmsd =3D &vmstate_xlnx_csu_dma; + + ssc->push =3D ((StreamSinkClass *)data)->push; + ssc->can_push =3D ((StreamSinkClass *)data)->can_push; +} + +static StreamSinkClass xlnx_csu_dma_stream_class =3D { + .push =3D xlnx_csu_dma_stream_push, + .can_push =3D xlnx_csu_dma_stream_can_push, +}; + +static const TypeInfo xlnx_csu_dma_info =3D { + .name =3D TYPE_XLNX_CSU_DMA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxCSUDMA), + .class_init =3D xlnx_csu_dma_class_init, + .class_data =3D &xlnx_csu_dma_stream_class, + .instance_init =3D xlnx_csu_dma_init, + .interfaces =3D (InterfaceInfo[]) { + { TYPE_STREAM_SINK }, + { } + } +}; + +static void xlnx_csu_dma_register_types(void) +{ + type_register_static(&xlnx_csu_dma_info); +} + +type_init(xlnx_csu_dma_register_types) diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig index 5d6be1a..98fbb1b 100644 --- a/hw/dma/Kconfig +++ b/hw/dma/Kconfig @@ -26,3 +26,7 @@ config STP2000 =20 config SIFIVE_PDMA bool + +config XLNX_CSU_DMA + bool + select REGISTER diff --git a/hw/dma/meson.build b/hw/dma/meson.build index 47b4a7c..5c78a4e 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -14,3 +14,4 @@ softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_= dma.c', 'soc_dma.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c')) +softmmu_ss.add(when: 'CONFIG_XLNX_CSU_DMA', if_true: files('xlnx_csu_dma.c= ')) --=20 2.7.4 From nobody Sat May 18 14:01:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[44.242.66.180]) by smtp.gmail.com with ESMTPSA id y11sm785418ejd.72.2021.02.10.02.10.27 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Feb 2021 02:10:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=BZ8g2ECT89Ko7kszhPtszjRG/LCVRqOzQivisaMoOVg=; b=AY8fBZ/kRk5dyAqbeyd7jpL50Ksah+9NO2pkFawF+qhugxgztBk1OflT5RG+cGsdGL zYo6AZvWGGHKydSVtvTDq83ySJf5NW8FRsVyS3R2BNWncMdqJH3kKGTvxYi5Fn28wc8K 8gda56ecF19v8ZwMjsvKdl/qlXxJDLURKVtUczWOzYx3yaXQV25b5kheeaAx0kbK9eRi 1csK5pt3pGbLcL5hphMrHRxeaOb7DraDOTaXfMG7a5EoYHUw9uTe9Y6ioyj5V93wKqYA ElnK9zRptPQN3Ck+8MHKKeNHQNdcQZOsbsQCYP6EjzNf3TuCHjg3/6rN+aDkZ2vjKFBE 4+EA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BZ8g2ECT89Ko7kszhPtszjRG/LCVRqOzQivisaMoOVg=; b=UnSpF702BFjhiPAeUxTxuvgJp8a0EbjysLQDzbmZKCugDGgNT4dgfU//7LSl3KEimT YEmZCbSecg7DsAkCHcDVq4Kv0ot1CpqE2YJN8dzucovZv1aAb494Cwv7m+hyplKH5Ul4 km/Y3rPnIGDQMsSigVfgTMUhxmhEIqSGTeI3IM+fb4OF/DA8pMPppBDBBwqb0RBb6cWf 01MrU4EjCtti7P/GnrcWVaAuyMNO3TO6coqUxBFGO/zxdwdZpDAd2RAFmoKF5yrDVaWk /rF6CRY6ING8oQv2us9JRNvvBTfbESMyKZFJNvSQoN9/PDDKgwlGUZcctJSdnOoLWcZV LiUQ== X-Gm-Message-State: AOAM53022HOmicjMmAJGlwQYQ6tqQHaraq7T9Z+wqFO72zqZ7bWWiW+e I7NtnrKpGPQ4Lgv/YRgIZWU= X-Google-Smtp-Source: ABdhPJzGIGaYiAt4uPdCyMoYDwPDAhxLO/t80RB8dWbzTiLHyV1g8BzaNngSB+92TKQnS2ehpgOHZQ== X-Received: by 2002:a17:907:7346:: with SMTP id dq6mr2166883ejc.230.1612951832057; Wed, 10 Feb 2021 02:10:32 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v3 2/5] hw/arm: xlnx-zynqmp: Clean up coding convention issues Date: Wed, 10 Feb 2021 18:10:10 +0800 Message-Id: <1612951813-50542-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> References: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::633; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng There are some coding convention warnings in xlnx-zynqmp.c and xlnx-zynqmp.h, as reported by: $ ./scripts/checkpatch.pl include/hw/arm/xlnx-zynqmp.h $ ./scripts/checkpatch.pl hw/arm/xlnx-zynqmp.c Let's clean them up. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- Changes in v3: - new patch: xlnx-zynqmp: Clean up coding convention issues include/hw/arm/xlnx-zynqmp.h | 3 ++- hw/arm/xlnx-zynqmp.c | 11 +++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 6f45387..be15cc8 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -60,7 +60,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) =20 #define XLNX_ZYNQMP_GIC_REGIONS 6 =20 -/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k off= sets +/* + * ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k off= sets * and under-decodes the 64k region. This mirrors the 4k regions to every = 4k * aligned address in the 64k region. To implement each GIC region needs a * number of memory region aliases. diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 8818472..76b94a5 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -301,11 +301,13 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Err= or **errp) =20 ram_size =3D memory_region_size(s->ddr_ram); =20 - /* Create the DDR Memory Regions. User friendly checks should happen at + /* + * Create the DDR Memory Regions. User friendly checks should happen at * the board level */ if (ram_size > XLNX_ZYNQMP_MAX_LOW_RAM_SIZE) { - /* The RAM size is above the maximum available for the low DDR. + /* + * The RAM size is above the maximum available for the low DDR. * Create the high DDR memory region as well. */ assert(ram_size <=3D XLNX_ZYNQMP_MAX_RAM_SIZE); @@ -351,7 +353,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) =20 qdev_realize(DEVICE(&s->apu_cluster), NULL, &error_fatal); =20 - /* Realize APUs before realizing the GIC. KVM requires this. */ + /* Realize APUs before realizing the GIC. KVM requires this. */ for (i =3D 0; i < num_apus; i++) { const char *name; =20 @@ -526,7 +528,8 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) SysBusDevice *sbd =3D SYS_BUS_DEVICE(&s->sdhci[i]); Object *sdhci =3D OBJECT(&s->sdhci[i]); =20 - /* Compatible with: + /* + * Compatible with: * - SD Host Controller Specification Version 3.00 * - SDIO Specification Version 3.0 * - eMMC Specification Version 4.51 --=20 2.7.4 From nobody Sat May 18 14:01:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612951989; cv=none; d=zohomail.com; s=zohoarc; b=cEfbxACAFvYyCPZB0u9OJrwXnwY9GywuOn0QLGyQosv+DseITKK5u6kKFhDjcoCfUjpp6ge2yR83mDmAbbEN+aeJR2DpL2Nb6S0Jk+ptLNsJpDwEasS2cyyhZuSvhBFeomDQjJgEeYJQdE9onIgT69Pw4XWk1bokk1WDN38K8xY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612951989; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=JBkF+md++JxbgPCPBt1zkTEigdVgs8bJYJpVeVVJpDc=; b=dWmc0rHhTyh0pqFKY3xenLQi2AO87gqmVSSeHizECvq2ncqQ5x2zAL3+y7tBfvWO/57+RO3sDNi8X8RfBcYR0wFl0jdRtDpu0XNgT7gIagOx51DTWtHO+W2U15Z4YUJUhjXVJ00d7HTuRA1On1YfUlXn7yLlA4u5E+WHfHO4V3c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612951989434630.830589477829; Wed, 10 Feb 2021 02:13:09 -0800 (PST) Received: from localhost ([::1]:49882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l9mUe-0002Nr-Aw for importer@patchew.org; Wed, 10 Feb 2021 05:13:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37204) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l9mSI-0000CX-Fr; Wed, 10 Feb 2021 05:10:42 -0500 Received: from mail-ed1-x52b.google.com ([2a00:1450:4864:20::52b]:42200) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l9mSF-00032i-NZ; Wed, 10 Feb 2021 05:10:42 -0500 Received: by mail-ed1-x52b.google.com with SMTP id z22so2201153edb.9; Wed, 10 Feb 2021 02:10:37 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. 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Iglesias" , Peter Maydell Subject: [PATCH v3 3/5] hw/arm: xlnx-zynqmp: Add XLNX CSU DMA module Date: Wed, 10 Feb 2021 18:10:11 +0800 Message-Id: <1612951813-50542-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> References: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52b; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng Insert XLNX CSU DMA module to ZynqMP SoC, and connent the stream link of GQSPI to CSU DMA. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- Changes in v3: - new patch: xlnx-zynqmp: Add XLNX CSU DMA module include/hw/arm/xlnx-zynqmp.h | 2 ++ hw/arm/xlnx-zynqmp.c | 14 ++++++++++++++ hw/arm/Kconfig | 1 + 3 files changed, 17 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index be15cc8..d387c85 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -35,6 +35,7 @@ #include "target/arm/cpu.h" #include "qom/object.h" #include "net/can_emu.h" +#include "hw/dma/xlnx_csu_dma.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -108,6 +109,7 @@ struct XlnxZynqMPState { XlnxZynqMPRTC rtc; XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; + XlnxCSUDMA csu_dma; =20 char *boot_cpu; ARMCPU *boot_cpu_ptr; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 76b94a5..ed34692 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -63,6 +63,9 @@ #define RTC_ADDR 0xffa60000 #define RTC_IRQ 26 =20 +#define CSU_DMA_ADDR 0xff0f0800 +#define CSU_DMA_IRQ 15 + #define SDHCI_CAPABILITIES 0x280737ec6481 /* Datasheet: UG1085 (v1.7) */ =20 static const uint64_t gem_addr[XLNX_ZYNQMP_NUM_GEMS] =3D { @@ -284,6 +287,8 @@ static void xlnx_zynqmp_init(Object *obj) for (i =3D 0; i < XLNX_ZYNQMP_NUM_ADMA_CH; i++) { object_initialize_child(obj, "adma[*]", &s->adma[i], TYPE_XLNX_ZDM= A); } + + object_initialize_child(obj, "csu-dma", &s->csu_dma, TYPE_XLNX_CSU_DMA= ); } =20 static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) @@ -643,6 +648,15 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->adma[i]), 0, gic_spi[adma_ch_intr[i]]); } + + if (!sysbus_realize(SYS_BUS_DEVICE(&s->csu_dma), errp)) { + return; + } + + sysbus_mmio_map(SYS_BUS_DEVICE(&s->csu_dma), 0, CSU_DMA_ADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->csu_dma), 0, gic_spi[CSU_DMA_IRQ= ]); + object_property_set_link(OBJECT(&s->qspi), "stream-connected-dma", + OBJECT(&s->csu_dma), errp); } =20 static Property xlnx_zynqmp_props[] =3D { diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index be017b9..0c0384c 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -353,6 +353,7 @@ config XLNX_ZYNQMP_ARM select SSI_M25P80 select XILINX_AXI select XILINX_SPIPS + select XLNX_CSU_DMA select XLNX_ZYNQMP select XLNX_ZDMA =20 --=20 2.7.4 From nobody Sat May 18 14:01:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612952042; cv=none; d=zohomail.com; s=zohoarc; b=PVduPhb4MiNV8g88q+zFp25ick438X3NNywBDjigwSMWssSM4vfYOCzTEh0Q4c7Ur/byYSvw8GYMyGj+omo/7YIvuj12n1zVb9Fq2ZCdl6aahIZddTt9lTHNtWY2TUImAyz4c8dLgZgZ8HDyiOYua3Wk1v2UVCuagwVf1giF7y8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612952042; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vlegheEyqXl7+NwMvyJSahCC2mYTto9ZEvw05hdEWZ4=; b=ANQT2f6Csc+cgQFSDU1W4p4LPMl3IXFiRtd76+rh8QoN7QQTXFawhHAsz9CnBhXrGcU6c1T2DqHsg2Xjugo34Cfjjv0FWT2/Mcb8WJxqjHnGxJIBoE7MS1GEQTDSY6g4/Lo/K3hOoOo4LlqYV4bLc+kuvUGMbpkf1hy/cZIxMCM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612952041942910.5176962332238; Wed, 10 Feb 2021 02:14:01 -0800 (PST) Received: from localhost ([::1]:51716 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l9mVT-000377-He for importer@patchew.org; Wed, 10 Feb 2021 05:13:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l9mSL-0000Gu-UE; Wed, 10 Feb 2021 05:10:47 -0500 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]:42592) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l9mSJ-00034K-Sh; Wed, 10 Feb 2021 05:10:45 -0500 Received: by mail-ej1-x62c.google.com with SMTP id l25so3045834eja.9; Wed, 10 Feb 2021 02:10:43 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. [44.242.66.180]) by smtp.gmail.com with ESMTPSA id y11sm785418ejd.72.2021.02.10.02.10.37 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 10 Feb 2021 02:10:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vlegheEyqXl7+NwMvyJSahCC2mYTto9ZEvw05hdEWZ4=; b=Osik7mT9ZKNDairkQpWfkPh6La1CZhGlRtjEk7qRjQ+mzdGOhGLVsi5RT4U3gFSgEb LjdQrDEM0oPhNli7T0IgzNYf6uIG5vbi5vjIsaR/99+mTzubSKPlQnwLdkUllsVd9nNo 8QKHtliU4dJJ4o5VLoQ1rDo2lYnApf+vBDf9KLIPwep8FXZXg5Ugpf0MMin/hNX3x/6S vhgF2caiPpB0jT4fel6QraVnTv/Wd3xypYXGhV4Og157h12CYbiWartIzy8wVji0yTzz BK1Bk8kp9TrBhg7s8l4TgZeNrgHtbERb+hbsukIpmXkrmul/EBJ21gU7eUwazSekijH4 erWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vlegheEyqXl7+NwMvyJSahCC2mYTto9ZEvw05hdEWZ4=; b=DIKilaMeEyiTfWjODvH1KAHvg1WZ1CPw36PMe/cQC9Bx1Bed5AVY16M/WvGDg9cpIX FTLTK+Y8GnS3zrLuvEwGSntyYu53hz+DuQXQVgA9eAyc9h0zgi1hUB+gq1iQRR/hnjok 9xuTEShHx4ZlRRAwlYBwJJ+WkeZXjNq9MDj5MgC04wfcjtRBE1ZQoxAj+7CYGvOn6HTE wR2lvlS+9fx07gJGA9rvqVXY7ri9HRxRZWsmI3QPkj1MlN29huZLOk0SN81eC1jATZd9 sZdTNRJVh7v3r9tEILqpXcCuKA6dGz8BiVPsMStkLGDNNUrv886ftn3cDXWLr5lYi5Nd MfZQ== X-Gm-Message-State: AOAM5305ewUqlCeZLtAn8zq0S5U9nflIccOaosblL81EoDGTsp7jLtl9 npoDLUf1lYEP/Lr1DXBlhlE= X-Google-Smtp-Source: ABdhPJzatyB7ecRbeT4Gsoy/wNxa8o+0adcFrQSaBy8TLly0LMKgOnAAg/cwwz6QH70R2tMh4mbGgQ== X-Received: by 2002:a17:906:2993:: with SMTP id x19mr2079622eje.409.1612951842226; Wed, 10 Feb 2021 02:10:42 -0800 (PST) From: Bin Meng To: Alistair Francis , "Edgar E . Iglesias" , Peter Maydell Subject: [PATCH v3 4/5] hw/ssi: xilinx_spips: Clean up coding convention issues Date: Wed, 10 Feb 2021 18:10:12 +0800 Message-Id: <1612951813-50542-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> References: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::62c; envelope-from=bmeng.cn@gmail.com; helo=mail-ej1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Xuzhou Cheng There are some coding convention warnings in xilinx_spips.c, as reported by: $ ./scripts/checkpatch.pl hw/ssi/xilinx_spips.c Let's clean them up. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Edgar E. Iglesias --- (no changes since v1) hw/ssi/xilinx_spips.c | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index a897034..8a0cc22 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -176,7 +176,8 @@ FIELD(GQSPI_FIFO_CTRL, GENERIC_FIFO_RESET, 0, 1) #define R_GQSPI_GFIFO_THRESH (0x150 / 4) #define R_GQSPI_DATA_STS (0x15c / 4) -/* We use the snapshot register to hold the core state for the currently +/* + * We use the snapshot register to hold the core state for the currently * or most recently executed command. So the generic fifo format is defined * for the snapshot register */ @@ -424,7 +425,8 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) xlnx_zynqmp_qspips_update_ixr(s); } =20 -/* N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) +/* + * N way (num) in place bit striper. Lay out row wise bits (MSB to LSB) * column wise (from element 0 to N-1). num is the length of x, and dir * reverses the direction of the transform. Best illustrated by example: * Each digit in the below array is a single bit (num =3D=3D 3): @@ -637,8 +639,10 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) tx_rx[i] =3D tx; } } else { - /* Extract a dummy byte and generate dummy cycles according to= the - * link state */ + /* + * Extract a dummy byte and generate dummy cycles according to= the + * link state + */ tx =3D fifo8_pop(&s->tx_fifo); dummy_cycles =3D 8 / s->link_state; } @@ -721,8 +725,9 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) } break; case (SNOOP_ADDR): - /* Address has been transmitted, transmit dummy cycles now if - * needed */ + /* + * Address has been transmitted, transmit dummy cycles now if = needed + */ if (s->cmd_dummies < 0) { s->snoop_state =3D SNOOP_NONE; } else { @@ -876,7 +881,7 @@ static void xlnx_zynqmp_qspips_notify(void *opaque) } =20 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, - unsigned size) + unsigned size) { XilinxSPIPS *s =3D opaque; uint32_t mask =3D ~0; @@ -970,7 +975,7 @@ static uint64_t xlnx_zynqmp_qspips_read(void *opaque, } =20 static void xilinx_spips_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) + uint64_t value, unsigned size) { int mask =3D ~0; XilinxSPIPS *s =3D opaque; @@ -1072,7 +1077,7 @@ static void xilinx_qspips_write(void *opaque, hwaddr = addr, } =20 static void xlnx_zynqmp_qspips_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) + uint64_t value, unsigned size) { XlnxZynqMPQSPIPS *s =3D XLNX_ZYNQMP_QSPIPS(opaque); uint32_t reg =3D addr / 4; --=20 2.7.4 From nobody Sat May 18 14:01:38 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1612952130; cv=none; d=zohomail.com; s=zohoarc; b=RXfkffnfw8JNz8h1nVpe+cQoOP6Bec3rrh+9841YMWhyQ68yNdFMHb16EjY81HOCtVoAZpREdmbUmkuTkpU8G7rLwRUBmYtl0K3xL8QHyEUWwrTC8q578ua8Y98lYcQ3skn9VXHNIF81yqQnXs49dP4v6pCjLHT4+xpZTj4GEKM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1612952130; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=HgooUYReWht3R5owWvQqwU/EQ/eHh1JGCNZbl+Tx3t8=; b=OOzgdJRVg746Xlc1bXKE/E3kd1qH95JXAefmbDHKK+CAvOaGigssZI/83YhnxJ4+GKR/vKHkU6dvuk/YxItlfxzLtar1eYbFP81A35N7eImfh8zthol8m3cOWLYX70bkoeDPmwQXh//fEi2T97xejRHPaR1kd1ISh34KrD5Wcbk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1612952130332430.97865779369897; Wed, 10 Feb 2021 02:15:30 -0800 (PST) Received: from localhost ([::1]:57478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1l9mWv-0005Qb-95 for importer@patchew.org; Wed, 10 Feb 2021 05:15:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:37274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1l9mSS-0000KR-6z; Wed, 10 Feb 2021 05:10:53 -0500 Received: from mail-ed1-x529.google.com ([2a00:1450:4864:20::529]:42200) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1l9mSP-00036S-3v; Wed, 10 Feb 2021 05:10:51 -0500 Received: by mail-ed1-x529.google.com with SMTP id z22so2202024edb.9; Wed, 10 Feb 2021 02:10:48 -0800 (PST) Received: from pek-vx-bsp2.wrs.com (ec2-44-242-66-180.us-west-2.compute.amazonaws.com. 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Iglesias" , Peter Maydell Subject: [PATCH v3 5/5] hw/ssi: xilinx_spips: Remove DMA related code from zynqmp_qspips Date: Wed, 10 Feb 2021 18:10:13 +0800 Message-Id: <1612951813-50542-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> References: <1612951813-50542-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::529; envelope-from=bmeng.cn@gmail.com; helo=mail-ed1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Francisco Iglesias , qemu-arm@nongnu.org, qemu-devel@nongnu.org, Xuzhou Cheng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Xuzhou Cheng Now that the XLNX CSU DMA model is implemented, the existing codes in the ZynqMP QSPIS are useless and should be removed. Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng --- Changes in v3: - new patch: xilinx_spips: Remove DMA related code from zynqmp_qspips hw/ssi/xilinx_spips.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 8a0cc22..1e9dba2 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -195,13 +195,6 @@ #define R_GQSPI_MOD_ID (0x1fc / 4) #define R_GQSPI_MOD_ID_RESET (0x10a0000) =20 -#define R_QSPIDMA_DST_CTRL (0x80c / 4) -#define R_QSPIDMA_DST_CTRL_RESET (0x803ffa00) -#define R_QSPIDMA_DST_I_MASK (0x820 / 4) -#define R_QSPIDMA_DST_I_MASK_RESET (0xfe) -#define R_QSPIDMA_DST_CTRL2 (0x824 / 4) -#define R_QSPIDMA_DST_CTRL2_RESET (0x081bfff8) - /* size of TXRX FIFOs */ #define RXFF_A (128) #define TXFF_A (128) @@ -417,9 +410,6 @@ static void xlnx_zynqmp_qspips_reset(DeviceState *d) s->regs[R_GQSPI_GPIO] =3D 1; s->regs[R_GQSPI_LPBK_DLY_ADJ] =3D R_GQSPI_LPBK_DLY_ADJ_RESET; s->regs[R_GQSPI_MOD_ID] =3D R_GQSPI_MOD_ID_RESET; - s->regs[R_QSPIDMA_DST_CTRL] =3D R_QSPIDMA_DST_CTRL_RESET; - s->regs[R_QSPIDMA_DST_I_MASK] =3D R_QSPIDMA_DST_I_MASK_RESET; - s->regs[R_QSPIDMA_DST_CTRL2] =3D R_QSPIDMA_DST_CTRL2_RESET; s->man_start_com_g =3D false; s->gqspi_irqline =3D 0; xlnx_zynqmp_qspips_update_ixr(s); --=20 2.7.4