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Mon, 08 Feb 2021 00:46:50 -0500 Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 07 Feb 2021 21:46:29 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 07 Feb 2021 21:46:28 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id B0C6914E6; Sun, 7 Feb 2021 23:46:28 -0600 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1612763193; x=1644299193; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=aDEyM1fv9oRr0Su6HcOS/2lGOJ5PWbgNGrfSnVEqwUo=; b=b7CLToOC4LISoQ9InKQmp8C2LgrNVpmKjMGVd+egNrRQPLun7vcixD7L 73OoufxMHB8ylgscPo9b3zl/ZQ0YPnn5e9vS8Kz0+KXsKjgLtTlUZm9DH mQsxhGYo0VV/t9g7sbQUxp1aj+RJlrx/ajKhAf14v1O9kzy1/q5l+J2j5 s=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH v8 03/35] Hexagon (include/elf.h) ELF machine definition Date: Sun, 7 Feb 2021 23:45:53 -0600 Message-Id: <1612763186-18161-4-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1612763186-18161-1-git-send-email-tsimpson@quicinc.com> References: <1612763186-18161-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" Define EM_HEXAGON 164 Signed-off-by: Taylor Simpson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- include/elf.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/elf.h b/include/elf.h index 7a418ee..f4fa3c1 100644 --- a/include/elf.h +++ b/include/elf.h @@ -176,6 +176,7 @@ typedef struct mips_elf_abiflags_v0 { =20 #define EM_UNICORE32 110 /* UniCore32 */ =20 +#define EM_HEXAGON 164 /* Qualcomm Hexagon */ #define EM_RX 173 /* Renesas RX family */ =20 #define EM_RISCV 243 /* RISC-V */ --=20 2.7.4