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charset="utf-8" Using the cfg.use_non_secure bitfield and the MMU access type, we can deter= mine if the access should be secure or not. Signed-off-by: Joe Komlodi Reviewed-by: Edgar E. Iglesias Tested-by: Edgar E. Iglesias --- target/microblaze/cpu.c | 2 +- target/microblaze/cpu.h | 3 ++- target/microblaze/helper.c | 26 +++++++++++++++++++++++--- 3 files changed, 26 insertions(+), 5 deletions(-) diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index accfb23..d5e8bfe 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -375,7 +375,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) cc->tlb_fill =3D mb_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed =3D mb_cpu_transaction_failed; - cc->get_phys_page_debug =3D mb_cpu_get_phys_page_debug; + cc->get_phys_page_attrs_debug =3D mb_cpu_get_phys_page_attrs_debug; dc->vmsd =3D &vmstate_mb_cpu; #endif device_class_set_props(dc, mb_properties); diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 199cfb0..e4bba8a 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -361,7 +361,8 @@ void mb_cpu_do_unaligned_access(CPUState *cs, vaddr vad= dr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); void mb_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, + MemTxAttrs *attrs); int mb_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); =20 diff --git a/target/microblaze/helper.c b/target/microblaze/helper.c index cda14a1..20dbd67 100644 --- a/target/microblaze/helper.c +++ b/target/microblaze/helper.c @@ -46,6 +46,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int si= ze, =20 #else /* !CONFIG_USER_ONLY */ =20 +static bool mb_cpu_access_is_secure(MicroBlazeCPU *cpu, + MMUAccessType access_type) +{ + if (access_type =3D=3D MMU_INST_FETCH) { + return !cpu->ns_axi_ip; + } else { + return !cpu->ns_axi_dp; + } +} + bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -55,12 +65,16 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int s= ize, MicroBlazeMMULookup lu; unsigned int hit; int prot; + MemTxAttrs attrs =3D {}; + + attrs.secure =3D mb_cpu_access_is_secure(cpu, access_type); =20 if (mmu_idx =3D=3D MMU_NOMMU_IDX) { /* MMU disabled or not available. */ address &=3D TARGET_PAGE_MASK; prot =3D PAGE_BITS; - tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE= ); + tlb_set_page_with_attrs(cs, address, address, attrs, prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } =20 @@ -71,7 +85,8 @@ bool mb_cpu_tlb_fill(CPUState *cs, vaddr address, int siz= e, =20 qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=3D%d v=3D%x p=3D%x prot=3D= %x\n", mmu_idx, vaddr, paddr, lu.prot); - tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); + tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, lu.prot, mmu_idx, + TARGET_PAGE_SIZE); return true; } =20 @@ -230,7 +245,8 @@ void mb_cpu_do_interrupt(CPUState *cs) } } =20 -hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +hwaddr mb_cpu_get_phys_page_attrs_debug(CPUState *cs, vaddr addr, + MemTxAttrs *attrs) { MicroBlazeCPU *cpu =3D MICROBLAZE_CPU(cs); CPUMBState *env =3D &cpu->env; @@ -239,6 +255,10 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr = addr) int mmu_idx =3D cpu_mmu_index(env, false); unsigned int hit; =20 + /* Caller doesn't initialize */ + *attrs =3D (MemTxAttrs) {}; + attrs->secure =3D mb_cpu_access_is_secure(cpu, MMU_DATA_LOAD); + if (mmu_idx !=3D MMU_NOMMU_IDX) { hit =3D mmu_translate(cpu, &lu, addr, 0, 0); if (hit) { --=20 2.7.4