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Tue, 19 Jan 2021 22:30:42 -0500 Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 19 Jan 2021 19:29:28 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 19 Jan 2021 19:29:28 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 5AB4B2950; Tue, 19 Jan 2021 21:29:28 -0600 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1611113440; x=1642649440; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Btrcwx/fEjL+FfiFc0Xpyv8l8EAIDUHnxtH+WuDMpw4=; b=GtWq4H6W8s5ZHiY/s+B4i9lQVg/6Ccsit5auIv74/PcThVLoEt4aHwRz w0+25YiW3xNy5sW+/wRWQ9qYp8dTrK+TQiP3ggFVYw58ivYEzZM75HQFV wn6xj98RHV0s9UpzggLUeWHFkZy+dJOHpHJLtXpEkGmnaFuE2Ftc4kqi3 0=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH v7 33/35] Hexagon (tests/tcg/hexagon) TCG tests - floating point Date: Tue, 19 Jan 2021 21:29:06 -0600 Message-Id: <1611113349-24906-34-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611113349-24906-1-git-send-email-tsimpson@quicinc.com> References: <1611113349-24906-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, philmd@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) --- tests/tcg/hexagon/fpstuff.c | 370 ++++++++++++++++++++++++++++++++++= ++++ tests/tcg/hexagon/Makefile.target | 1 + 2 files changed, 371 insertions(+) create mode 100644 tests/tcg/hexagon/fpstuff.c diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c new file mode 100644 index 0000000..e4f1a0e --- /dev/null +++ b/tests/tcg/hexagon/fpstuff.c @@ -0,0 +1,370 @@ +/* + * Copyright(c) 2020-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * This test checks various FP operations performed on Hexagon + */ + +#include + +const int FPINVF_BIT =3D 1; /* Invalid */ +const int FPINVF =3D 1 << FPINVF_BIT; +const int FPDBZF_BIT =3D 2; /* Divide by zero */ +const int FPDBZF =3D 1 << FPDBZF_BIT; +const int FPOVFF_BIT =3D 3; /* Overflow */ +const int FPOVFF =3D 1 << FPOVFF_BIT; +const int FPUNFF_BIT =3D 4; /* Underflow */ +const int FPUNFF =3D 1 << FPUNFF_BIT; +const int FPINPF_BIT =3D 5; /* Inexact */ +const int FPINPF =3D 1 << FPINPF_BIT; + +const int SF_ZERO =3D 0x00000000; +const int SF_NaN =3D 0x7fc00000; +const int SF_NaN_special =3D 0x7f800001; +const int SF_ANY =3D 0x3f800000; +const int SF_HEX_NAN =3D 0xffffffff; + +const long long DF_NaN =3D 0x7ff8000000000000ULL; +const long long DF_ANY =3D 0x3f80000000000000ULL; +const long long DF_HEX_NAN =3D 0xffffffffffffffffULL; + +int err; + +#define CLEAR_FPSTATUS \ + "r2 =3D usr\n\t" \ + "r2 =3D clrbit(r2, #1)\n\t" \ + "r2 =3D clrbit(r2, #2)\n\t" \ + "r2 =3D clrbit(r2, #3)\n\t" \ + "r2 =3D clrbit(r2, #4)\n\t" \ + "r2 =3D clrbit(r2, #5)\n\t" \ + "usr =3D r2\n\t" + +static void check_fpstatus_bit(int usr, int expect, int flag, const char *= n) +{ + int bit =3D 1 << flag; + if ((usr & bit) !=3D (expect & bit)) { + printf("ERROR %s: usr =3D %d, expect =3D %d\n", n, + (usr >> flag) & 1, (expect >> flag) & 1); + err++; + } +} + +static void check_fpstatus(int usr, int expect) +{ + check_fpstatus_bit(usr, expect, FPINVF_BIT, "Invalid"); + check_fpstatus_bit(usr, expect, FPDBZF_BIT, "Div by zero"); + check_fpstatus_bit(usr, expect, FPOVFF_BIT, "Overflow"); + check_fpstatus_bit(usr, expect, FPUNFF_BIT, "Underflow"); + check_fpstatus_bit(usr, expect, FPINPF_BIT, "Inexact"); +} + +static void check32(int val, int expect) +{ + if (val !=3D expect) { + printf("ERROR: 0x%x !=3D 0x%x\n", val, expect); + err++; + } +} +static void check64(unsigned long long val, unsigned long long expect) +{ + if (val !=3D expect) { + printf("ERROR: 0x%llx !=3D 0x%llx\n", val, expect); + err++; + } +} + +static void check_compare_exception(void) +{ + int cmp; + int usr; + + /* Check that FP compares are quiet (don't raise any execptions) */ + asm (CLEAR_FPSTATUS + "p0 =3D sfcmp.eq(%2, %3)\n\t" + "%0 =3D p0\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "p0", "usr"); + check32(cmp, 0); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "p0 =3D sfcmp.gt(%2, %3)\n\t" + "%0 =3D p0\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "p0", "usr"); + check32(cmp, 0); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "p0 =3D sfcmp.ge(%2, %3)\n\t" + "%0 =3D p0\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "p0", "usr"); + check32(cmp, 0); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "p0 =3D dfcmp.eq(%2, %3)\n\t" + "%0 =3D p0\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "r2", "p0", "usr"); + check32(cmp, 0); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "p0 =3D dfcmp.gt(%2, %3)\n\t" + "%0 =3D p0\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "r2", "p0", "usr"); + check32(cmp, 0); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "p0 =3D dfcmp.ge(%2, %3)\n\t" + "%0 =3D p0\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "r2", "p0", "usr"); + check32(cmp, 0); + check_fpstatus(usr, 0); +} + +static void check_sfminmax(void) +{ + int minmax; + int usr; + + /* + * Execute sfmin/sfmax instructions with one operand as NaN + * Check that + * Result is the other operand + * Invalid bit in USR is not set + */ + asm (CLEAR_FPSTATUS + "%0 =3D sfmin(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check64(minmax, SF_ANY); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "%0 =3D sfmax(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check64(minmax, SF_ANY); + check_fpstatus(usr, 0); + + /* + * Execute sfmin/sfmax instructions with both operands NaN + * Check that + * Result is SF_HEX_NAN + * Invalid bit in USR is set + */ + asm (CLEAR_FPSTATUS + "%0 =3D sfmin(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_NaN) + : "r2", "usr"); + check64(minmax, SF_HEX_NAN); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "%0 =3D sfmax(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_NaN) + : "r2", "usr"); + check64(minmax, SF_HEX_NAN); + check_fpstatus(usr, 0); +} + +static void check_dfminmax(void) +{ + unsigned long long minmax; + int usr; + + /* + * Execute dfmin/dfmax instructions with one operand as NaN + * Check that + * Result is the other operand + * Invalid bit in USR is set + */ + asm (CLEAR_FPSTATUS + "%0 =3D dfmin(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "r2", "usr"); + check64(minmax, DF_ANY); + check_fpstatus(usr, FPINVF); + + asm (CLEAR_FPSTATUS + "%0 =3D dfmax(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "r2", "usr"); + check64(minmax, DF_ANY); + check_fpstatus(usr, FPINVF); + + /* + * Execute dfmin/dfmax instructions with both operands NaN + * Check that + * Result is DF_HEX_NAN + * Invalid bit in USR is set + */ + asm (CLEAR_FPSTATUS + "%0 =3D dfmin(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_NaN) + : "r2", "usr"); + check64(minmax, DF_HEX_NAN); + check_fpstatus(usr, FPINVF); + + asm (CLEAR_FPSTATUS + "%0 =3D dfmax(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_NaN) + : "r2", "usr"); + check64(minmax, DF_HEX_NAN); + check_fpstatus(usr, FPINVF); +} + +static void check_canonical_NaN(void) +{ + int sf_result; + unsigned long long df_result; + int usr; + + /* Check that each FP instruction properly returns SF_HEX_NAN/DF_HEX_N= AN */ + asm(CLEAR_FPSTATUS + "%0 =3D sfadd(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + asm(CLEAR_FPSTATUS + "%0 =3D sfsub(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + asm(CLEAR_FPSTATUS + "%0 =3D sfmpy(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + sf_result =3D SF_ZERO; + asm(CLEAR_FPSTATUS + "%0 +=3D sfmpy(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "+r"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + sf_result =3D SF_ZERO; + asm(CLEAR_FPSTATUS + "p0 =3D !cmp.eq(r0, r0)\n\t" + "%0 +=3D sfmpy(%2, %3, p0):scale\n\t" + "%1 =3D usr\n\t" + : "+r"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr", "p0"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + sf_result =3D SF_ZERO; + asm(CLEAR_FPSTATUS + "%0 -=3D sfmpy(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "+r"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + sf_result =3D SF_ZERO; + asm(CLEAR_FPSTATUS + "%0 +=3D sfmpy(%2, %3):lib\n\t" + "%1 =3D usr\n\t" + : "+r"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + sf_result =3D SF_ZERO; + asm(CLEAR_FPSTATUS + "%0 -=3D sfmpy(%2, %3):lib\n\t" + "%1 =3D usr\n\t" + : "+r"(sf_result), "=3Dr"(usr) : "r"(SF_NaN), "r"(SF_ANY) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_df2sf(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(sf_result), "=3Dr"(usr) : "r"(DF_NaN) + : "r2", "usr"); + check32(sf_result, SF_HEX_NAN); + check_fpstatus(usr, 0); + + asm(CLEAR_FPSTATUS + "%0 =3D dfadd(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(df_result), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "r2", "usr"); + check64(df_result, DF_HEX_NAN); + check_fpstatus(usr, 0); + + asm(CLEAR_FPSTATUS + "%0 =3D dfsub(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(df_result), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "r2", "usr"); + check64(df_result, DF_HEX_NAN); + check_fpstatus(usr, 0); + + asm(CLEAR_FPSTATUS + "%0 =3D convert_sf2df(%2)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(df_result), "=3Dr"(usr) : "r"(SF_NaN) + : "r2", "usr"); + check64(df_result, DF_HEX_NAN); + check_fpstatus(usr, 0); +} + +int main() +{ + check_compare_exception(); + check_sfminmax(); + check_dfminmax(); + check_canonical_NaN(); + + puts(err ? "FAIL" : "PASS"); + return err ? 1 : 0; +} diff --git a/tests/tcg/hexagon/Makefile.target b/tests/tcg/hexagon/Makefile= .target index a54e3c7..616af69 100644 --- a/tests/tcg/hexagon/Makefile.target +++ b/tests/tcg/hexagon/Makefile.target @@ -41,5 +41,6 @@ HEX_TESTS +=3D preg_alias HEX_TESTS +=3D dual_stores HEX_TESTS +=3D mem_noshuf HEX_TESTS +=3D atomics +HEX_TESTS +=3D fpstuff =20 TESTS +=3D $(HEX_TESTS) --=20 2.7.4