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Tue, 19 Jan 2021 22:29:58 -0500 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 19 Jan 2021 19:29:26 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 19 Jan 2021 19:29:25 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 75CB02C37; Tue, 19 Jan 2021 21:29:25 -0600 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1611113396; x=1642649396; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=T+Qy8KwLgyYw1BBXJsPHtnBszZU2+Dlz5YLgDrsgwFA=; b=GlJMFux5HpAUYJHJZp2AVU2NrhDtQa5HQDAFJSZtxPHzQkozRCEufCQT VlQ0FMzANyieZyWcPVMoBYfbNT6Fp77rGSn3Lniy/r4Ry7SYekF6AH67M 7yIE3Ll88jTepMaXAyRuJEkRIy300sBdxyGe+DlkpVujRFwInbww/H1Gw s=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH v7 15/35] Hexagon (target/hexagon/arch.[ch]) utility functions Date: Tue, 19 Jan 2021 21:28:48 -0600 Message-Id: <1611113349-24906-16-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611113349-24906-1-git-send-email-tsimpson@quicinc.com> References: <1611113349-24906-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, philmd@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Signed-off-by: Taylor Simpson --- target/hexagon/arch.h | 35 ++++++ target/hexagon/arch.c | 294 ++++++++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 329 insertions(+) create mode 100644 target/hexagon/arch.h create mode 100644 target/hexagon/arch.c diff --git a/target/hexagon/arch.h b/target/hexagon/arch.h new file mode 100644 index 0000000..a8374a3 --- /dev/null +++ b/target/hexagon/arch.h @@ -0,0 +1,35 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_ARCH_H +#define HEXAGON_ARCH_H + +#include "qemu/osdep.h" +#include "qemu/int128.h" + +extern uint64_t interleave(uint32_t odd, uint32_t even); +extern uint64_t deinterleave(uint64_t src); +extern uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c); +extern int32_t conv_round(int32_t a, int n); +extern void arch_fpop_start(CPUHexagonState *env); +extern void arch_fpop_end(CPUHexagonState *env); +extern int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, + int *adjust, float_status *fp_status); +extern int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, + float_status *fp_status); + +#endif diff --git a/target/hexagon/arch.c b/target/hexagon/arch.c new file mode 100644 index 0000000..c59cad5 --- /dev/null +++ b/target/hexagon/arch.c @@ -0,0 +1,294 @@ +/* + * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "fpu/softfloat.h" +#include "cpu.h" +#include "fma_emu.h" +#include "arch.h" +#include "macros.h" + +#define SF_BIAS 127 +#define SF_MAXEXP 254 +#define SF_MANTBITS 23 +#define float32_nan make_float32(0xffffffff) + +#define BITS_MASK_8 0x5555555555555555ULL +#define PAIR_MASK_8 0x3333333333333333ULL +#define NYBL_MASK_8 0x0f0f0f0f0f0f0f0fULL +#define BYTE_MASK_8 0x00ff00ff00ff00ffULL +#define HALF_MASK_8 0x0000ffff0000ffffULL +#define WORD_MASK_8 0x00000000ffffffffULL + +uint64_t interleave(uint32_t odd, uint32_t even) +{ + /* Convert to long long */ + uint64_t myodd =3D odd; + uint64_t myeven =3D even; + /* First, spread bits out */ + myodd =3D (myodd | (myodd << 16)) & HALF_MASK_8; + myeven =3D (myeven | (myeven << 16)) & HALF_MASK_8; + myodd =3D (myodd | (myodd << 8)) & BYTE_MASK_8; + myeven =3D (myeven | (myeven << 8)) & BYTE_MASK_8; + myodd =3D (myodd | (myodd << 4)) & NYBL_MASK_8; + myeven =3D (myeven | (myeven << 4)) & NYBL_MASK_8; + myodd =3D (myodd | (myodd << 2)) & PAIR_MASK_8; + myeven =3D (myeven | (myeven << 2)) & PAIR_MASK_8; + myodd =3D (myodd | (myodd << 1)) & BITS_MASK_8; + myeven =3D (myeven | (myeven << 1)) & BITS_MASK_8; + /* Now OR together */ + return myeven | (myodd << 1); +} + +uint64_t deinterleave(uint64_t src) +{ + /* Get odd and even bits */ + uint64_t myodd =3D ((src >> 1) & BITS_MASK_8); + uint64_t myeven =3D (src & BITS_MASK_8); + + /* Unspread bits */ + myeven =3D (myeven | (myeven >> 1)) & PAIR_MASK_8; + myodd =3D (myodd | (myodd >> 1)) & PAIR_MASK_8; + myeven =3D (myeven | (myeven >> 2)) & NYBL_MASK_8; + myodd =3D (myodd | (myodd >> 2)) & NYBL_MASK_8; + myeven =3D (myeven | (myeven >> 4)) & BYTE_MASK_8; + myodd =3D (myodd | (myodd >> 4)) & BYTE_MASK_8; + myeven =3D (myeven | (myeven >> 8)) & HALF_MASK_8; + myodd =3D (myodd | (myodd >> 8)) & HALF_MASK_8; + myeven =3D (myeven | (myeven >> 16)) & WORD_MASK_8; + myodd =3D (myodd | (myodd >> 16)) & WORD_MASK_8; + + /* Return odd bits in upper half */ + return myeven | (myodd << 32); +} + +uint32_t carry_from_add64(uint64_t a, uint64_t b, uint32_t c) +{ + uint64_t tmpa, tmpb, tmpc; + tmpa =3D fGETUWORD(0, a); + tmpb =3D fGETUWORD(0, b); + tmpc =3D tmpa + tmpb + c; + tmpa =3D fGETUWORD(1, a); + tmpb =3D fGETUWORD(1, b); + tmpc =3D tmpa + tmpb + fGETUWORD(1, tmpc); + tmpc =3D fGETUWORD(1, tmpc); + return tmpc; +} + +int32_t conv_round(int32_t a, int n) +{ + int64_t val; + + if (n =3D=3D 0) { + val =3D a; + } else if ((a & ((1 << (n - 1)) - 1)) =3D=3D 0) { /* N-1..0 all zer= o? */ + /* Add LSB from int part */ + val =3D ((fSE32_64(a)) + (int64_t) (((uint32_t) ((1 << n) & a)) >>= 1)); + } else { + val =3D ((fSE32_64(a)) + (1 << (n - 1))); + } + + val =3D val >> n; + return (int32_t)val; +} + +/* Floating Point Stuff */ + +static const int softfloat_roundingmodes[] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_down, + float_round_up, +}; + +void arch_fpop_start(CPUHexagonState *env) +{ + set_float_exception_flags(0, &env->fp_status); + set_float_rounding_mode( + softfloat_roundingmodes[fREAD_REG_FIELD(USR, USR_FPRND)], + &env->fp_status); +} + +#define RAISE_FP_EXCEPTION \ + do {} while (0) /* Not modelled in qemu user mode */ + +#define SOFTFLOAT_TEST_FLAG(FLAG, MYF, MYE) \ + do { \ + if (flags & FLAG) { \ + if (GET_USR_FIELD(USR_##MYF) =3D=3D 0) { \ + SET_USR_FIELD(USR_##MYF, 1); \ + if (GET_USR_FIELD(USR_##MYE)) { \ + RAISE_FP_EXCEPTION; \ + } \ + } \ + } \ + } while (0) + +void arch_fpop_end(CPUHexagonState *env) +{ + int flags =3D get_float_exception_flags(&env->fp_status); + if (flags !=3D 0) { + SOFTFLOAT_TEST_FLAG(float_flag_inexact, FPINPF, FPINPE); + SOFTFLOAT_TEST_FLAG(float_flag_divbyzero, FPDBZF, FPDBZE); + SOFTFLOAT_TEST_FLAG(float_flag_invalid, FPINVF, FPINVE); + SOFTFLOAT_TEST_FLAG(float_flag_overflow, FPOVFF, FPOVFE); + SOFTFLOAT_TEST_FLAG(float_flag_underflow, FPUNFF, FPUNFE); + } +} + +static float32 float32_mul_pow2(float32 a, uint32_t p, float_status *fp_st= atus) +{ + float32 b =3D make_float32((SF_BIAS + p) << SF_MANTBITS); + return float32_mul(a, b, fp_status); +} + +int arch_sf_recip_common(float32 *Rs, float32 *Rt, float32 *Rd, int *adjus= t, + float_status *fp_status) +{ + int n_exp; + int d_exp; + int ret =3D 0; + float32 RsV, RtV, RdV; + int PeV =3D 0; + RsV =3D *Rs; + RtV =3D *Rt; + if (float32_is_any_nan(RsV) && float32_is_any_nan(RtV)) { + if (extract32(RsV & RtV, 22, 1) =3D=3D 0) { + float_raise(float_flag_invalid, fp_status); + } + RdV =3D RsV =3D RtV =3D float32_nan; + } else if (float32_is_any_nan(RsV)) { + if (extract32(RsV, 22, 1) =3D=3D 0) { + float_raise(float_flag_invalid, fp_status); + } + RdV =3D RsV =3D RtV =3D float32_nan; + } else if (float32_is_any_nan(RtV)) { + /* or put NaN in num/den fixup? */ + if (extract32(RtV, 22, 1) =3D=3D 0) { + float_raise(float_flag_invalid, fp_status); + } + RdV =3D RsV =3D RtV =3D float32_nan; + } else if (float32_is_infinity(RsV) && float32_is_infinity(RtV)) { + /* or put Inf in num fixup? */ + RdV =3D RsV =3D RtV =3D float32_nan; + float_raise(float_flag_invalid, fp_status); + } else if (float32_is_zero(RsV) && float32_is_zero(RtV)) { + /* or put zero in num fixup? */ + RdV =3D RsV =3D RtV =3D float32_nan; + float_raise(float_flag_invalid, fp_status); + } else if (float32_is_zero(RtV)) { + /* or put Inf in num fixup? */ + uint8_t RsV_sign =3D float32_is_neg(RsV); + uint8_t RtV_sign =3D float32_is_neg(RtV); + RsV =3D infinite_float32(RsV_sign ^ RtV_sign); + RtV =3D float32_one; + RdV =3D float32_one; + if (float32_is_infinity(RsV)) { + float_raise(float_flag_divbyzero, fp_status); + } + } else if (float32_is_infinity(RtV)) { + RsV =3D make_float32(0x80000000 & (RsV ^ RtV)); + RtV =3D float32_one; + RdV =3D float32_one; + } else if (float32_is_zero(RsV)) { + /* Does this just work itself out? */ + /* No, 0/Inf causes problems. */ + RsV =3D make_float32(0x80000000 & (RsV ^ RtV)); + RtV =3D float32_one; + RdV =3D float32_one; + } else if (float32_is_infinity(RsV)) { + uint8_t RsV_sign =3D float32_is_neg(RsV); + uint8_t RtV_sign =3D float32_is_neg(RtV); + RsV =3D infinite_float32(RsV_sign ^ RtV_sign); + RtV =3D float32_one; + RdV =3D float32_one; + } else { + PeV =3D 0x00; + /* Basic checks passed */ + n_exp =3D float32_getexp(RsV); + d_exp =3D float32_getexp(RtV); + if ((n_exp - d_exp + SF_BIAS) <=3D SF_MANTBITS) { + /* Near quotient underflow / inexact Q */ + PeV =3D 0x80; + RtV =3D float32_mul_pow2(RtV, -64, fp_status); + RsV =3D float32_mul_pow2(RsV, 64, fp_status); + } else if ((n_exp - d_exp + SF_BIAS) > (SF_MAXEXP - 24)) { + /* Near quotient overflow */ + PeV =3D 0x40; + RtV =3D float32_mul_pow2(RtV, 32, fp_status); + RsV =3D float32_mul_pow2(RsV, -32, fp_status); + } else if (n_exp <=3D SF_MANTBITS + 2) { + RtV =3D float32_mul_pow2(RtV, 64, fp_status); + RsV =3D float32_mul_pow2(RsV, 64, fp_status); + } else if (d_exp <=3D 1) { + RtV =3D float32_mul_pow2(RtV, 32, fp_status); + RsV =3D float32_mul_pow2(RsV, 32, fp_status); + } else if (d_exp > 252) { + RtV =3D float32_mul_pow2(RtV, -32, fp_status); + RsV =3D float32_mul_pow2(RsV, -32, fp_status); + } + RdV =3D 0; + ret =3D 1; + } + *Rs =3D RsV; + *Rt =3D RtV; + *Rd =3D RdV; + *adjust =3D PeV; + return ret; +} + +int arch_sf_invsqrt_common(float32 *Rs, float32 *Rd, int *adjust, + float_status *fp_status) +{ + float32 RsV, RdV; + int PeV =3D 0; + int r_exp; + int ret =3D 0; + RsV =3D *Rs; + if (float32_is_infinity(RsV)) { + if (extract32(RsV, 22, 1) =3D=3D 0) { + float_raise(float_flag_invalid, fp_status); + } + RdV =3D RsV =3D float32_nan; + } else if (float32_lt(RsV, float32_zero, fp_status)) { + /* Negative nonzero values are NaN */ + float_raise(float_flag_invalid, fp_status); + RsV =3D float32_nan; + RdV =3D float32_nan; + } else if (float32_is_infinity(RsV)) { + /* or put Inf in num fixup? */ + RsV =3D infinite_float32(1); + RdV =3D infinite_float32(1); + } else if (float32_is_zero(RsV)) { + /* or put zero in num fixup? */ + RdV =3D float32_one; + } else { + PeV =3D 0x00; + /* Basic checks passed */ + r_exp =3D float32_getexp(RsV); + if (r_exp <=3D 24) { + RsV =3D float32_mul_pow2(RsV, 64, fp_status); + PeV =3D 0xe0; + } + RdV =3D 0; + ret =3D 1; + } + *Rs =3D RsV; + *Rd =3D RdV; + *adjust =3D PeV; + return ret; +} --=20 2.7.4