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[147.11.124.94]) by smtp.gmail.com with ESMTPSA id s6sm11089546ild.45.2021.01.19.05.40.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 19 Jan 2021 05:40:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8RGy8xtddkf/Hto4xoWIa8XeOj/4qpPYA/syTc95gqg=; b=K2GDJ+5tCgk1p4oz1whw/ZDacMlkuUBqH8Z6zP6UmQhk0QRpiOb21oFGchagmNZYwv 9l5YE/Qp9GuBATYWzCnuW9JaUvXo49DE+EDR6exklbxiwSddP67HNTsUExTOxtwkhwSb juX25InKpQxPqdSF5jalMcnzBFy08RbfOAib+XIUMIk5rsnMprp/9JylUCkPsQGHtzZS QRtRQypdwAE6ktTZ6LRxxEC19KoDj2FR6DLMWzcwDwySP6ZES/Mr3gb84CBeJEaPfXan 5yJdTG28WM9mTxCDq4TjrfMDjxJWXoQgomDodvk8Kucsh0KpHNGjOYuf2nUBS6lTVe/T GP1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8RGy8xtddkf/Hto4xoWIa8XeOj/4qpPYA/syTc95gqg=; b=KCYX/0uSfwGtxn4K/pKfE4Ez28Dp9ekCY7qUXf4KvtYEsZH2pBesdHvUT2ZU9y7F5l S6mKGfvu+/eoAS2hdqEsHa0+Q8xfEw005vVbk2PkuQrPu0PcEnMFFLVF9qzvZ6Z9Jjo4 gjvteGQi0nMTjrekdVdBBvtwK3mgPprOFYbyOOZ8SYBc/NU7GNM0oRSrNh37MAQVek+C 3WEzoqcB8yvBk24p0X1bf5wuylj0iS68eEQlKWupS7ExKWarEWygCWmAFNQ11ZlzYTEk CdeXIadOCIKll8Bo0Harc3L28exME2nu8CWFLbNMpB+P5ad0PGiGHNe698ZAlwDuw9TL GPDA== X-Gm-Message-State: AOAM532NXrOCQC+xfWQaNWKON05OpvS7ZdsldHHCiiGHTGjQjmCTKPma GftAlyhV/6Rw8OcPbgM08NA= X-Google-Smtp-Source: ABdhPJy3Ux6p2NP5QBZNpMdeFFm+tETzDN9JrFtzjUcowAi94is/DiKgqU+fITJ+mZvop/Ce3xlFjQ== X-Received: by 2002:a05:6638:214a:: with SMTP id z10mr3500247jaj.41.1611063635884; Tue, 19 Jan 2021 05:40:35 -0800 (PST) From: Bin Meng To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , Alistair Francis Subject: [PATCH v8 07/10] hw/ssi: imx_spi: Disable chip selects when controller is disabled Date: Tue, 19 Jan 2021 21:39:03 +0800 Message-Id: <1611063546-20278-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> References: <1611063546-20278-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::d2f; envelope-from=bmeng.cn@gmail.com; helo=mail-io1-xd2f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , Xuzhou Cheng , qemu-arm@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Xuzhou Cheng When a write to ECSPI_CONREG register to disable the SPI controller, imx_spi_reset() is called to reset the controller, but chip select lines should have been disabled, otherwise the state machine of any devices (e.g.: SPI flashes) connected to the SPI master is stuck to its last state and responds incorrectly to any follow-up commands. Fixes: c906a3a01582 ("i.MX: Add the Freescale SPI Controller") Signed-off-by: Xuzhou Cheng Signed-off-by: Bin Meng Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- (no changes since v3) Changes in v3: - Move the chip selects disable out of imx_spi_reset() Changes in v2: - Fix the "Fixes" tag in the commit message hw/ssi/imx_spi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/ssi/imx_spi.c b/hw/ssi/imx_spi.c index 23f9f9d..5838bb0 100644 --- a/hw/ssi/imx_spi.c +++ b/hw/ssi/imx_spi.c @@ -257,9 +257,15 @@ static void imx_spi_reset(DeviceState *dev) =20 static void imx_spi_soft_reset(IMXSPIState *s) { + int i; + imx_spi_reset(DEVICE(s)); =20 imx_spi_update_irq(s); + + for (i =3D 0; i < ECSPI_NUM_CS; i++) { + qemu_set_irq(s->cs_lines[i], 1); + } } =20 static uint64_t imx_spi_read(void *opaque, hwaddr offset, unsigned size) --=20 2.7.4