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[147.11.124.94]) by smtp.gmail.com with ESMTPSA id b67sm863814qkc.44.2021.01.11.20.52.13 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 11 Jan 2021 20:52:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XulXpk/URsYQ/0PFYvTgQh46JVvQ+x1a9lNdwgJyFaU=; b=bqOE/RuOcrL3klhahIodrPrqFfQcK0s6HtV+40FVF9/nJ7i2r+tzzu8KI/BTvhPHqe trJxCkmn2MOiuHD7dRXBTJ0xzT90QDMhpApJIJUPB5jjN++GWoYf5wWZa6/E4gziQ200 qV1mJPkxDssdfyxVrS5U3gc2EeAlm5H/RM7eBbcvrkFH6o8I6ATXPtVnotJ1kUIhY0Yg OzVOUppd6P46kOBGQXyC246SLcw9VCV7mWk7aEAUHRznhu7rsTvfT0JkiirdAGZsUvgP gC8DKkOCSdF9KV9X8r2TJrmW1pH+cj3YQ0lc5mT+nZJGOQ8+oD5WX63x7su8QKb5gKcs 1H6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XulXpk/URsYQ/0PFYvTgQh46JVvQ+x1a9lNdwgJyFaU=; b=aY5qL5ZFgqX/wz/T/LsgR5Qca5Ne+4fIhFbiuuij6Qh+nGwrhyRCsR2s2rJpn8ycBE yNNM85bLl9RORoykigPOh9J5obTLwC8oMxXkn7VfvsvUIeZ65PeKJpE746QYGN0rlQdD 2eZeKK0WR5AHNtbJHn7yYDZfKiJmEzaizn1CxQCBM80P9lzRDZo53/5Ddnk5vSwOJS0J k8yOOPrZ32mYSvXObFI26rShMzycCncK4HchuEGtCYPrDQZ8bptt7tMqlY3esH8LN3vC l+cFsxiea59Ta7R3Bx6idw4IBV5wDYO92Qeva4KmQKoQYV9WaSjr0MVNlWOlKrrmhbww oPbQ== X-Gm-Message-State: AOAM533Pd4gY08ukDwBA9PDSD7SGSjuNg9yGUDa728j5/zRS2k/U5Jj8 NSfgnLkSbG94u+arLn0D2QM= X-Google-Smtp-Source: ABdhPJxqjQWcSs2cCp9iso3q8oRJTppRT3s9k4dseYIzGjMEwYp77nEmjhKYtFl01nUMK1zvbb0Lyw== X-Received: by 2002:a05:620a:1279:: with SMTP id b25mr2778160qkl.8.1610427137504; Mon, 11 Jan 2021 20:52:17 -0800 (PST) From: Bin Meng To: Jim Wilson , Alistair Francis Subject: [PATCH 2/4] target/riscv: Add CSR name in the CSR function table Date: Tue, 12 Jan 2021 12:52:02 +0800 Message-Id: <1610427124-49887-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610427124-49887-1-git-send-email-bmeng.cn@gmail.com> References: <1610427124-49887-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::72c; envelope-from=bmeng.cn@gmail.com; helo=mail-qk1-x72c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng In preparation to generate the CSR register list for GDB stub dynamically, let's add the CSR name in the CSR function table. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 1 + target/riscv/csr.c | 332 +++++++++++++++++++++++++++++++++++++++----------= ---- 2 files changed, 249 insertions(+), 84 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6f9e1cc..6684316 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -476,6 +476,7 @@ typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int = csrno, target_ulong *ret_value, target_ulong new_value, target_ulong write_ma= sk); =20 typedef struct { + const char *name; riscv_csr_predicate_fn predicate; riscv_csr_read_fn read; riscv_csr_write_fn write; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 507e8ee..fd2e636 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1372,112 +1372,276 @@ int riscv_csrrw_debug(CPURISCVState *env, int csr= no, target_ulong *ret_value, /* Control and Status Register function table */ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { /* User Floating-Point CSRs */ - [CSR_FFLAGS] =3D { fs, read_fflags, write_fflags = }, - [CSR_FRM] =3D { fs, read_frm, write_frm = }, - [CSR_FCSR] =3D { fs, read_fcsr, write_fcsr = }, + [CSR_FFLAGS] =3D { "fflags", fs, read_fflags, write_fflags }, + [CSR_FRM] =3D { "frm", fs, read_frm, write_frm }, + [CSR_FCSR] =3D { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] =3D { vs, read_vstart, write_vstart = }, - [CSR_VXSAT] =3D { vs, read_vxsat, write_vxsat = }, - [CSR_VXRM] =3D { vs, read_vxrm, write_vxrm = }, - [CSR_VL] =3D { vs, read_vl = }, - [CSR_VTYPE] =3D { vs, read_vtype = }, + [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart }, + [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat }, + [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm }, + [CSR_VL] =3D { "vl", vs, read_vl }, + [CSR_VTYPE] =3D { "vtype", vs, read_vtype }, /* User Timers and Counters */ - [CSR_CYCLE] =3D { ctr, read_instret = }, - [CSR_INSTRET] =3D { ctr, read_instret = }, - [CSR_CYCLEH] =3D { ctr32, read_instreth = }, - [CSR_INSTRETH] =3D { ctr32, read_instreth = }, - - /* In privileged mode, the monitor will have to emulate TIME CSRs only= if - * rdtime callback is not provided by machine/platform emulation */ - [CSR_TIME] =3D { ctr, read_time = }, - [CSR_TIMEH] =3D { ctr32, read_timeh = }, + [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, + [CSR_INSTRET] =3D { "instret", ctr, read_instret }, + [CSR_CYCLEH] =3D { "cycleh", ctr32, read_instreth }, + [CSR_INSTRETH] =3D { "instreth", ctr32, read_instreth }, + + /* + * In privileged mode, the monitor will have to emulate TIME CSRs only= if + * rdtime callback is not provided by machine/platform emulation. + */ + [CSR_TIME] =3D { "time", ctr, read_time }, + [CSR_TIMEH] =3D { "timeh", ctr32, read_timeh }, =20 #if !defined(CONFIG_USER_ONLY) /* Machine Timers and Counters */ - [CSR_MCYCLE] =3D { any, read_instret = }, - [CSR_MINSTRET] =3D { any, read_instret = }, - [CSR_MCYCLEH] =3D { any32, read_instreth = }, - [CSR_MINSTRETH] =3D { any32, read_instreth = }, + [CSR_MCYCLE] =3D { "mcycle", any, read_instret }, + [CSR_MINSTRET] =3D { "minstret", any, read_instret }, + [CSR_MCYCLEH] =3D { "mcycleh", any32, read_instreth }, + [CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth }, =20 /* Machine Information Registers */ - [CSR_MVENDORID] =3D { any, read_zero = }, - [CSR_MARCHID] =3D { any, read_zero = }, - [CSR_MIMPID] =3D { any, read_zero = }, - [CSR_MHARTID] =3D { any, read_mhartid = }, + [CSR_MVENDORID] =3D { "mvendorid", any, read_zero }, + [CSR_MARCHID] =3D { "marchid", any, read_zero }, + [CSR_MIMPID] =3D { "mimpid", any, read_zero }, + [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, =20 /* Machine Trap Setup */ - [CSR_MSTATUS] =3D { any, read_mstatus, write_mstatus = }, - [CSR_MISA] =3D { any, read_misa, write_misa = }, - [CSR_MIDELEG] =3D { any, read_mideleg, write_mideleg = }, - [CSR_MEDELEG] =3D { any, read_medeleg, write_medeleg = }, - [CSR_MIE] =3D { any, read_mie, write_mie = }, - [CSR_MTVEC] =3D { any, read_mtvec, write_mtvec = }, - [CSR_MCOUNTEREN] =3D { any, read_mcounteren, write_mcounter= en }, + [CSR_MSTATUS] =3D { "mstatus", any, read_mstatus, write_m= status }, + [CSR_MISA] =3D { "misa", any, read_misa, write_m= isa }, + [CSR_MIDELEG] =3D { "mideleg", any, read_mideleg, write_m= ideleg }, + [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_m= edeleg }, + [CSR_MIE] =3D { "mie", any, read_mie, write_m= ie }, + [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_m= tvec }, + [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, write_m= counteren }, =20 - [CSR_MSTATUSH] =3D { any32, read_mstatush, write_mstatu= sh }, + [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, =20 - [CSR_MSCOUNTEREN] =3D { any, read_mscounteren, write_mscounte= ren }, + [CSR_MSCOUNTEREN] =3D { "msounteren", any, read_mscounteren, write_m= scounteren }, =20 /* Machine Trap Handling */ - [CSR_MSCRATCH] =3D { any, read_mscratch, write_mscratch= }, - [CSR_MEPC] =3D { any, read_mepc, write_mepc = }, - [CSR_MCAUSE] =3D { any, read_mcause, write_mcause = }, - [CSR_MBADADDR] =3D { any, read_mbadaddr, write_mbadaddr= }, - [CSR_MIP] =3D { any, NULL, NULL, rmw_mip = }, + [CSR_MSCRATCH] =3D { "mscratch", any, read_mscratch, write_mscratch }, + [CSR_MEPC] =3D { "mepc", any, read_mepc, write_mepc }, + [CSR_MCAUSE] =3D { "mcause", any, read_mcause, write_mcause }, + [CSR_MBADADDR] =3D { "mbadaddr", any, read_mbadaddr, write_mbadaddr }, + [CSR_MIP] =3D { "mip", any, NULL, NULL, rmw_mip }, =20 /* Supervisor Trap Setup */ - [CSR_SSTATUS] =3D { smode, read_sstatus, write_sstatus= }, - [CSR_SIE] =3D { smode, read_sie, write_sie = }, - [CSR_STVEC] =3D { smode, read_stvec, write_stvec = }, - [CSR_SCOUNTEREN] =3D { smode, read_scounteren, write_scounte= ren }, + [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus }, + [CSR_SIE] =3D { "sie", smode, read_sie, write_sie= }, + [CSR_STVEC] =3D { "stvec", smode, read_stvec, write_stv= ec }, + [CSR_SCOUNTEREN] =3D { "scounteren", smode, read_scounteren, write_sco= unteren }, =20 /* Supervisor Trap Handling */ - [CSR_SSCRATCH] =3D { smode, read_sscratch, write_sscratc= h }, - [CSR_SEPC] =3D { smode, read_sepc, write_sepc = }, - [CSR_SCAUSE] =3D { smode, read_scause, write_scause = }, - [CSR_SBADADDR] =3D { smode, read_sbadaddr, write_sbadadd= r }, - [CSR_SIP] =3D { smode, NULL, NULL, rmw_sip = }, + [CSR_SSCRATCH] =3D { "sscratch", smode, read_sscratch, write_sscratch = }, + [CSR_SEPC] =3D { "sepc", smode, read_sepc, write_sepc = }, + [CSR_SCAUSE] =3D { "scause", smode, read_scause, write_scause = }, + [CSR_SBADADDR] =3D { "sbadaddr", smode, read_sbadaddr, write_sbadaddr = }, + [CSR_SIP] =3D { "sip", smode, NULL, NULL, rmw_sip = }, =20 /* Supervisor Protection and Translation */ - [CSR_SATP] =3D { smode, read_satp, write_satp = }, - - [CSR_HSTATUS] =3D { hmode, read_hstatus, write_hstat= us }, - [CSR_HEDELEG] =3D { hmode, read_hedeleg, write_hedel= eg }, - [CSR_HIDELEG] =3D { hmode, read_hideleg, write_hidel= eg }, - [CSR_HVIP] =3D { hmode, NULL, NULL, rmw_hvip = }, - [CSR_HIP] =3D { hmode, NULL, NULL, rmw_hip = }, - [CSR_HIE] =3D { hmode, read_hie, write_hie = }, - [CSR_HCOUNTEREN] =3D { hmode, read_hcounteren, write_hcoun= teren }, - [CSR_HGEIE] =3D { hmode, read_hgeie, write_hgeie= }, - [CSR_HTVAL] =3D { hmode, read_htval, write_htval= }, - [CSR_HTINST] =3D { hmode, read_htinst, write_htins= t }, - [CSR_HGEIP] =3D { hmode, read_hgeip, write_hgeip= }, - [CSR_HGATP] =3D { hmode, read_hgatp, write_hgatp= }, - [CSR_HTIMEDELTA] =3D { hmode, read_htimedelta, write_htime= delta }, - [CSR_HTIMEDELTAH] =3D { hmode32, read_htimedeltah, write_hti= medeltah}, - - [CSR_VSSTATUS] =3D { hmode, read_vsstatus, write_vssta= tus }, - [CSR_VSIP] =3D { hmode, NULL, NULL, rmw_vsip = }, - [CSR_VSIE] =3D { hmode, read_vsie, write_vsie = }, - [CSR_VSTVEC] =3D { hmode, read_vstvec, write_vstve= c }, - [CSR_VSSCRATCH] =3D { hmode, read_vsscratch, write_vsscr= atch }, - [CSR_VSEPC] =3D { hmode, read_vsepc, write_vsepc= }, - [CSR_VSCAUSE] =3D { hmode, read_vscause, write_vscau= se }, - [CSR_VSTVAL] =3D { hmode, read_vstval, write_vstva= l }, - [CSR_VSATP] =3D { hmode, read_vsatp, write_vsatp= }, - - [CSR_MTVAL2] =3D { hmode, read_mtval2, write_mtval= 2 }, - [CSR_MTINST] =3D { hmode, read_mtinst, write_mtins= t }, + [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, + + [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, writ= e_hstatus }, + [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, writ= e_hedeleg }, + [CSR_HIDELEG] =3D { "hideleg", hmode, read_hideleg, writ= e_hideleg }, + [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_= hvip }, + [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_= hip }, + [CSR_HIE] =3D { "hie", hmode, read_hie, writ= e_hie }, + [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, writ= e_hcounteren }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie }, + [CSR_HTVAL] =3D { "htval", hmode, read_htval, writ= e_htval }, + [CSR_HTINST] =3D { "htinst", hmode, read_htinst, writ= e_htinst }, + [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, writ= e_hgeip }, + [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, writ= e_hgatp }, + [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, writ= e_htimedelta }, + [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah }, + + [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, writ= e_vsstatus }, + [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_= vsip }, + [CSR_VSIE] =3D { "vsie", hmode, read_vsie, writ= e_vsie }, + [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, writ= e_vstvec }, + [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, writ= e_vsscratch }, + [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, writ= e_vsepc }, + [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, writ= e_vscause }, + [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, writ= e_vstval }, + [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, writ= e_vsatp }, + + [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, writ= e_mtval2 }, + [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, =20 /* Physical Memory Protection */ - [CSR_PMPCFG0 ... CSR_PMPCFG3] =3D { pmp, read_pmpcfg, write_pmpc= fg }, - [CSR_PMPADDR0 ... CSR_PMPADDR15] =3D { pmp, read_pmpaddr, write_pmpa= ddr }, + [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, + [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, + [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, + [CSR_PMPCFG3] =3D { "pmpcfg3", pmp, read_pmpcfg, write_pmpcfg }, + [CSR_PMPADDR0] =3D { "pmpaddr0", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR1] =3D { "pmpaddr1", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR2] =3D { "pmpaddr2", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR3] =3D { "pmpaddr3", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR4] =3D { "pmpaddr4", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR5] =3D { "pmpaddr5", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR6] =3D { "pmpaddr6", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR7] =3D { "pmpaddr7", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR8] =3D { "pmpaddr8", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR9] =3D { "pmpaddr9", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR10] =3D { "pmpaddr10", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR11] =3D { "pmpaddr11", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR12] =3D { "pmpaddr12", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR13] =3D { "pmpaddr13", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, + [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, =20 /* Performance Counters */ - [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] =3D { ctr, read_zero = }, - [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] =3D { any, read_zero = }, - [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] =3D { any, read_zero = }, - [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] =3D { ctr32, read_zero = }, - [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] =3D { any32, read_zero = }, + [CSR_HPMCOUNTER3] =3D { "hpmcounter3", ctr, read_zero }, + [CSR_HPMCOUNTER4] =3D { "hpmcounter4", ctr, read_zero }, + [CSR_HPMCOUNTER5] =3D { "hpmcounter5", ctr, read_zero }, + [CSR_HPMCOUNTER6] =3D { "hpmcounter6", ctr, read_zero }, + [CSR_HPMCOUNTER7] =3D { "hpmcounter7", ctr, read_zero }, + [CSR_HPMCOUNTER8] =3D { "hpmcounter8", ctr, read_zero }, + [CSR_HPMCOUNTER9] =3D { "hpmcounter9", ctr, read_zero }, + [CSR_HPMCOUNTER10] =3D { "hpmcounter10", ctr, read_zero }, + [CSR_HPMCOUNTER11] =3D { "hpmcounter11", ctr, read_zero }, + [CSR_HPMCOUNTER12] =3D { "hpmcounter12", ctr, read_zero }, + [CSR_HPMCOUNTER13] =3D { "hpmcounter13", ctr, read_zero }, + [CSR_HPMCOUNTER14] =3D { "hpmcounter14", ctr, read_zero }, + [CSR_HPMCOUNTER15] =3D { "hpmcounter15", ctr, read_zero }, + [CSR_HPMCOUNTER16] =3D { "hpmcounter16", ctr, read_zero }, + [CSR_HPMCOUNTER17] =3D { "hpmcounter17", ctr, read_zero }, + [CSR_HPMCOUNTER18] =3D { "hpmcounter18", ctr, read_zero }, + [CSR_HPMCOUNTER19] =3D { "hpmcounter19", ctr, read_zero }, + [CSR_HPMCOUNTER20] =3D { "hpmcounter20", ctr, read_zero }, + [CSR_HPMCOUNTER21] =3D { "hpmcounter21", ctr, read_zero }, + [CSR_HPMCOUNTER22] =3D { "hpmcounter22", ctr, read_zero }, + [CSR_HPMCOUNTER23] =3D { "hpmcounter23", ctr, read_zero }, + [CSR_HPMCOUNTER24] =3D { "hpmcounter24", ctr, read_zero }, + [CSR_HPMCOUNTER25] =3D { "hpmcounter25", ctr, read_zero }, + [CSR_HPMCOUNTER26] =3D { "hpmcounter26", ctr, read_zero }, + [CSR_HPMCOUNTER27] =3D { "hpmcounter27", ctr, read_zero }, + [CSR_HPMCOUNTER28] =3D { "hpmcounter28", ctr, read_zero }, + [CSR_HPMCOUNTER29] =3D { "hpmcounter29", ctr, read_zero }, + [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, + [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, + + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", any, read_zero }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", any, read_zero }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", any, read_zero }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", any, read_zero }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", any, read_zero }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", any, read_zero }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", any, read_zero }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", any, read_zero }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", any, read_zero }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", any, read_zero }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", any, read_zero }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", any, read_zero }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", any, read_zero }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", any, read_zero }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", any, read_zero }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", any, read_zero }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", any, read_zero }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", any, read_zero }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", any, read_zero }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", any, read_zero }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", any, read_zero }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", any, read_zero }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", any, read_zero }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", any, read_zero }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", any, read_zero }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", any, read_zero }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", any, read_zero }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, + + [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, + [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, + [CSR_MHPMEVENT5] =3D { "mhpmevent5", any, read_zero }, + [CSR_MHPMEVENT6] =3D { "mhpmevent6", any, read_zero }, + [CSR_MHPMEVENT7] =3D { "mhpmevent7", any, read_zero }, + [CSR_MHPMEVENT8] =3D { "mhpmevent8", any, read_zero }, + [CSR_MHPMEVENT9] =3D { "mhpmevent9", any, read_zero }, + [CSR_MHPMEVENT10] =3D { "mhpmevent10", any, read_zero }, + [CSR_MHPMEVENT11] =3D { "mhpmevent11", any, read_zero }, + [CSR_MHPMEVENT12] =3D { "mhpmevent12", any, read_zero }, + [CSR_MHPMEVENT13] =3D { "mhpmevent13", any, read_zero }, + [CSR_MHPMEVENT14] =3D { "mhpmevent14", any, read_zero }, + [CSR_MHPMEVENT15] =3D { "mhpmevent15", any, read_zero }, + [CSR_MHPMEVENT16] =3D { "mhpmevent16", any, read_zero }, + [CSR_MHPMEVENT17] =3D { "mhpmevent17", any, read_zero }, + [CSR_MHPMEVENT18] =3D { "mhpmevent18", any, read_zero }, + [CSR_MHPMEVENT19] =3D { "mhpmevent19", any, read_zero }, + [CSR_MHPMEVENT20] =3D { "mhpmevent20", any, read_zero }, + [CSR_MHPMEVENT21] =3D { "mhpmevent21", any, read_zero }, + [CSR_MHPMEVENT22] =3D { "mhpmevent22", any, read_zero }, + [CSR_MHPMEVENT23] =3D { "mhpmevent23", any, read_zero }, + [CSR_MHPMEVENT24] =3D { "mhpmevent24", any, read_zero }, + [CSR_MHPMEVENT25] =3D { "mhpmevent25", any, read_zero }, + [CSR_MHPMEVENT26] =3D { "mhpmevent26", any, read_zero }, + [CSR_MHPMEVENT27] =3D { "mhpmevent27", any, read_zero }, + [CSR_MHPMEVENT28] =3D { "mhpmevent28", any, read_zero }, + [CSR_MHPMEVENT29] =3D { "mhpmevent29", any, read_zero }, + [CSR_MHPMEVENT30] =3D { "mhpmevent30", any, read_zero }, + [CSR_MHPMEVENT31] =3D { "mhpmevent31", any, read_zero }, + + [CSR_HPMCOUNTER3H] =3D { "hpmcounter3h", ctr32, read_zero }, + [CSR_HPMCOUNTER4H] =3D { "hpmcounter4h", ctr32, read_zero }, + [CSR_HPMCOUNTER5H] =3D { "hpmcounter5h", ctr32, read_zero }, + [CSR_HPMCOUNTER6H] =3D { "hpmcounter6h", ctr32, read_zero }, + [CSR_HPMCOUNTER7H] =3D { "hpmcounter7h", ctr32, read_zero }, + [CSR_HPMCOUNTER8H] =3D { "hpmcounter8h", ctr32, read_zero }, + [CSR_HPMCOUNTER9H] =3D { "hpmcounter9h", ctr32, read_zero }, + [CSR_HPMCOUNTER10H] =3D { "hpmcounter10h", ctr32, read_zero }, + [CSR_HPMCOUNTER11H] =3D { "hpmcounter11h", ctr32, read_zero }, + [CSR_HPMCOUNTER12H] =3D { "hpmcounter12h", ctr32, read_zero }, + [CSR_HPMCOUNTER13H] =3D { "hpmcounter13h", ctr32, read_zero }, + [CSR_HPMCOUNTER14H] =3D { "hpmcounter14h", ctr32, read_zero }, + [CSR_HPMCOUNTER15H] =3D { "hpmcounter15h", ctr32, read_zero }, + [CSR_HPMCOUNTER16H] =3D { "hpmcounter16h", ctr32, read_zero }, + [CSR_HPMCOUNTER17H] =3D { "hpmcounter17h", ctr32, read_zero }, + [CSR_HPMCOUNTER18H] =3D { "hpmcounter18h", ctr32, read_zero }, + [CSR_HPMCOUNTER19H] =3D { "hpmcounter19h", ctr32, read_zero }, + [CSR_HPMCOUNTER20H] =3D { "hpmcounter20h", ctr32, read_zero }, + [CSR_HPMCOUNTER21H] =3D { "hpmcounter21h", ctr32, read_zero }, + [CSR_HPMCOUNTER22H] =3D { "hpmcounter22h", ctr32, read_zero }, + [CSR_HPMCOUNTER23H] =3D { "hpmcounter23h", ctr32, read_zero }, + [CSR_HPMCOUNTER24H] =3D { "hpmcounter24h", ctr32, read_zero }, + [CSR_HPMCOUNTER25H] =3D { "hpmcounter25h", ctr32, read_zero }, + [CSR_HPMCOUNTER26H] =3D { "hpmcounter26h", ctr32, read_zero }, + [CSR_HPMCOUNTER27H] =3D { "hpmcounter27h", ctr32, read_zero }, + [CSR_HPMCOUNTER28H] =3D { "hpmcounter28h", ctr32, read_zero }, + [CSR_HPMCOUNTER29H] =3D { "hpmcounter29h", ctr32, read_zero }, + [CSR_HPMCOUNTER30H] =3D { "hpmcounter30h", ctr32, read_zero }, + [CSR_HPMCOUNTER31H] =3D { "hpmcounter31h", ctr32, read_zero }, + + [CSR_MHPMCOUNTER3H] =3D { "mhpmcounter3h", any32, read_zero }, + [CSR_MHPMCOUNTER4H] =3D { "mhpmcounter4h", any32, read_zero }, + [CSR_MHPMCOUNTER5H] =3D { "mhpmcounter5h", any32, read_zero }, + [CSR_MHPMCOUNTER6H] =3D { "mhpmcounter6h", any32, read_zero }, + [CSR_MHPMCOUNTER7H] =3D { "mhpmcounter7h", any32, read_zero }, + [CSR_MHPMCOUNTER8H] =3D { "mhpmcounter8h", any32, read_zero }, + [CSR_MHPMCOUNTER9H] =3D { "mhpmcounter9h", any32, read_zero }, + [CSR_MHPMCOUNTER10H] =3D { "mhpmcounter10h", any32, read_zero }, + [CSR_MHPMCOUNTER11H] =3D { "mhpmcounter11h", any32, read_zero }, + [CSR_MHPMCOUNTER12H] =3D { "mhpmcounter12h", any32, read_zero }, + [CSR_MHPMCOUNTER13H] =3D { "mhpmcounter13h", any32, read_zero }, + [CSR_MHPMCOUNTER14H] =3D { "mhpmcounter14h", any32, read_zero }, + [CSR_MHPMCOUNTER15H] =3D { "mhpmcounter15h", any32, read_zero }, + [CSR_MHPMCOUNTER16H] =3D { "mhpmcounter16h", any32, read_zero }, + [CSR_MHPMCOUNTER17H] =3D { "mhpmcounter17h", any32, read_zero }, + [CSR_MHPMCOUNTER18H] =3D { "mhpmcounter18h", any32, read_zero }, + [CSR_MHPMCOUNTER19H] =3D { "mhpmcounter19h", any32, read_zero }, + [CSR_MHPMCOUNTER20H] =3D { "mhpmcounter20h", any32, read_zero }, + [CSR_MHPMCOUNTER21H] =3D { "mhpmcounter21h", any32, read_zero }, + [CSR_MHPMCOUNTER22H] =3D { "mhpmcounter22h", any32, read_zero }, + [CSR_MHPMCOUNTER23H] =3D { "mhpmcounter23h", any32, read_zero }, + [CSR_MHPMCOUNTER24H] =3D { "mhpmcounter24h", any32, read_zero }, + [CSR_MHPMCOUNTER25H] =3D { "mhpmcounter25h", any32, read_zero }, + [CSR_MHPMCOUNTER26H] =3D { "mhpmcounter26h", any32, read_zero }, + [CSR_MHPMCOUNTER27H] =3D { "mhpmcounter27h", any32, read_zero }, + [CSR_MHPMCOUNTER28H] =3D { "mhpmcounter28h", any32, read_zero }, + [CSR_MHPMCOUNTER29H] =3D { "mhpmcounter29h", any32, read_zero }, + [CSR_MHPMCOUNTER30H] =3D { "mhpmcounter30h", any32, read_zero }, + [CSR_MHPMCOUNTER31H] =3D { "mhpmcounter31h", any32, read_zero }, #endif /* !CONFIG_USER_ONLY */ }; --=20 2.7.4