From nobody Mon Feb 9 20:10:21 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1610082639; cv=none; d=zohomail.com; s=zohoarc; b=OfZNaE+Y6YdHoMpKBpvILPWuRgZvpb/SSuxZdAaIF+7B/3fokiQJ5nWQfG6D/aCkTi6Xk7Gvarnyv1x+aZ6YN+uInejYrtejIOZXIVNp6eFsaUXLj0bu3WTC1JPGGH75eJYfcwu0O4mT+6nIti+usEboGmOqJLrJIYxRgINsUjk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1610082639; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MP0p+d0tCPd8RO+KWYmjChAvFvfuCSZjYWt38Th6n6c=; b=NdyWkwsLNoglopRF/GjgRr0iGXoULhZ/MzGS+t60QqrevQCY2SmfMPppKHPlD1M0giq/DsUIeLwPCEM02KFuh8r//wbgkrdhKdVqZRoC0yrScKb8gqSLSFN8sDhDKR170eFRsf0UrFkuUy0ksMZxA5mGtLv11zP7oDvN6s9BoWY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1610082639361229.58485888101313; Thu, 7 Jan 2021 21:10:39 -0800 (PST) Received: from localhost ([::1]:55588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kxk2o-0004AB-7O for importer@patchew.org; Fri, 08 Jan 2021 00:10:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:52428) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kxjPg-00081J-2p for qemu-devel@nongnu.org; Thu, 07 Jan 2021 23:30:12 -0500 Received: from alexa-out-sd-01.qualcomm.com ([199.106.114.38]:25196) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1kxjPd-00059s-Py for qemu-devel@nongnu.org; Thu, 07 Jan 2021 23:30:11 -0500 Received: from unknown (HELO ironmsg05-sd.qualcomm.com) ([10.53.140.145]) by alexa-out-sd-01.qualcomm.com with ESMTP; 07 Jan 2021 20:29:15 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg05-sd.qualcomm.com with ESMTP; 07 Jan 2021 20:29:15 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 27C2DFFD; Thu, 7 Jan 2021 22:29:15 -0600 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1610080209; x=1641616209; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=MP0p+d0tCPd8RO+KWYmjChAvFvfuCSZjYWt38Th6n6c=; b=KW3ncuEO1gOpVzDJbsoDlONM0SMzmo9ET+zdlqsObUvt4vaa90rwLuUi QuHGGpBERzy98il7ZiAfCXModq0OCkcNr1C4aFNEOt2OuVpXWnmAoJG9a kyYQuJhKOnyYRqKyTmXOFxQifY4LzzW9IOzD3wxs5TXlk1SgTyFNrIJnd g=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH v6 28/35] Hexagon (target/hexagon) TCG for floating point instructions Date: Thu, 7 Jan 2021 22:28:59 -0600 Message-Id: <1610080146-14968-29-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1610080146-14968-1-git-send-email-tsimpson@quicinc.com> References: <1610080146-14968-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=199.106.114.38; envelope-from=tsimpson@qualcomm.com; helo=alexa-out-sd-01.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.248, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, laurent@vivier.eu, tsimpson@quicinc.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) The imported code uses host floating point. We override them to use qemu softfloat Signed-off-by: Taylor Simpson --- target/hexagon/gen_tcg.h | 121 +++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 121 insertions(+) diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 35568d1..d605b1e 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -195,4 +195,125 @@ #define fGEN_TCG_S4_stored_locked(SHORTCODE) \ do { SHORTCODE; READ_PREG(PdV, PdN); } while (0) =20 +/* Floating point */ +#define fGEN_TCG_F2_conv_sf2df(SHORTCODE) \ + gen_helper_conv_sf2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2sf(SHORTCODE) \ + gen_helper_conv_df2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_uw2sf(SHORTCODE) \ + gen_helper_conv_uw2sf(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_uw2df(SHORTCODE) \ + gen_helper_conv_uw2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_w2sf(SHORTCODE) \ + gen_helper_conv_w2sf(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_w2df(SHORTCODE) \ + gen_helper_conv_w2df(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_ud2sf(SHORTCODE) \ + gen_helper_conv_ud2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_ud2df(SHORTCODE) \ + gen_helper_conv_ud2df(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_d2sf(SHORTCODE) \ + gen_helper_conv_d2sf(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_d2df(SHORTCODE) \ + gen_helper_conv_d2df(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_sf2uw(SHORTCODE) \ + gen_helper_conv_sf2uw(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2w(SHORTCODE) \ + gen_helper_conv_sf2w(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2ud(SHORTCODE) \ + gen_helper_conv_sf2ud(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2d(SHORTCODE) \ + gen_helper_conv_sf2d(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2uw(SHORTCODE) \ + gen_helper_conv_df2uw(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2w(SHORTCODE) \ + gen_helper_conv_df2w(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2ud(SHORTCODE) \ + gen_helper_conv_df2ud(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2d(SHORTCODE) \ + gen_helper_conv_df2d(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_sf2uw_chop(SHORTCODE) \ + gen_helper_conv_sf2uw_chop(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2w_chop(SHORTCODE) \ + gen_helper_conv_sf2w_chop(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2ud_chop(SHORTCODE) \ + gen_helper_conv_sf2ud_chop(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_sf2d_chop(SHORTCODE) \ + gen_helper_conv_sf2d_chop(RddV, cpu_env, RsV) +#define fGEN_TCG_F2_conv_df2uw_chop(SHORTCODE) \ + gen_helper_conv_df2uw_chop(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2w_chop(SHORTCODE) \ + gen_helper_conv_df2w_chop(RdV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2ud_chop(SHORTCODE) \ + gen_helper_conv_df2ud_chop(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_conv_df2d_chop(SHORTCODE) \ + gen_helper_conv_df2d_chop(RddV, cpu_env, RssV) +#define fGEN_TCG_F2_sfadd(SHORTCODE) \ + gen_helper_sfadd(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfsub(SHORTCODE) \ + gen_helper_sfsub(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpeq(SHORTCODE) \ + gen_helper_sfcmpeq(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpgt(SHORTCODE) \ + gen_helper_sfcmpgt(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpge(SHORTCODE) \ + gen_helper_sfcmpge(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfcmpuo(SHORTCODE) \ + gen_helper_sfcmpuo(PdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfmax(SHORTCODE) \ + gen_helper_sfmax(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfmin(SHORTCODE) \ + gen_helper_sfmin(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sfclass(SHORTCODE) \ + do { \ + TCGv imm =3D tcg_const_tl(uiV); \ + gen_helper_sfclass(PdV, cpu_env, RsV, imm); \ + tcg_temp_free(imm); \ + } while (0) +#define fGEN_TCG_F2_sffixupn(SHORTCODE) \ + gen_helper_sffixupn(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffixupd(SHORTCODE) \ + gen_helper_sffixupd(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffixupr(SHORTCODE) \ + gen_helper_sffixupr(RdV, cpu_env, RsV) +#define fGEN_TCG_F2_dfadd(SHORTCODE) \ + gen_helper_dfadd(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfsub(SHORTCODE) \ + gen_helper_dfsub(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmax(SHORTCODE) \ + gen_helper_dfmax(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmin(SHORTCODE) \ + gen_helper_dfmin(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpeq(SHORTCODE) \ + gen_helper_dfcmpeq(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpgt(SHORTCODE) \ + gen_helper_dfcmpgt(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpge(SHORTCODE) \ + gen_helper_dfcmpge(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfcmpuo(SHORTCODE) \ + gen_helper_dfcmpuo(PdV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfclass(SHORTCODE) \ + do { \ + TCGv imm =3D tcg_const_tl(uiV); \ + gen_helper_dfclass(PdV, cpu_env, RssV, imm); \ + tcg_temp_free(imm); \ + } while (0) +#define fGEN_TCG_F2_sfmpy(SHORTCODE) \ + gen_helper_sfmpy(RdV, cpu_env, RsV, RtV) +#define fGEN_TCG_F2_sffma(SHORTCODE) \ + gen_helper_sffma(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffma_sc(SHORTCODE) \ + gen_helper_sffma_sc(RxV, cpu_env, RxV, RsV, RtV, PuV) +#define fGEN_TCG_F2_sffms(SHORTCODE) \ + gen_helper_sffms(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffma_lib(SHORTCODE) \ + gen_helper_sffma_lib(RxV, cpu_env, RxV, RsV, RtV) +#define fGEN_TCG_F2_sffms_lib(SHORTCODE) \ + gen_helper_sffms_lib(RxV, cpu_env, RxV, RsV, RtV) + +#define fGEN_TCG_F2_dfmpyfix(SHORTCODE) \ + gen_helper_dfmpyfix(RddV, cpu_env, RssV, RttV) +#define fGEN_TCG_F2_dfmpyhh(SHORTCODE) \ + gen_helper_dfmpyhh(RxxV, cpu_env, RxxV, RssV, RttV) + #endif --=20 2.7.4