From nobody Fri Jun 14 00:29:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1606811804; cv=pass; d=zohomail.com; s=zohoarc; b=abIF7K8aN6ALWktlGS1UIe91bqIU7K3dTP7V4CC43Ep7mIKlUnch0y0FhjYdUkHFqhBDddqIBnfwWRhoSO6T6GCZ+XEKZUVGsFQX8atI08kN6Sm7l5vwTEFzaI5VLMiS+xQXfnP6zPI4JL+gcOVTEn4GlneHIJYeQdlDwHgivPg= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606811804; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Fe78VrVGC2p6SU/vzFfLGoLfAfRnLNySc8GfllVEjBI=; b=byxvrEDjkJmYHnFtDgMNCoHpDAYdNwBYsuK032bpidTLYW8q1klqMboPQambYPK+xa9WLUbbXFkiqAyEhAVwrAFmLchv3SJ7cQEauRbtxn8r5MabLFelfDhH2V4bbQ0qwpkDtLMDwpgN+29l7bT7cY//JiOIZ0E6W8MUq9CoTjU= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606811803873746.5179949475591; Tue, 1 Dec 2020 00:36:43 -0800 (PST) Received: from localhost ([::1]:39852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kk19O-0007Eu-NL for importer@patchew.org; Tue, 01 Dec 2020 03:36:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk171-0005TM-7X for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:15 -0500 Received: from mail-dm6nam10on2049.outbound.protection.outlook.com ([40.107.93.49]:20960 helo=NAM10-DM6-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk16x-0002xS-9x for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:14 -0500 Received: from BL0PR1501CA0016.namprd15.prod.outlook.com (2603:10b6:207:17::29) by SJ0PR02MB7853.namprd02.prod.outlook.com (2603:10b6:a03:32e::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.22; Tue, 1 Dec 2020 08:34:07 +0000 Received: from BL2NAM02FT004.eop-nam02.prod.protection.outlook.com (2603:10b6:207:17:cafe::3a) by BL0PR1501CA0016.outlook.office365.com (2603:10b6:207:17::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Tue, 1 Dec 2020 08:34:07 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by BL2NAM02FT004.mail.protection.outlook.com (10.152.76.168) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3611.27 via Frontend Transport; Tue, 1 Dec 2020 08:34:07 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Tue, 1 Dec 2020 00:34:06 -0800 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Tue, 1 Dec 2020 00:34:06 -0800 Received: from [10.140.6.35] (port=34284 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kk16r-0000KB-8D; Tue, 01 Dec 2020 00:34:05 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id C5F6613C04B0; Tue, 1 Dec 2020 14:08:39 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=iArFH6uyFI1oZQmVcenJNXTsOjAg7y6VgIvhqvc3XOzf6KW2ufwLCmzveXsHkP9W1p4uQBLMWDn842Rtu65E6S5gl4Icz9PlkHxIGt3cM1A1gpLs+E1Nxg5dWmYuGSzEMyKyE1mYm+P1p94qCl/OYsicCalyN2jdR6f5ifLFbUpLhs05uQ9uPldM4u557tghZbhONlY47fHBC/VmKvAPBwC7T1jOYtN1EqLXz4wC+TiHrZ3g4+6Q00YI+z09pfsP5H7Zeg9C21POsgfd20g632NkGas697Vr8Q/OHmHsoFooiJRuQrpRamrL2ogA5aaSnzxecN6MJhhwCkEz6h5xHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Fe78VrVGC2p6SU/vzFfLGoLfAfRnLNySc8GfllVEjBI=; b=jiq7CxD+EpVBJc/4Cms2Hx3WB8s1AERK9mQ300e4/iXMSBQgjMLbOnK9xyDlGkAyGdlJ+toO1449m7hpcc5NEhNoqKbQ7Ll6t2BN1ZAmoqf6qmnKB1OH+UT7RvDNOMje+IC9oa0ZGOYxgQfX9MfaAwfR461nHtEXeV8ovSouZuW762Fx29xod8So03exaM5aLi35YykaDY3HQnyA2k4yAiv1ZVcmzykO6lPXkYgebdbG3o3L80+gFIyQdVVIAOiXWXx11ycr6jX98zDOnmiH6E9cvv6Pi8/YImozpyAMiH20sQPcCi9JgOa5DHE++zC5IwXu1nsvCaJmEqjUml2TdA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=gmail.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=Fe78VrVGC2p6SU/vzFfLGoLfAfRnLNySc8GfllVEjBI=; b=IIvjy6bsNFhcue4tSuTLkmIpQDl6ZAGjrhl9Qil4llsiYD10qyYzRjoNhk0YU8UTpNdzzqXX9Dxw8h0jbPt0T5SIqDqa3eyYAKZ9L30Y8rwv/e/ZrBlp5IVKkV7VKvUUS0cdvPoDX+tzjVvIaa2zFPRk4AhmwbVWCVDGzJvsyeU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , "Gerd Hoffmann" , Edgar Iglesias , "Francisco Eduardo Iglesias" , Alistair Francis , Eduardo Habkost , Ying Fang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Vikram Garhwal , Paul Zimmerman , Sai Pavan Boddu Subject: [PATCH v14 1/4] usb: Add versal-usb2-ctrl-regs module Date: Tue, 1 Dec 2020 14:08:32 +0530 Message-ID: <1606811915-8492-2-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 640ef256-6c3a-4e67-ad6a-08d895d3de37 X-MS-TrafficTypeDiagnostic: SJ0PR02MB7853: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:352; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: LnvBmMP+Ni/hTa41zRZmFyFgmpfi4ccMSzPFFovcxWxYRiYX8MDTlg3MCrKxHRdSt1NGM0V9G5PBosWWTH3xiwFsD9pD10u3zU4tt5blkfCdj+xs8X/w/LEMZKX0G0gNK+DaaFIwOJ05bxIy2OhRdkMLRqjOnRTJP8yhPI+oYQZ2AlG2gJPpF1Kcm2NkcXUu6wBKcdcURXY/8ILE/IXLfGzNnvY7I4zVv57mOPHJ6dVEEZ/RPzi5M2oUoobrexd4DPjTYegA+uAaxP9kWbW9MK/cituLnB8YB48uPJ+Zo5UeM42A5+Ha4oRN52quHmCDths7xCRLq6BF28fmTsiXCoPGY/xPHel9vy66/wU554/aRDvtSmIWZN4AbNJBNNWmIP7EVqHTOAG3yP0OT4FEOqN48rLGQQMgbdw6A8V968XpZVc17qdggEhgN7xyM3QQ X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(39860400002)(376002)(346002)(136003)(396003)(46966005)(186003)(7416002)(4326008)(30864003)(82310400003)(2906002)(36906005)(6666004)(26005)(316002)(70586007)(336012)(83380400001)(478600001)(8936002)(110136005)(8676002)(356005)(7636003)(42186006)(2616005)(19627235002)(82740400003)(6636002)(47076004)(921005)(36756003)(426003)(6266002)(5660300002)(70206006)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2020 08:34:07.0324 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 640ef256-6c3a-4e67-ad6a-08d895d3de37 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT004.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR02MB7853 Received-SPF: pass client-ip=40.107.93.49; envelope-from=saipava@xilinx.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This module emulates control registers of versal usb2 controller, this is a= dded just to make guest happy. In general this module would control the phy-reset signal from usb controller, data coherency of the transactions, signals the host system errors received from controller. Signed-off-by: Sai Pavan Boddu Signed-off-by: Vikram Garhwal Reviewed-by: Edgar E. Iglesias Reviewed-by: Peter Maydell --- hw/usb/meson.build | 1 + hw/usb/xlnx-versal-usb2-ctrl-regs.c | 229 ++++++++++++++++++++++++= ++++ include/hw/usb/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++ 3 files changed, 275 insertions(+) create mode 100644 hw/usb/xlnx-versal-usb2-ctrl-regs.c create mode 100644 include/hw/usb/xlnx-versal-usb2-ctrl-regs.h diff --git a/hw/usb/meson.build b/hw/usb/meson.build index 934e4fa..ecfec0a 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('h= cd-dwc2.c')) softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c')) +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-us= b2-ctrl-regs.c')) =20 # emulated usb devices softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c')) diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-= ctrl-regs.c new file mode 100644 index 0000000..9eaa59e --- /dev/null +++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c @@ -0,0 +1,229 @@ +/* + * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for + * USB2.0 controller + * + * This module should control phy_reset, permanent device plugs, frame len= gth + * time adjust & setting of coherency paths. None of which are emulated in + * present model. + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "migration/vmstate.h" +#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h" + +#ifndef XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG +#define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0 +#endif + +REG32(BUS_FILTER, 0x30) + FIELD(BUS_FILTER, BYPASS, 0, 4) +REG32(PORT, 0x34) + FIELD(PORT, HOST_SMI_BAR_WR, 4, 1) + FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1) + FIELD(PORT, HOST_MSI_ENABLE, 2, 1) + FIELD(PORT, PWR_CTRL_PRSNT, 1, 1) + FIELD(PORT, HUB_PERM_ATTACH, 0, 1) +REG32(JITTER_ADJUST, 0x38) + FIELD(JITTER_ADJUST, FLADJ, 0, 6) +REG32(BIGENDIAN, 0x40) + FIELD(BIGENDIAN, ENDIAN_GS, 0, 1) +REG32(COHERENCY, 0x44) + FIELD(COHERENCY, USB_COHERENCY, 0, 1) +REG32(XHC_BME, 0x48) + FIELD(XHC_BME, XHC_BME, 0, 1) +REG32(REG_CTRL, 0x60) + FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1) +REG32(IR_STATUS, 0x64) + FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1) + FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1) +REG32(IR_MASK, 0x68) + FIELD(IR_MASK, HOST_SYS_ERR, 1, 1) + FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1) +REG32(IR_ENABLE, 0x6c) + FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1) + FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1) +REG32(IR_DISABLE, 0x70) + FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1) + FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1) +REG32(USB3, 0x78) + +static void ir_update_irq(VersalUsb2CtrlRegs *s) +{ + bool pending =3D s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; + qemu_set_irq(s->irq_ir, pending); +} + +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + /* + * TODO: This should also clear USBSTS.HSE field in USB XHCI register. + * May be combine both the modules. + */ + ir_update_irq(s); +} + +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] &=3D ~val; + ir_update_irq(s); + return 0; +} + +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] |=3D val; + ir_update_irq(s); + return 0; +} + +static const RegisterAccessInfo usb2_ctrl_regs_regs_info[] =3D { + { .name =3D "BUS_FILTER", .addr =3D A_BUS_FILTER, + .rsvd =3D 0xfffffff0, + },{ .name =3D "PORT", .addr =3D A_PORT, + .rsvd =3D 0xffffffe0, + },{ .name =3D "JITTER_ADJUST", .addr =3D A_JITTER_ADJUST, + .reset =3D 0x20, + .rsvd =3D 0xffffffc0, + },{ .name =3D "BIGENDIAN", .addr =3D A_BIGENDIAN, + .rsvd =3D 0xfffffffe, + },{ .name =3D "COHERENCY", .addr =3D A_COHERENCY, + .rsvd =3D 0xfffffffe, + },{ .name =3D "XHC_BME", .addr =3D A_XHC_BME, + .reset =3D 0x1, + .rsvd =3D 0xfffffffe, + },{ .name =3D "REG_CTRL", .addr =3D A_REG_CTRL, + .rsvd =3D 0xfffffffe, + },{ .name =3D "IR_STATUS", .addr =3D A_IR_STATUS, + .rsvd =3D 0xfffffffc, + .w1c =3D 0x3, + .post_write =3D ir_status_postw, + },{ .name =3D "IR_MASK", .addr =3D A_IR_MASK, + .reset =3D 0x3, + .rsvd =3D 0xfffffffc, + .ro =3D 0x3, + },{ .name =3D "IR_ENABLE", .addr =3D A_IR_ENABLE, + .rsvd =3D 0xfffffffc, + .pre_write =3D ir_enable_prew, + },{ .name =3D "IR_DISABLE", .addr =3D A_IR_DISABLE, + .rsvd =3D 0xfffffffc, + .pre_write =3D ir_disable_prew, + },{ .name =3D "USB3", .addr =3D A_USB3, + } +}; + +static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void usb2_ctrl_regs_reset_hold(Object *obj) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + + ir_update_irq(s); +} + +static const MemoryRegionOps usb2_ctrl_regs_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void usb2_ctrl_regs_init(Object *obj) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + USB2_REGS_R_MAX * 4); + reg_array =3D + register_init_block32(DEVICE(obj), usb2_ctrl_regs_regs_info, + ARRAY_SIZE(usb2_ctrl_regs_regs_info), + s->regs_info, s->regs, + &usb2_ctrl_regs_ops, + XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG, + USB2_REGS_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + 0x0, + ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_ir); +} + +static const VMStateDescription vmstate_usb2_ctrl_regs =3D { + .name =3D TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, VersalUsb2CtrlRegs, USB2_REGS_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void usb2_ctrl_regs_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D usb2_ctrl_regs_reset_init; + rc->phases.hold =3D usb2_ctrl_regs_reset_hold; + dc->vmsd =3D &vmstate_usb2_ctrl_regs; +} + +static const TypeInfo usb2_ctrl_regs_info =3D { + .name =3D TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(VersalUsb2CtrlRegs), + .class_init =3D usb2_ctrl_regs_class_init, + .instance_init =3D usb2_ctrl_regs_init, +}; + +static void usb2_ctrl_regs_register_types(void) +{ + type_register_static(&usb2_ctrl_regs_info); +} + +type_init(usb2_ctrl_regs_register_types) diff --git a/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h b/include/hw/usb/x= lnx-versal-usb2-ctrl-regs.h new file mode 100644 index 0000000..975a717 --- /dev/null +++ b/include/hw/usb/xlnx-versal-usb2-ctrl-regs.h @@ -0,0 +1,45 @@ +/* + * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for + * USB2.0 controller + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef _XLNX_USB2_REGS_H_ +#define _XLNX_USB2_REGS_H_ + +#define TYPE_XILINX_VERSAL_USB2_CTRL_REGS "xlnx.versal-usb2-ctrl-regs" + +#define XILINX_VERSAL_USB2_CTRL_REGS(obj) \ + OBJECT_CHECK(VersalUsb2CtrlRegs, (obj), TYPE_XILINX_VERSAL_USB2_CTRL_= REGS) + +#define USB2_REGS_R_MAX ((0x78 / 4) + 1) + +typedef struct VersalUsb2CtrlRegs { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_ir; + + uint32_t regs[USB2_REGS_R_MAX]; + RegisterInfo regs_info[USB2_REGS_R_MAX]; +} VersalUsb2CtrlRegs; + +#endif --=20 2.7.4 From nobody Fri Jun 14 00:29:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1606811921; cv=pass; d=zohomail.com; s=zohoarc; b=AQ17zfXtEI2gO8bTuDKYKo2EatBrIWPwYfDWb84B4CAn0g8hrvvA8p2zYAP/LXeBELCAUhEsZNu7M+uwJJ17eiKQRilMx+ZlUgk22IEiwLGDaYS3vpeQ2dpe0ATpOp5cTglF4nsZbAOCxoPQFtAztzqqDvWDSAHQf+jZZUvx8+s= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606811921; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S7Qpb1rBjWu5V9nC9IVGq25JvCpAjhfPFW6Pc25REF4=; b=QNOxtMq79jVG8lgeZPdaBfwUHHOaPgGGMkfzRhWlEza+dQXeWHwzueFel7NY5thzxwCvRUMYfsLM5y1vL8oKkbHyfYchluovbDO/ToF3Fq9MCriGDgsy8UwjUG+sWtbrbQT7A/p8sWGlggnaov3ALWy3h8BwR5q8cvac1r5XIeA= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606811921001877.1203813635083; Tue, 1 Dec 2020 00:38:41 -0800 (PST) Received: from localhost ([::1]:44636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kk1BH-0000oL-S0 for importer@patchew.org; Tue, 01 Dec 2020 03:38:39 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk17D-0005fs-Vj for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:28 -0500 Received: from mail-dm6nam12on2041.outbound.protection.outlook.com ([40.107.243.41]:37472 helo=NAM12-DM6-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk17B-00030o-1M for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:27 -0500 Received: from MN2PR11CA0003.namprd11.prod.outlook.com (2603:10b6:208:23b::8) by BN6PR02MB2500.namprd02.prod.outlook.com (2603:10b6:404:54::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.25; Tue, 1 Dec 2020 08:34:20 +0000 Received: from BL2NAM02FT038.eop-nam02.prod.protection.outlook.com (2603:10b6:208:23b:cafe::c1) by MN2PR11CA0003.outlook.office365.com (2603:10b6:208:23b::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Tue, 1 Dec 2020 08:34:20 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (149.199.62.198) by BL2NAM02FT038.mail.protection.outlook.com (10.152.77.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3611.27 via Frontend Transport; Tue, 1 Dec 2020 08:34:20 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Tue, 1 Dec 2020 00:34:11 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Tue, 1 Dec 2020 00:34:11 -0800 Received: from [10.140.6.35] (port=34286 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kk16r-0001JE-8f; Tue, 01 Dec 2020 00:34:06 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id CAF4813C089C; Tue, 1 Dec 2020 14:08:39 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=itpppkkPrHV3jEZRjGA56nnX3CePTR6e9K470hOQgUOpBq0zjbn6BmghfpSk58/wV3x3r2yiChtUhFU0GDGrgARNqCA4NLvrm1nRsuQZ8KKc/xY2zsUScjY8m0Ilj6t8j/txuJQFOnsEsjrwFqSdzNzawm5CaXRbDOJaDcVPCh8WCa4umYAJCTE4HE1pNb7eqqmbc4KhBj//QhM/HNjfSF8HdaPQK55zdy1Wudi34Gfi9BB1c2ZRWGmnkM1kXzXAWct+qMLxmTg1M/1DQCE2L1KuRMGYp582Q/dBVteE3+cNReycO3xQQrALncby2qOQ6h49RDj1FkxUN+PzFhTG3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S7Qpb1rBjWu5V9nC9IVGq25JvCpAjhfPFW6Pc25REF4=; b=NSmeIuLOO16KPWl0bjJTDCveoeJxwmY1JIOT7OKmzkbQ234aMyfa/IAUVgpMBMFyPEv/VmnoDC2aXUIyPNZpZsZbMypeb2+AGREsGbFpRLC/fwlDKLMICmiiZM3zb9UveHcrKNfGlORkKwUJLIxIZJQxs/a/kPhfFSVvAHQTYNZv4jLDNc2nMU8yJRyc4Yw+0K0jM8OIPlZAtdUc4+5sMWbbcldbC55EqdmwjOEzseqHZzTxYql+kyfCgktme+OaURcFR3RCCxx5Ufzy9ThSvUSCv4UPjuZoOkyvL+AMva+aPojK37tY8gF8S4QocRXSE6ckOA7R+cJX3MrksIjj7A== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=gmail.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=S7Qpb1rBjWu5V9nC9IVGq25JvCpAjhfPFW6Pc25REF4=; b=bMog21aeBLyxj080TvQ9vPnicwzCR6EIFXBkAD1rVkFrD1aIanKRWCJyQ8Q0zZEw8wClKMVTmNTURmjFSeqcC2tUvGEH0/ZZ+uDCdRQ4WF2sCMEZsmmF6xokFkWgXlt1cYfssX4HWa9dcOnJiqjMlSySho8PxlrYTo836viSmJ8= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch01.xlnx.xilinx.com; From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , "Gerd Hoffmann" , Edgar Iglesias , "Francisco Eduardo Iglesias" , Alistair Francis , Eduardo Habkost , Ying Fang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Vikram Garhwal , Paul Zimmerman , Sai Pavan Boddu Subject: [PATCH v14 2/4] usb: Add DWC3 model Date: Tue, 1 Dec 2020 14:08:33 +0530 Message-ID: <1606811915-8492-3-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4971f3cc-69e9-4b7d-1db5-08d895d3e625 X-MS-TrafficTypeDiagnostic: BN6PR02MB2500: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:254; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AvMDKHp8GT6+A0hUbuoFwTvkLgDbkU35P6rfFbMZd/Pq4hJfDfraoURilOovbCHLOxnu/EmMxZTLrKc5pJ0y0FWOgewC+6MzqgeIulmHanI2ips2WE+rXJ16WhJ6znXIq4CtJEU89Og0v95ay8TETpvetiVaifFzNrU2rUtyTZxr2kayBLCIr0V8kAEBrb3b2D6nTzqUHQo6W8kIiUL+YwKTCKvFrWBDlY+HXQkzjk5t6anf+6RVxw9YXwVowzjrDhrOa0CgTM1Ws8uAOrUM/BgsOi9TWj5VqU6esUEDzNN+1S31cCR1ozYFopuXJ5/unHBkjZvVcQG0lvduhq3tNHi0zU/5lqm0f5EdJoTukCKw+DKYY7Rd8yHVQCHTFNgW2p0T7/67r48oGzvpDTH2TA3mGAlGfKp+6O9iiHc1ccbsKtPEAZTGnmtcWBgu6X3Q X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch01.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(39860400002)(136003)(376002)(396003)(346002)(46966005)(30864003)(8676002)(6266002)(110136005)(316002)(42186006)(6636002)(921005)(4326008)(7416002)(82310400003)(356005)(36756003)(2906002)(70586007)(478600001)(6666004)(83380400001)(70206006)(47076004)(82740400003)(186003)(5660300002)(8936002)(7636003)(36906005)(336012)(426003)(2616005)(26005)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2020 08:34:20.3266 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4971f3cc-69e9-4b7d-1db5-08d895d3e625 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch01.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT038.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN6PR02MB2500 Received-SPF: pass client-ip=40.107.243.41; envelope-from=saipava@xilinx.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal This patch adds skeleton model of dwc3 usb controller attached to xhci-sysbus device. It defines global register space of DWC3 controller, global registers control the AXI/AHB interfaces properties, external FIFO support and event count support. All of which are unimplemented at present,we are only supporting core reset and read of ID register. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- hw/usb/Kconfig | 5 + hw/usb/hcd-dwc3.c | 677 ++++++++++++++++++++++++++++++++++++++++++= ++++ hw/usb/meson.build | 1 + include/hw/usb/hcd-dwc3.h | 56 ++++ 4 files changed, 739 insertions(+) create mode 100644 hw/usb/hcd-dwc3.c create mode 100644 include/hw/usb/hcd-dwc3.h diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 7fbae18..56da78a 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -112,3 +112,8 @@ config IMX_USBPHY bool default y depends on USB + +config USB_DWC3 + bool + select USB_XHCI_SYSBUS + select REGISTER diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c new file mode 100644 index 0000000..cf71fe4 --- /dev/null +++ b/hw/usb/hcd-dwc3.c @@ -0,0 +1,677 @@ +/* + * QEMU model of the USB DWC3 host controller emulation. + * + * This model defines global register space of DWC3 controller. Global + * registers control the AXI/AHB interfaces properties, external FIFO supp= ort + * and event count support. All of which are unimplemented at present. We = are + * only supporting core reset and read of ID register. + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/usb/hcd-dwc3.h" +#include "qapi/error.h" + +#ifndef USB_DWC3_ERR_DEBUG +#define USB_DWC3_ERR_DEBUG 0 +#endif + +#define HOST_MODE 1 +#define FIFO_LEN 0x1000 + +REG32(GSBUSCFG0, 0x00) + FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4) + FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4) + FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4) + FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4) + FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4) + FIELD(GSBUSCFG0, DATBIGEND, 11, 1) + FIELD(GSBUSCFG0, DESBIGEND, 10, 1) + FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2) + FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1) + FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1) + FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1) + FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1) + FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1) + FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1) + FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1) + FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1) +REG32(GSBUSCFG1, 0x04) + FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19) + FIELD(GSBUSCFG1, EN1KPAGE, 12, 1) + FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4) + FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8) +REG32(GTXTHRCFG, 0x08) + FIELD(GTXTHRCFG, RESERVED_31, 31, 1) + FIELD(GTXTHRCFG, RESERVED_30, 30, 1) + FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1) + FIELD(GTXTHRCFG, RESERVED_28, 28, 1) + FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4) + FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8) + FIELD(GTXTHRCFG, RESERVED_15, 15, 1) + FIELD(GTXTHRCFG, RESERVED_14, 14, 1) + FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3) + FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11) +REG32(GRXTHRCFG, 0x0c) + FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2) + FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1) + FIELD(GRXTHRCFG, RESERVED_28, 28, 1) + FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4) + FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5) + FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3) + FIELD(GRXTHRCFG, RESERVED_15, 15, 1) + FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2) + FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13) +REG32(GCTL, 0x10) + FIELD(GCTL, PWRDNSCALE, 19, 13) + FIELD(GCTL, MASTERFILTBYPASS, 18, 1) + FIELD(GCTL, BYPSSETADDR, 17, 1) + FIELD(GCTL, U2RSTECN, 16, 1) + FIELD(GCTL, FRMSCLDWN, 14, 2) + FIELD(GCTL, PRTCAPDIR, 12, 2) + FIELD(GCTL, CORESOFTRESET, 11, 1) + FIELD(GCTL, U1U2TIMERSCALE, 9, 1) + FIELD(GCTL, DEBUGATTACH, 8, 1) + FIELD(GCTL, RAMCLKSEL, 6, 2) + FIELD(GCTL, SCALEDOWN, 4, 2) + FIELD(GCTL, DISSCRAMBLE, 3, 1) + FIELD(GCTL, U2EXIT_LFPS, 2, 1) + FIELD(GCTL, GBLHIBERNATIONEN, 1, 1) + FIELD(GCTL, DSBLCLKGTNG, 0, 1) +REG32(GPMSTS, 0x14) +REG32(GSTS, 0x18) + FIELD(GSTS, CBELT, 20, 12) + FIELD(GSTS, RESERVED_19_12, 12, 8) + FIELD(GSTS, SSIC_IP, 11, 1) + FIELD(GSTS, OTG_IP, 10, 1) + FIELD(GSTS, BC_IP, 9, 1) + FIELD(GSTS, ADP_IP, 8, 1) + FIELD(GSTS, HOST_IP, 7, 1) + FIELD(GSTS, DEVICE_IP, 6, 1) + FIELD(GSTS, CSRTIMEOUT, 5, 1) + FIELD(GSTS, BUSERRADDRVLD, 4, 1) + FIELD(GSTS, RESERVED_3_2, 2, 2) + FIELD(GSTS, CURMOD, 0, 2) +REG32(GUCTL1, 0x1c) + FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1) +REG32(GSNPSID, 0x20) +REG32(GGPIO, 0x24) + FIELD(GGPIO, GPO, 16, 16) + FIELD(GGPIO, GPI, 0, 16) +REG32(GUID, 0x28) +REG32(GUCTL, 0x2c) + FIELD(GUCTL, REFCLKPER, 22, 10) + FIELD(GUCTL, NOEXTRDL, 21, 1) + FIELD(GUCTL, RESERVED_20_18, 18, 3) + FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1) + FIELD(GUCTL, RESBWHSEPS, 16, 1) + FIELD(GUCTL, RESERVED_15, 15, 1) + FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1) + FIELD(GUCTL, ENOVERLAPCHK, 13, 1) + FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1) + FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1) + FIELD(GUCTL, DTCT, 9, 2) + FIELD(GUCTL, DTFT, 0, 9) +REG32(GBUSERRADDRLO, 0x30) +REG32(GBUSERRADDRHI, 0x34) +REG32(GHWPARAMS0, 0x40) + FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2) + FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3) + FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3) +REG32(GHWPARAMS1, 0x44) + FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2) + FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2) + FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6) + FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3) +REG32(GHWPARAMS2, 0x48) +REG32(GHWPARAMS3, 0x4c) + FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8) + FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5) + FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6) + FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2) +REG32(GHWPARAMS4, 0x50) + FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2) + FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2) + FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6) +REG32(GHWPARAMS5, 0x54) + FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4) + FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4) +REG32(GHWPARAMS6, 0x58) + FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16) + FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1) + FIELD(GHWPARAMS6, BCSUPPORT, 14, 1) + FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1) + FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1) + FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1) + FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2) + FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6) +REG32(GHWPARAMS7, 0x5c) + FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16) + FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16) +REG32(GDBGFIFOSPACE, 0x60) + FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16) + FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7) + FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9) +REG32(GUCTL2, 0x9c) + FIELD(GUCTL2, RESERVED_31_26, 26, 6) + FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7) + FIELD(GUCTL2, NOLOWPWRDUR, 15, 4) + FIELD(GUCTL2, RST_ACTBITLATER, 14, 1) + FIELD(GUCTL2, RESERVED_13, 13, 1) + FIELD(GUCTL2, DISABLECFC, 11, 1) +REG32(GUSB2PHYCFG, 0x100) + FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1) + FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1) + FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1) + FIELD(GUSB2PHYCFG, LSTRD, 22, 3) + FIELD(GUSB2PHYCFG, LSIPD, 19, 3) + FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1) + FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1) + FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1) + FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1) + FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1) + FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4) + FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1) + FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1) + FIELD(GUSB2PHYCFG, PHYSEL, 7, 1) + FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1) + FIELD(GUSB2PHYCFG, FSINTF, 5, 1) + FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1) + FIELD(GUSB2PHYCFG, PHYIF, 3, 1) + FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3) +REG32(GUSB2I2CCTL, 0x140) +REG32(GUSB2PHYACC_ULPI, 0x180) + FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5) + FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1) + FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1) + FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1) + FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1) + FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1) + FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6) + FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8) + FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8) +REG32(GTXFIFOSIZ0, 0x200) + FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ1, 0x204) + FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ2, 0x208) + FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ3, 0x20c) + FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ4, 0x210) + FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ5, 0x214) + FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ0, 0x280) + FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ1, 0x284) + FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ2, 0x288) + FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16) +REG32(GEVNTADRLO_0, 0x300) +REG32(GEVNTADRHI_0, 0x304) +REG32(GEVNTSIZ_0, 0x308) + FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_0, 0x30c) + FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_1, 0x310) +REG32(GEVNTADRHI_1, 0x314) +REG32(GEVNTSIZ_1, 0x318) + FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_1, 0x31c) + FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_2, 0x320) +REG32(GEVNTADRHI_2, 0x324) +REG32(GEVNTSIZ_2, 0x328) + FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_2, 0x32c) + FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_3, 0x330) +REG32(GEVNTADRHI_3, 0x334) +REG32(GEVNTSIZ_3, 0x338) + FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_3, 0x33c) + FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16) +REG32(GHWPARAMS8, 0x500) +REG32(GTXFIFOPRIDEV, 0x510) + FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26) + FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6) +REG32(GTXFIFOPRIHST, 0x518) + FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29) + FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3) +REG32(GRXFIFOPRIHST, 0x51c) + FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29) + FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3) +REG32(GDMAHLRATIO, 0x524) + FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19) + FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5) + FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3) + FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5) +REG32(GFLADJ, 0x530) + FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1) + FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7) + FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1) + FIELD(GFLADJ, RESERVED_22, 22, 1) + FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14) + FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1) + FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6) + +#define DWC3_GLOBAL_OFFSET 0xC100 +static void reset_csr(USBDWC3 * s) +{ + int i =3D 0; + /* + * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUI= D, + * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY + * register as we don't implement them. + */ + for (i =3D 0; i < USB_DWC3_R_MAX; i++) { + switch (i) { + case R_GCTL: + break; + case R_GSTS: + break; + case R_GSNPSID: + break; + case R_GGPIO: + break; + case R_GUID: + break; + case R_GUCTL: + break; + case R_GHWPARAMS0...R_GHWPARAMS7: + break; + case R_GHWPARAMS8: + break; + default: + register_reset(&s->regs_info[i]); + break; + } + } + + xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); +} + +static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64) +{ + USBDWC3 *s =3D USB_DWC3(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) { + reset_csr(s); + } +} + +static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64) +{ + USBDWC3 *s =3D USB_DWC3(reg->opaque); + + s->regs[R_GUID] =3D s->cfg.dwc_usb3_user; +} + +static const RegisterAccessInfo usb_dwc3_regs_info[] =3D { + { .name =3D "GSBUSCFG0", .addr =3D A_GSBUSCFG0, + .ro =3D 0xf300, + .unimp =3D 0xffffffff, + },{ .name =3D "GSBUSCFG1", .addr =3D A_GSBUSCFG1, + .reset =3D 0x300, + .ro =3D 0xffffe0ff, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXTHRCFG", .addr =3D A_GTXTHRCFG, + .ro =3D 0xd000ffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXTHRCFG", .addr =3D A_GRXTHRCFG, + .ro =3D 0xd007e000, + .unimp =3D 0xffffffff, + },{ .name =3D "GCTL", .addr =3D A_GCTL, + .reset =3D 0x30c13004, .post_write =3D usb_dwc3_gctl_postw, + },{ .name =3D "GPMSTS", .addr =3D A_GPMSTS, + .ro =3D 0xfffffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GSTS", .addr =3D A_GSTS, + .reset =3D 0x7e800000, + .ro =3D 0xffffffcf, + .w1c =3D 0x30, + .unimp =3D 0xffffffff, + },{ .name =3D "GUCTL1", .addr =3D A_GUCTL1, + .reset =3D 0x198a, + .ro =3D 0x7800, + .unimp =3D 0xffffffff, + },{ .name =3D "GSNPSID", .addr =3D A_GSNPSID, + .reset =3D 0x5533330a, + .ro =3D 0xffffffff, + },{ .name =3D "GGPIO", .addr =3D A_GGPIO, + .ro =3D 0xffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GUID", .addr =3D A_GUID, + .reset =3D 0x12345678, .post_write =3D usb_dwc3_guid_postw, + },{ .name =3D "GUCTL", .addr =3D A_GUCTL, + .reset =3D 0x0c808010, + .ro =3D 0x1c8000, + .unimp =3D 0xffffffff, + },{ .name =3D "GBUSERRADDRLO", .addr =3D A_GBUSERRADDRLO, + .ro =3D 0xffffffff, + },{ .name =3D "GBUSERRADDRHI", .addr =3D A_GBUSERRADDRHI, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS0", .addr =3D A_GHWPARAMS0, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS1", .addr =3D A_GHWPARAMS1, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS2", .addr =3D A_GHWPARAMS2, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS3", .addr =3D A_GHWPARAMS3, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS4", .addr =3D A_GHWPARAMS4, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS5", .addr =3D A_GHWPARAMS5, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS6", .addr =3D A_GHWPARAMS6, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS7", .addr =3D A_GHWPARAMS7, + .ro =3D 0xffffffff, + },{ .name =3D "GDBGFIFOSPACE", .addr =3D A_GDBGFIFOSPACE, + .reset =3D 0xa0000, + .ro =3D 0xfffffe00, + .unimp =3D 0xffffffff, + },{ .name =3D "GUCTL2", .addr =3D A_GUCTL2, + .reset =3D 0x40d, + .ro =3D 0x2000, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2PHYCFG", .addr =3D A_GUSB2PHYCFG, + .reset =3D 0x40102410, + .ro =3D 0x1e014030, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2I2CCTL", .addr =3D A_GUSB2I2CCTL, + .ro =3D 0xffffffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2PHYACC_ULPI", .addr =3D A_GUSB2PHYACC_ULPI, + .ro =3D 0xfd000000, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ0", .addr =3D A_GTXFIFOSIZ0, + .reset =3D 0x2c7000a, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ1", .addr =3D A_GTXFIFOSIZ1, + .reset =3D 0x2d10103, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ2", .addr =3D A_GTXFIFOSIZ2, + .reset =3D 0x3d40103, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ3", .addr =3D A_GTXFIFOSIZ3, + .reset =3D 0x4d70083, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ4", .addr =3D A_GTXFIFOSIZ4, + .reset =3D 0x55a0083, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ5", .addr =3D A_GTXFIFOSIZ5, + .reset =3D 0x5dd0083, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ0", .addr =3D A_GRXFIFOSIZ0, + .reset =3D 0x1c20105, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ1", .addr =3D A_GRXFIFOSIZ1, + .reset =3D 0x2c70000, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ2", .addr =3D A_GRXFIFOSIZ2, + .reset =3D 0x2c70000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_0", .addr =3D A_GEVNTADRLO_0, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_0", .addr =3D A_GEVNTADRHI_0, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_0", .addr =3D A_GEVNTSIZ_0, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_0", .addr =3D A_GEVNTCOUNT_0, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_1", .addr =3D A_GEVNTADRLO_1, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_1", .addr =3D A_GEVNTADRHI_1, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_1", .addr =3D A_GEVNTSIZ_1, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_1", .addr =3D A_GEVNTCOUNT_1, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_2", .addr =3D A_GEVNTADRLO_2, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_2", .addr =3D A_GEVNTADRHI_2, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_2", .addr =3D A_GEVNTSIZ_2, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_2", .addr =3D A_GEVNTCOUNT_2, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_3", .addr =3D A_GEVNTADRLO_3, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_3", .addr =3D A_GEVNTADRHI_3, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_3", .addr =3D A_GEVNTSIZ_3, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_3", .addr =3D A_GEVNTCOUNT_3, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GHWPARAMS8", .addr =3D A_GHWPARAMS8, + .ro =3D 0xffffffff, + },{ .name =3D "GTXFIFOPRIDEV", .addr =3D A_GTXFIFOPRIDEV, + .ro =3D 0xffffffc0, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOPRIHST", .addr =3D A_GTXFIFOPRIHST, + .ro =3D 0xfffffff8, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOPRIHST", .addr =3D A_GRXFIFOPRIHST, + .ro =3D 0xfffffff8, + .unimp =3D 0xffffffff, + },{ .name =3D "GDMAHLRATIO", .addr =3D A_GDMAHLRATIO, + .ro =3D 0xffffe0e0, + .unimp =3D 0xffffffff, + },{ .name =3D "GFLADJ", .addr =3D A_GFLADJ, + .reset =3D 0xc83f020, + .rsvd =3D 0x40, + .ro =3D 0x400040, + .unimp =3D 0xffffffff, + } +}; + +static void usb_dwc3_reset(DeviceState *dev) +{ + USBDWC3 *s =3D USB_DWC3(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + switch (i) { + case R_GHWPARAMS0...R_GHWPARAMS7: + break; + case R_GHWPARAMS8: + break; + default: + register_reset(&s->regs_info[i]); + }; + } + + xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); +} + +static const MemoryRegionOps usb_dwc3_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void usb_dwc3_realize(DeviceState *dev, Error **errp) +{ + USBDWC3 *s =3D USB_DWC3(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + Error *err =3D NULL; + + sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err); + if (err) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->iomem, 0, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->sysbus_xhci), 0)); + sysbus_init_mmio(sbd, &s->iomem); + + /* + * Device Configuration + */ + s->regs[R_GHWPARAMS0] =3D 0x40204048 | s->cfg.mode; + s->regs[R_GHWPARAMS1] =3D 0x222493b; + s->regs[R_GHWPARAMS2] =3D 0x12345678; + s->regs[R_GHWPARAMS3] =3D 0x618c088; + s->regs[R_GHWPARAMS4] =3D 0x47822004; + s->regs[R_GHWPARAMS5] =3D 0x4202088; + s->regs[R_GHWPARAMS6] =3D 0x7850c20; + s->regs[R_GHWPARAMS7] =3D 0x0; + s->regs[R_GHWPARAMS8] =3D 0x478; +} + +static void usb_dwc3_init(Object *obj) +{ + USBDWC3 *s =3D USB_DWC3(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, DWC3_SIZE); + reg_array =3D + register_init_block32(DEVICE(obj), usb_dwc3_regs_info, + ARRAY_SIZE(usb_dwc3_regs_info), + s->regs_info, s->regs, + &usb_dwc3_ops, + USB_DWC3_ERR_DEBUG, + USB_DWC3_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + DWC3_GLOBAL_OFFSET, + ®_array->mem); + object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci, + TYPE_XHCI_SYSBUS); + qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj); + + s->cfg.mode =3D HOST_MODE; +} + +static Property usb_dwc3_properties[] =3D { + DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user, + 0x12345678), + DEFINE_PROP_END_OF_LIST(), +}; + +static void usb_dwc3_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D usb_dwc3_reset; + dc->realize =3D usb_dwc3_realize; + device_class_set_props(dc, usb_dwc3_properties); +} + +static const TypeInfo usb_dwc3_info =3D { + .name =3D TYPE_USB_DWC3, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(USBDWC3), + .class_init =3D usb_dwc3_class_init, + .instance_init =3D usb_dwc3_init, +}; + +static void usb_dwc3_register_types(void) +{ + type_register_static(&usb_dwc3_info); +} + +type_init(usb_dwc3_register_types) diff --git a/hw/usb/meson.build b/hw/usb/meson.build index ecfec0a..433c27e 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -26,6 +26,7 @@ softmmu_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: f= iles('hcd-xhci-sysbus.c softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c= ')) softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c')) softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c')) +softmmu_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c')) =20 softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h new file mode 100644 index 0000000..791776a --- /dev/null +++ b/include/hw/usb/hcd-dwc3.h @@ -0,0 +1,56 @@ +/* + * QEMU model of the USB DWC3 host controller emulation. + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written by Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#ifndef HCD_DWC3_H +#define HCD_DWC3_H + +#include "hw/usb/hcd-xhci.h" +#include "hw/usb/hcd-xhci-sysbus.h" + +#define TYPE_USB_DWC3 "usb_dwc3" + +#define USB_DWC3(obj) \ + OBJECT_CHECK(USBDWC3, (obj), TYPE_USB_DWC3) + +#define USB_DWC3_R_MAX ((0x530 / 4) + 1) +#define DWC3_SIZE 0x10000 + +typedef struct USBDWC3 { + SysBusDevice parent_obj; + MemoryRegion iomem; + MemoryRegion fifos; + XHCISysbusState sysbus_xhci; + + uint32_t regs[USB_DWC3_R_MAX]; + RegisterInfo regs_info[USB_DWC3_R_MAX]; + + struct { + uint8_t mode; + uint32_t dwc_usb3_user; + } cfg; + +} USBDWC3; + +#endif --=20 2.7.4 From nobody Fri Jun 14 00:29:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1606812026; cv=pass; d=zohomail.com; s=zohoarc; b=k2XKg8SpuLqWioQJe0G+Bx8WVj0Hy0EopYKg9L7gl5Zm8gHaZ/Qetb5wzyt0C0NYiiWt0qxOpu3zkON5keWEUczpX98BZoPc2lWj832GX5yuPO4T0FOW+jLPIIctG9Rsn6O0z36KF2VdR5Qgj7RO/tglS7O9woix9M5SsIymlYk= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606812026; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KWu8oaaQLkanZvSPmemhH6Bgs1py2VQfkZpxfuL82us=; b=GVcITN91O2WdLOr4f7WgoQ5Al4cuqcco3KJxBFRqYAaeyt8/Tyj00pZSn0dhh/VS+Ktu09pDW1uDJAu4c2IlSJ/6q+IZ2anZaUr1hmDBbeXnQlHVr9JPTn7aQtLKHdiIrm5GcC9LNHs6HQJvnkkch324Fr5peJLlNKEFh6e2/Ig= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606812026759483.857576129614; Tue, 1 Dec 2020 00:40:26 -0800 (PST) Received: from localhost ([::1]:49462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kk1Cz-0002kn-Gc for importer@patchew.org; Tue, 01 Dec 2020 03:40:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40118) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk17O-0005qg-Bh for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:38 -0500 Received: from mail-co1nam11on2058.outbound.protection.outlook.com ([40.107.220.58]:39808 helo=NAM11-CO1-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk17M-00033f-66 for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:38 -0500 Received: from CY1PR07CA0039.namprd07.prod.outlook.com (2a01:111:e400:c60a::49) by BY5PR02MB6594.namprd02.prod.outlook.com (2603:10b6:a03:20b::18) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.25; Tue, 1 Dec 2020 08:34:33 +0000 Received: from CY1NAM02FT023.eop-nam02.prod.protection.outlook.com (2a01:111:e400:c60a:cafe::7d) by CY1PR07CA0039.outlook.office365.com (2a01:111:e400:c60a::49) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3632.17 via Frontend Transport; Tue, 1 Dec 2020 08:34:33 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by CY1NAM02FT023.mail.protection.outlook.com (10.152.74.237) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3611.27 via Frontend Transport; Tue, 1 Dec 2020 08:34:33 +0000 Received: from xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Tue, 1 Dec 2020 00:34:10 -0800 Received: from smtp.xilinx.com (172.19.127.95) by xsj-pvapexch01.xlnx.xilinx.com (172.19.86.40) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Tue, 1 Dec 2020 00:34:10 -0800 Received: from [10.140.6.35] (port=34288 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kk16r-0001JF-9h; Tue, 01 Dec 2020 00:34:05 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id D271213C08A3; Tue, 1 Dec 2020 14:08:39 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Rw6Kqqc9YQull3De1gHa1dbHhFKdmJ4kCV2bzc4tqK47OSYMigAD4qzJqndgkaXt2v2Rge4vcrMuVqKtytO2XlPs/NzMbLJCHziG1hnqfnXpXbNusYr+lwik+Zx/uxBTURDOWw3Xgi9pkYnDS71juLzHhfMBt0TlKbaRcGpxLg0TqqAUOCAxPu9tS4jfwtD30979M766/b8MOm822LVnbVljEu/gh2I5grzF9TjNLOocJA1jHEOmo/TrIvKninNuQ9zHVI6wKhh7Ej1hJVPyAFO14+iqcUFXfgyiv9Ji3KAVywEKj1wsDNnKlLLFdR51mbE0fhNGGZdACqby7j1EPA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KWu8oaaQLkanZvSPmemhH6Bgs1py2VQfkZpxfuL82us=; b=U08PBFKDbCyeTK4rJq3f2T1SOw9jdjFId4KSHW6/fZDE0Kw83wMai0KPFLHhRbO93h10O4ryekqq95UbmJMgPuFfEAbfqzPySTlZFv2vZOdGvojAGy+jjmr0MMCIQFnJrfEFssxUgx4E8puezeHUen2nHL8L8MkKUrtpahsts2hN7Zofn+3+eynalpl21luFymiwGfFuxVkWqDMsexvbuCA9tsT1sZUt8FENQa7y2NVXZ1jOufuZeyQRw94h3oNZVzXDqrxwJPMg1IpUhok+/B+YCQveRGbW04Xp55U4k8lS51HPDUNzT1F8iN+Ol5bh4Epwf2Ecd4dUl+6T2ZGydQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=gmail.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=KWu8oaaQLkanZvSPmemhH6Bgs1py2VQfkZpxfuL82us=; b=aYw2O3Yj6/21M5I33+HS7F0kAI2nyH597p7u0aTVPNaLrLMEGKffltKQ3NsguOEkvhLfkIfLi+mEaGzTwSqrl+A/71avt1OqMgXbSGalD11KNyAmLsdIypiHnac1ih/UxqtE3UcriayV7a7VWFbbdbFGR8Hi0Uncrs/U5SjSY/k= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , "Gerd Hoffmann" , Edgar Iglesias , "Francisco Eduardo Iglesias" , Alistair Francis , Eduardo Habkost , Ying Fang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Vikram Garhwal , Paul Zimmerman , Sai Pavan Boddu Subject: [PATCH v14 3/4] usb: xlnx-usb-subsystem: Add xilinx usb subsystem Date: Tue, 1 Dec 2020 14:08:34 +0530 Message-ID: <1606811915-8492-4-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e309c200-cc47-4e2b-a107-08d895d3edee X-MS-TrafficTypeDiagnostic: BY5PR02MB6594: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:2657; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: tTKndWvtZ8MF/TRbHKuBPzrkEo2BIx127PAXGu2X+a3HGSbF2vcA6QxqnPrVFTK2pvGhgHYexdF8a85JhvrEXKVUhYR9eHzqEUyj2nJ6OKZdXEzBArhRAUftKwhkokZqGsgzF+YhzI5ncVwts2VousdIgwDlWF3L2C91Q3zO6L6UwN5oY4sRX469zZema6BBGRngFsgvYZAvKrWL/QZnbYZPC8thTzGHeuaYqFkt8AbDZArmaIofmlK/28oZqRPhQjnA2jesnxP3E2dDuEy2/HXBi42LaZc6wFyFjuhtiYvVwVbVSajwg8lUk2z24C7omKjjzf+lEKzJ5E2CxeJATTjeQhVuroxmDcrjKLkpr850tK/Pk9Ze3Jh0UU9wKCPDDS4kjx0Y/SNbR/cJu8cBltvqwnlvdAgztvha+6v72RLklkLCRaDZnAV9SzCnh49J X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(39860400002)(346002)(376002)(136003)(396003)(46966005)(70586007)(83380400001)(36756003)(6636002)(19627235002)(6666004)(921005)(47076004)(5660300002)(82740400003)(356005)(7636003)(82310400003)(42186006)(8676002)(4326008)(2616005)(336012)(426003)(110136005)(2906002)(70206006)(26005)(478600001)(316002)(7416002)(186003)(36906005)(8936002)(6266002)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2020 08:34:33.4782 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e309c200-cc47-4e2b-a107-08d895d3edee X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT023.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR02MB6594 Received-SPF: pass client-ip=40.107.220.58; envelope-from=saipava@xilinx.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This model is a top level integration wrapper for hcd-dwc3 and versal-usb2-ctrl-regs modules, this is used by xilinx versal soc's and future xilinx usb subsystems would also be part of it. Signed-off-by: Sai Pavan Boddu Reviewed-by: Peter Maydell --- hw/usb/Kconfig | 5 ++ hw/usb/meson.build | 1 + hw/usb/xlnx-usb-subsystem.c | 94 +++++++++++++++++++++++++++++++++= ++++ include/hw/usb/xlnx-usb-subsystem.h | 45 ++++++++++++++++++ 4 files changed, 145 insertions(+) create mode 100644 hw/usb/xlnx-usb-subsystem.c create mode 100644 include/hw/usb/xlnx-usb-subsystem.h diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 56da78a..40093d7 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -117,3 +117,8 @@ config USB_DWC3 bool select USB_XHCI_SYSBUS select REGISTER + +config XLNX_USB_SUBSYS + bool + default y if XLNX_VERSAL + select USB_DWC3 diff --git a/hw/usb/meson.build b/hw/usb/meson.build index 433c27e..f46c6b6 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -32,6 +32,7 @@ softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('t= usb6010.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) softmmu_ss.add(when: 'CONFIG_IMX_USBPHY', if_true: files('imx-usb-phy.c')) specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-us= b2-ctrl-regs.c')) +specific_ss.add(when: 'CONFIG_XLNX_USB_SUBSYS', if_true: files('xlnx-usb-s= ubsystem.c')) =20 # emulated usb devices softmmu_ss.add(when: 'CONFIG_USB', if_true: files('dev-hub.c')) diff --git a/hw/usb/xlnx-usb-subsystem.c b/hw/usb/xlnx-usb-subsystem.c new file mode 100644 index 0000000..5682573 --- /dev/null +++ b/hw/usb/xlnx-usb-subsystem.c @@ -0,0 +1,94 @@ +/* + * QEMU model of the Xilinx usb subsystem + * + * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" +#include "hw/usb/xlnx-usb-subsystem.h" + +static void versal_usb2_realize(DeviceState *dev, Error **errp) +{ + VersalUsb2 *s =3D VERSAL_USB2(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + Error *err =3D NULL; + + sysbus_realize(SYS_BUS_DEVICE(&s->dwc3), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_realize(SYS_BUS_DEVICE(&s->usb2Ctrl), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_init_mmio(sbd, &s->dwc3_mr); + sysbus_init_mmio(sbd, &s->usb2Ctrl_mr); + qdev_pass_gpios(DEVICE(&s->dwc3.sysbus_xhci), dev, SYSBUS_DEVICE_GPIO_= IRQ); +} + +static void versal_usb2_init(Object *obj) +{ + VersalUsb2 *s =3D VERSAL_USB2(obj); + + object_initialize_child(obj, "versal.dwc3", &s->dwc3, + TYPE_USB_DWC3); + object_initialize_child(obj, "versal.usb2-ctrl", &s->usb2Ctrl, + TYPE_XILINX_VERSAL_USB2_CTRL_REGS); + memory_region_init_alias(&s->dwc3_mr, obj, "versal.dwc3_alias", + &s->dwc3.iomem, 0, DWC3_SIZE); + memory_region_init_alias(&s->usb2Ctrl_mr, obj, "versal.usb2Ctrl_alias", + &s->usb2Ctrl.iomem, 0, USB2_REGS_R_MAX * 4); + qdev_alias_all_properties(DEVICE(&s->dwc3), obj); + qdev_alias_all_properties(DEVICE(&s->dwc3.sysbus_xhci), obj); + object_property_add_alias(obj, "dma", OBJECT(&s->dwc3.sysbus_xhci), "d= ma"); +} + +static void versal_usb2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D versal_usb2_realize; +} + +static const TypeInfo versal_usb2_info =3D { + .name =3D TYPE_XILINX_VERSAL_USB2, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(VersalUsb2), + .class_init =3D versal_usb2_class_init, + .instance_init =3D versal_usb2_init, +}; + +static void versal_usb_types(void) +{ + type_register_static(&versal_usb2_info); +} + +type_init(versal_usb_types) diff --git a/include/hw/usb/xlnx-usb-subsystem.h b/include/hw/usb/xlnx-usb-= subsystem.h new file mode 100644 index 0000000..739bef7 --- /dev/null +++ b/include/hw/usb/xlnx-usb-subsystem.h @@ -0,0 +1,45 @@ +/* + * QEMU model of the Xilinx usb subsystem + * + * Copyright (c) 2020 Xilinx Inc. Sai Pavan Boddu + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef _XLNX_VERSAL_USB_SUBSYSTEM_H_ +#define _XLNX_VERSAL_USB_SUBSYSTEM_H_ + +#include "hw/usb/xlnx-versal-usb2-ctrl-regs.h" +#include "hw/usb/hcd-dwc3.h" + +#define TYPE_XILINX_VERSAL_USB2 "xlnx.versal-usb2" + +#define VERSAL_USB2(obj) \ + OBJECT_CHECK(VersalUsb2, (obj), TYPE_XILINX_VERSAL_USB2) + +typedef struct VersalUsb2 { + SysBusDevice parent_obj; + MemoryRegion dwc3_mr; + MemoryRegion usb2Ctrl_mr; + + VersalUsb2CtrlRegs usb2Ctrl; + USBDWC3 dwc3; +} VersalUsb2; + +#endif --=20 2.7.4 From nobody Fri Jun 14 00:29:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1606811910; cv=pass; d=zohomail.com; s=zohoarc; b=leBxxI4xLn4pFpCtViSozC6vH0WeVzU0h+z8KDuBSMZZD6XvMinbaBEFBIX+f10Mce45T+8LwDSrMzW1ApUct91E4ooNOrsk+Lcg2fWns0V4WE1yYCOutygjKEVE7q82LLwE31JppZH5AHt1Ka6bF1cu+M6AdLJ3SjOJi/lMmOY= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1606811910; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zcFd3c1cxvwcGg9DlG/yuYAwKWO1vwg5OcdMwFn/vc0=; b=dshTCavgyzi99IQ1O+hRuo8XuPaCrMF6RyrJe2gzssHsXUw9LitXb3mzJ7K2bUf/rcucw28vjrGRjGs3Do5+6FHth8NInqVP9IWBFKQ2trwmayXRan8ruEjKTas1jC/vvydB6EnPcGpcHEOp+++pjsu2w1k7lbYTKwT+0+Mp2j0= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1606811910108497.6652105275315; Tue, 1 Dec 2020 00:38:30 -0800 (PST) Received: from localhost ([::1]:44166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kk1B6-0000ch-UW for importer@patchew.org; Tue, 01 Dec 2020 03:38:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk17N-0005pA-Hs for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:37 -0500 Received: from mail-bn7nam10on2080.outbound.protection.outlook.com ([40.107.92.80]:53473 helo=NAM10-BN7-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kk17L-00032p-Aw for qemu-devel@nongnu.org; Tue, 01 Dec 2020 03:34:37 -0500 Received: from CY4PR01CA0007.prod.exchangelabs.com (2603:10b6:903:1f::17) by SN6PR02MB5629.namprd02.prod.outlook.com (2603:10b6:805:f0::20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.25; Tue, 1 Dec 2020 08:34:31 +0000 Received: from CY1NAM02FT044.eop-nam02.prod.protection.outlook.com (2603:10b6:903:1f:cafe::63) by CY4PR01CA0007.outlook.office365.com (2603:10b6:903:1f::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3611.20 via Frontend Transport; Tue, 1 Dec 2020 08:34:31 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (149.199.62.198) by CY1NAM02FT044.mail.protection.outlook.com (10.152.75.137) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3611.27 via Frontend Transport; Tue, 1 Dec 2020 08:34:31 +0000 Received: from xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.1913.5; Tue, 1 Dec 2020 00:34:05 -0800 Received: from smtp.xilinx.com (172.19.127.96) by xsj-pvapexch02.xlnx.xilinx.com (172.19.86.41) with Microsoft SMTP Server id 15.1.1913.5 via Frontend Transport; Tue, 1 Dec 2020 00:34:05 -0800 Received: from [10.140.6.35] (port=34290 helo=xhdsaipava40.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.90) (envelope-from ) id 1kk16r-0000KC-B8; Tue, 01 Dec 2020 00:34:05 -0800 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id DA5D513C08A7; Tue, 1 Dec 2020 14:08:39 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Skwzx3Nas2l9nVKHLM+q6I+r25LjfDGdG5hLMzZH/UG7ltRpy9p7sy5bI+GO/W7l734WKS1SQsEG9XgoFZRz+gDNj18K5jukzUCBBOXK90jAYKCa1nLbMT8YIG/fTSJJRpW3qU0ubn0AxhXdut8AtarP1Pa9/LuuioFh+udn4xWPeZhiGxPLUR/RpOgt/lJBzKti+Lr6GeAoihDS8jFVS3SJzly6Z5os3/8o3y1e2+FaAeKE+Ts6ejmYRzMH8B5rOda3J9ntRhrdvIDmhSMvbi841kKIYdW1+0Yxwn2ITMZky3HSjYMYVwfzzFFScpqB/HiGIVwtdbBe8AnUevNljA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zcFd3c1cxvwcGg9DlG/yuYAwKWO1vwg5OcdMwFn/vc0=; b=PKqytnuvFNH8QMqov9N6LbdaMjF16pVLNqVo93+mgOkmbV0Hmzc+sbXrk6iOJDJ2DlRCKoIVesSzfrnBa2DrCTnh6PIaYxMiPczVoEmplEf5j1ugM3c38JIRfKP1uH1eu6XfCJYsPpGUeVInfQih9uhxbKZBL/XnhhylxAKWhQ/0P3rHKhAdwut4OI2yDiTkj70kKsMiUok2whuK3Bc+qm0afwGOLJZeSJaItD4obGuxKqA18noNVB6TumbS0rY9uxySvAaE5al6vlvzCiL8efbD9j2BTuJXOeUlg0clRAZbQ8X/qIOgQsOb1HRurq1ibdjgtxm5JJiAq1fkETt58Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.62.198) smtp.rcpttodomain=gmail.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=zcFd3c1cxvwcGg9DlG/yuYAwKWO1vwg5OcdMwFn/vc0=; b=fxEJ6GGnXsiRiIp1pAyw4tU+52Fsq4smytUXdTDf7pOxYPQ35Cgq1MlsF3U1n8+On8cQm2hShT8wEAIZizK0dNMzPV6im6eY/42YZ156UGtUtRpVcpX5f2x8HYznDKdxhTfBrp6z5wYmZ05Y4Rp2CwCkgwwaBsihf0qeS1Cef6Y= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.62.198) smtp.mailfrom=xilinx.com; gmail.com; dkim=none (message not signed) header.d=none;gmail.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.62.198 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.62.198; helo=xsj-pvapexch02.xlnx.xilinx.com; From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Paolo Bonzini , "Gerd Hoffmann" , Edgar Iglesias , "Francisco Eduardo Iglesias" , Alistair Francis , Eduardo Habkost , Ying Fang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Vikram Garhwal , Paul Zimmerman , Sai Pavan Boddu Subject: [PATCH v14 4/4] arm: xlnx-versal: Connect usb to virt-versal Date: Tue, 1 Dec 2020 14:08:35 +0530 Message-ID: <1606811915-8492-5-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1606811915-8492-1-git-send-email-sai.pavan.boddu@xilinx.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a4f92f82-005a-4787-d107-08d895d3ec98 X-MS-TrafficTypeDiagnostic: SN6PR02MB5629: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:142; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YUBdN7aGkChDbQ6Qe/TprUwQbGg19a95QoNPsnSmPgKIYkwPL614BmgH+PunVJcsP1SbLJfcoAK5VwgHkUIf+FDA56Nux41LD+1Clz23e44D/zZTluFs9A0+oiemjBVrDVlnSYH3jywhLQhY1wEAIW5g2FzPjQ9Ik/1C9wkzziVgHcFZKXYIiM+Kryv9cxklLAhd5NzcyGn+ITLSLvavN43Y93NXHUminFUXoBCD4iuWYIQVemc/BDxMYrW/y9OraAMtgBvaaeMhRUktR2Ei3p6lh1K1kBrCCJBXc5BKefiE8R43+/FEtrYumQ6LzOGBBOHwiXraKCY3H8hAX2CvZHvGLTfhc6DyUfaw1Pb59nz1xVKf+Kj5PrmYT0/2Z+NgthihgKqQAlExenfc4SV76z17N6il4swLieRW63VWK1Zn2leoFJ3/Uv5YeuUNZqga X-Forefront-Antispam-Report: CIP:149.199.62.198; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapexch02.xlnx.xilinx.com; PTR:unknown-62-198.xilinx.com; CAT:NONE; SFS:(4636009)(376002)(136003)(346002)(39860400002)(396003)(46966005)(336012)(6266002)(6666004)(36756003)(426003)(82740400003)(316002)(8936002)(478600001)(42186006)(2906002)(36906005)(47076004)(4326008)(8676002)(5660300002)(2616005)(83380400001)(110136005)(921005)(6636002)(356005)(186003)(7416002)(70206006)(7636003)(82310400003)(26005)(70586007)(102446001); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Dec 2020 08:34:31.2381 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a4f92f82-005a-4787-d107-08d895d3ec98 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.62.198]; Helo=[xsj-pvapexch02.xlnx.xilinx.com] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT044.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5629 Received-SPF: pass client-ip=40.107.92.80; envelope-from=saipava@xilinx.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: QEMU Developers Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal Connect VersalUbs2 subsystem to xlnx-versal SOC, its placed in iou of lpd domain and configure it as dual port host controller. Add the respective guest dts nodes for "xlnx-versal-virt" machine. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- hw/arm/xlnx-versal-virt.c | 58 ++++++++++++++++++++++++++++++++++++++++= ++++ hw/arm/xlnx-versal.c | 26 ++++++++++++++++++++ include/hw/arm/xlnx-versal.h | 9 +++++++ 3 files changed, 93 insertions(+) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index ee12822..84b450e 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -39,6 +39,8 @@ struct VersalVirt { uint32_t ethernet_phy[2]; uint32_t clk_125Mhz; uint32_t clk_25Mhz; + uint32_t usb; + uint32_t dwc; } phandle; struct arm_boot_info binfo; =20 @@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s) s->phandle.clk_25Mhz =3D qemu_fdt_alloc_phandle(s->fdt); s->phandle.clk_125Mhz =3D qemu_fdt_alloc_phandle(s->fdt); =20 + s->phandle.usb =3D qemu_fdt_alloc_phandle(s->fdt); + s->phandle.dwc =3D qemu_fdt_alloc_phandle(s->fdt); /* Create /chosen node for load_dtb. */ qemu_fdt_add_subnode(s->fdt, "/chosen"); =20 @@ -148,6 +152,59 @@ static void fdt_add_timer_nodes(VersalVirt *s) compat, sizeof(compat)); } =20 +static void fdt_add_usb_xhci_nodes(VersalVirt *s) +{ + const char clocknames[] =3D "bus_clk\0ref_clk"; + char *name =3D g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); + const char compat[] =3D "xlnx,versal-dwc3"; + + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB2_CTRL_REGS, + 2, MM_USB2_CTRL_REGS_SIZE); + qemu_fdt_setprop(s->fdt, name, "clock-names", + clocknames, sizeof(clocknames)); + qemu_fdt_setprop_cells(s->fdt, name, "clocks", + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz= ); + qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); + g_free(name); + + { + const char irq_name[] =3D "dwc_usb3"; + const char compat[] =3D "snps,dwc3"; + + name =3D g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, + MM_USB2_CTRL_REGS, MM_USB_0); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB_0, 2, MM_USB_0_SIZE); + qemu_fdt_setprop(s->fdt, name, "interrupt-names", + irq_name, sizeof(irq_name)); + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(s->fdt, name, + "snps,quirk-frame-length-adjustment", 0x20); + qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); + qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); + qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0= ); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0= ); + qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); + qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed= "); + g_free(name); + } +} + static void fdt_add_uart_nodes(VersalVirt *s) { uint64_t addrs[] =3D { MM_UART1, MM_UART0 }; @@ -515,6 +572,7 @@ static void versal_virt_init(MachineState *machine) fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); fdt_add_zdma_nodes(s); + fdt_add_usb_xhci_nodes(s); fdt_add_sd_nodes(s); fdt_add_rtc_node(s); fdt_add_cpu_nodes(s, psci_conduit); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 12ba6c4..b077716 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -145,6 +145,31 @@ static void versal_create_uarts(Versal *s, qemu_irq *p= ic) } } =20 +static void versal_create_usbs(Versal *s, qemu_irq *pic) +{ + DeviceState *dev; + MemoryRegion *mr; + + object_initialize_child(OBJECT(s), "usb2", &s->lpd.iou.usb, + TYPE_XILINX_VERSAL_USB2); + dev =3D DEVICE(&s->lpd.iou.usb); + + object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), + &error_abort); + qdev_prop_set_uint32(dev, "intrs", 1); + qdev_prop_set_uint32(dev, "slots", 2); + + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB_0, mr); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[VERSAL_USB0_IRQ_0]); + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); +} + static void versal_create_gems(Versal *s, qemu_irq *pic) { int i; @@ -333,6 +358,7 @@ static void versal_realize(DeviceState *dev, Error **er= rp) versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); versal_create_uarts(s, pic); + versal_create_usbs(s, pic); versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_sds(s, pic); diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 8ce8e63..2b76885 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -21,6 +21,7 @@ #include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" +#include "hw/usb/xlnx-usb-subsystem.h" =20 #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -59,6 +60,7 @@ struct Versal { PL011State uart[XLNX_VERSAL_NR_UARTS]; CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; + VersalUsb2 usb; } iou; } lpd; =20 @@ -88,6 +90,7 @@ struct Versal { =20 #define VERSAL_UART0_IRQ_0 18 #define VERSAL_UART1_IRQ_0 19 +#define VERSAL_USB0_IRQ_0 22 #define VERSAL_GEM0_IRQ_0 56 #define VERSAL_GEM0_WAKE_IRQ_0 57 #define VERSAL_GEM1_IRQ_0 58 @@ -125,6 +128,12 @@ struct Versal { #define MM_OCM 0xfffc0000U #define MM_OCM_SIZE 0x40000 =20 +#define MM_USB2_CTRL_REGS 0xFF9D0000 +#define MM_USB2_CTRL_REGS_SIZE 0x10000 + +#define MM_USB_0 0xFE200000 +#define MM_USB_0_SIZE 0x10000 + #define MM_TOP_DDR 0x0 #define MM_TOP_DDR_SIZE 0x80000000U #define MM_TOP_DDR_2 0x800000000ULL --=20 2.7.4