From nobody Sat May 18 18:27:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1603369175; cv=pass; d=zohomail.com; s=zohoarc; b=Ndzd7E76pqhIlbzZ+Md5VRLKklktW1qAKlZ2sW+UvM8NeSL1Xlmn9AVgRoLghceVJzPYmA3dGlWdj2DX/vvhQalrWEtBGMBImMsVQgfxgzH8pGYV5CkivxH0kcha0NnmpGeWoKrBFnAfstwZC1fMO+e0rdiqLcqFSqwuSTFnjqI= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603369175; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tPE4yAZzRCS2xIAjbDyfxY1KJd6LsnrNfOtf5P6Gq4o=; b=ZExkF52tBcFtu+0RaBmXUuZbdWzUnwjZ9FykV0jkl6ONB15bmbdTj5Teij4iNhOFXlgK/3fF4V8C2QYVc3oGpBCV9V5127V1q4nVGwptxKhTOKOyI42ka6wK8jkiHHkKV+oDIJKHlBa1snxE7jUvson/6a87B6PY7d/vSNk6u38= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1603369175282887.463747846926; Thu, 22 Oct 2020 05:19:35 -0700 (PDT) Received: from localhost ([::1]:46328 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVZZ8-0003tC-39 for importer@patchew.org; Thu, 22 Oct 2020 08:19:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42314) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVZTD-0007bX-NO for qemu-devel@nongnu.org; Thu, 22 Oct 2020 08:13:27 -0400 Received: from mail-bn8nam11on2059.outbound.protection.outlook.com ([40.107.236.59]:38043 helo=NAM11-BN8-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVZRZ-000134-1U for qemu-devel@nongnu.org; Thu, 22 Oct 2020 08:13:27 -0400 Received: from DM3PR08CA0023.namprd08.prod.outlook.com (2603:10b6:0:52::33) by SN4PR0201MB3583.namprd02.prod.outlook.com (2603:10b6:803:45::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.28; Thu, 22 Oct 2020 12:11:41 +0000 Received: from CY1NAM02FT062.eop-nam02.prod.protection.outlook.com (2603:10b6:0:52:cafe::ca) by DM3PR08CA0023.outlook.office365.com (2603:10b6:0:52::33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Thu, 22 Oct 2020 12:11:41 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT062.mail.protection.outlook.com (10.152.75.60) with Microsoft SMTP Server id 15.20.3499.20 via Frontend Transport; Thu, 22 Oct 2020 12:11:41 +0000 Received: from [149.199.38.66] (port=56480 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1kVZQY-0001kB-NR; Thu, 22 Oct 2020 05:10:42 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp1.xlnx.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.63) (envelope-from ) id 1kVZRU-0005qR-GR; Thu, 22 Oct 2020 05:11:40 -0700 Received: from xsj-pvapsmtp01 (mailman.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 09MCBdkW022865; Thu, 22 Oct 2020 05:11:39 -0700 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kVZRS-0005pq-TB; Thu, 22 Oct 2020 05:11:39 -0700 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 38CC113C02EE; Thu, 22 Oct 2020 17:47:51 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=LovYXxCX6elJGFhEbuYK7JDjUX5GOTMMQG8Z8rJrWAk229sSbBc+FMih+4v7o9aXjwtwdMR9zoZ+3s0FXp5a599kP14xULyFD8/lsxGw7Zf1ogVcb8fLIuKwN2xrHYkchRZKP4hv59GDshoIjO27dWGXlnOnyL85ekmvtLSo78NG+UfTQo3S0x9wKIOrsB/HTHJRVZFfxH5jT5lLL+IBK3cDgTKxI4vNYoGimSbQ1ktlaa+0uPmTuJb3hd9MR5MpAY1ZCCfbyCm7S/pkqlcAVOdi3ig1T6rU4A3t5AX8Q+XsTtiS2ylnysqUNp4iTNsSNftsPBhhsJ+lIlHRXbzMWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tPE4yAZzRCS2xIAjbDyfxY1KJd6LsnrNfOtf5P6Gq4o=; b=iyOt7FtAyxv30dpeBx+Z5vl3UYPA0AxL9nEck3ir9V73CfR0qMvt1dOGIA0Efd2gaPGeC8NkveFrVT2EvcOWLLHeAgz0btcj5mDajEORgekvRnOncCw9p81AszQ1xQ50i9FUrYfn5/qMWlI7jtvWVJtgUtp9hqwx7H1u7jPtr9aE43zjAPR+qEKZ+kN/e0ibx/eaKk8XtMKZu3Ar9MVWHhLPUAXl9obVMf/miKjhk46oN/O24hlSwvCt1DYy9+3+mJ0RtkkgHfkBZYrVrThbIUuIuLEsSFV9evZxxpkGzK6tjJIPIoYh6zZlLlNuAiUbQa2egN+JRxJ5D7AcQFC/uA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=wdc.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=tPE4yAZzRCS2xIAjbDyfxY1KJd6LsnrNfOtf5P6Gq4o=; b=p9gPimYgCx5fKMCBZQzXePhRoKzebY47jWOdqWKg274HM26mtAC4G10KA1Jvg64k4xjD2j/Hf3nghFn3K9MLyQ/QCdRj+aqdBuyrO4aU+2M1rrQO/MaWwRNBt+sVuzrwzhGtRtzUuKAIZXqEmAjU+iaB/TD1y9aUk5vnKsZCHCI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; wdc.com; dkim=none (message not signed) header.d=none;wdc.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?UTF-8?q?=27Marc-Andr=C3=A9=20Lureau=27?= , Paolo Bonzini , Gerd Hoffmann , Edgar Iglesias , Francisco Eduardo Iglesias Subject: [PATCH v12 1/3] misc: Add versal-usb2-ctrl-regs module Date: Thu, 22 Oct 2020 17:47:34 +0530 Message-Id: <1603369056-4168-2-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1603369056-4168-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1603369056-4168-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 68a20da4-a881-4b6b-b709-08d87683a278 X-MS-TrafficTypeDiagnostic: SN4PR0201MB3583: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:352; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0bqu25b3y1zeZgHX5efs3PGvnVB5tR3Xh/UtxXB6h1lWY1fiCV4gP3Lv2N4RIjmkuj2MM5Yd512hLp1+nfkhkDYPymFLUGUobtxAj7C4d1u9T1wLtPYCGE8vdyBE24cN/thjRqgpIZCCBXXpsWAehsWzkNcG6SEjSA3vHIccVtj4Fjsf6Qu4i4Jb6FBxII065PE8inpZY3lC/Q3zjI4DQYIjRLiMwIRoxQ+p4PyNKyO0/Pz/IHuP/5ecTjj5ETEE3o/w6Pny88Z1Bd4JY2fm3lvCuOBNR0uRSFJ6Nfx8QKF2VH5OEgVhNh+oZy16V8RpAzTCw3jW/DfHnUeqaHBOxC8xRMgVVcUuleIeJ1dw0TDZekzBi8iC6I0NRI3KOwG/yl5HsS+OwyvsQIhEWOGk1g== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(346002)(396003)(376002)(136003)(39860400002)(46966005)(83380400001)(6266002)(356005)(81166007)(336012)(8676002)(36756003)(82740400003)(426003)(6666004)(6636002)(19627235002)(186003)(47076004)(8936002)(478600001)(82310400003)(2616005)(54906003)(2906002)(26005)(4326008)(42186006)(316002)(110136005)(70586007)(5660300002)(30864003)(70206006)(7416002)(107886003); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2020 12:11:41.1393 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 68a20da4-a881-4b6b-b709-08d87683a278 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT062.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN4PR0201MB3583 Received-SPF: pass client-ip=40.107.236.59; envelope-from=saipava@xilinx.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/22 08:11:43 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Vikram Garhwal , qemu-devel@nongnu.org, Paul Zimmerman , Sai Pavan Boddu , Alistair Francis , Ying Fang , =?UTF-8?q?=27Philippe=20Mathieu-Daud=C3=A9=27?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" This module emulates control registers of versal usb2 controller, this is a= dded just to make guest happy. In general this module would control the phy-reset signal from usb controller, data coherency of the transactions, signals the host system errors received from controller. Signed-off-by: Sai Pavan Boddu Signed-off-by: Vikram Garhwal Reviewed-by: Edgar E. Iglesias --- hw/misc/meson.build | 1 + hw/misc/xlnx-versal-usb2-ctrl-regs.c | 229 +++++++++++++++++++++++= ++++ include/hw/misc/xlnx-versal-usb2-ctrl-regs.h | 45 ++++++ 3 files changed, 275 insertions(+) create mode 100644 hw/misc/xlnx-versal-usb2-ctrl-regs.c create mode 100644 include/hw/misc/xlnx-versal-usb2-ctrl-regs.h diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 793d45b..b336dd1 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -109,3 +109,4 @@ specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files= ('mips_cmgcr.c', 'mips_cp specific_ss.add(when: 'CONFIG_MIPS_ITU', if_true: files('mips_itu.c')) =20 specific_ss.add(when: 'CONFIG_SBSA_REF', if_true: files('sbsa_ec.c')) +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-us= b2-ctrl-regs.c')) diff --git a/hw/misc/xlnx-versal-usb2-ctrl-regs.c b/hw/misc/xlnx-versal-usb= 2-ctrl-regs.c new file mode 100644 index 0000000..0d09dd2 --- /dev/null +++ b/hw/misc/xlnx-versal-usb2-ctrl-regs.c @@ -0,0 +1,229 @@ +/* + * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for + * USB2.0 controller + * + * This module should control phy_reset, permanent device plugs, frame len= gth + * time adjust & setting of coherency paths. None of which are emulated in + * present model. + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "migration/vmstate.h" +#include "hw/misc/xlnx-versal-usb2-ctrl-regs.h" + +#ifndef XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG +#define XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG 0 +#endif + +REG32(BUS_FILTER, 0x30) + FIELD(BUS_FILTER, BYPASS, 0, 4) +REG32(PORT, 0x34) + FIELD(PORT, HOST_SMI_BAR_WR, 4, 1) + FIELD(PORT, HOST_SMI_PCI_CMD_REG_WR, 3, 1) + FIELD(PORT, HOST_MSI_ENABLE, 2, 1) + FIELD(PORT, PWR_CTRL_PRSNT, 1, 1) + FIELD(PORT, HUB_PERM_ATTACH, 0, 1) +REG32(JITTER_ADJUST, 0x38) + FIELD(JITTER_ADJUST, FLADJ, 0, 6) +REG32(BIGENDIAN, 0x40) + FIELD(BIGENDIAN, ENDIAN_GS, 0, 1) +REG32(COHERENCY, 0x44) + FIELD(COHERENCY, USB_COHERENCY, 0, 1) +REG32(XHC_BME, 0x48) + FIELD(XHC_BME, XHC_BME, 0, 1) +REG32(REG_CTRL, 0x60) + FIELD(REG_CTRL, SLVERR_ENABLE, 0, 1) +REG32(IR_STATUS, 0x64) + FIELD(IR_STATUS, HOST_SYS_ERR, 1, 1) + FIELD(IR_STATUS, ADDR_DEC_ERR, 0, 1) +REG32(IR_MASK, 0x68) + FIELD(IR_MASK, HOST_SYS_ERR, 1, 1) + FIELD(IR_MASK, ADDR_DEC_ERR, 0, 1) +REG32(IR_ENABLE, 0x6c) + FIELD(IR_ENABLE, HOST_SYS_ERR, 1, 1) + FIELD(IR_ENABLE, ADDR_DEC_ERR, 0, 1) +REG32(IR_DISABLE, 0x70) + FIELD(IR_DISABLE, HOST_SYS_ERR, 1, 1) + FIELD(IR_DISABLE, ADDR_DEC_ERR, 0, 1) +REG32(USB3, 0x78) + +static void ir_update_irq(VersalUsb2CtrlRegs *s) +{ + bool pending =3D s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; + qemu_set_irq(s->irq_ir, pending); +} + +static void ir_status_postw(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + /* + * TODO: This should also clear USBSTS.HSE field in USB XHCI register. + * May be combine both the modules. + */ + ir_update_irq(s); +} + +static uint64_t ir_enable_prew(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] &=3D ~val; + ir_update_irq(s); + return 0; +} + +static uint64_t ir_disable_prew(RegisterInfo *reg, uint64_t val64) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] |=3D val; + ir_update_irq(s); + return 0; +} + +static const RegisterAccessInfo usb2_ctrl_regs_regs_info[] =3D { + { .name =3D "BUS_FILTER", .addr =3D A_BUS_FILTER, + .rsvd =3D 0xfffffff0, + },{ .name =3D "PORT", .addr =3D A_PORT, + .rsvd =3D 0xffffffe0, + },{ .name =3D "JITTER_ADJUST", .addr =3D A_JITTER_ADJUST, + .reset =3D 0x20, + .rsvd =3D 0xffffffc0, + },{ .name =3D "BIGENDIAN", .addr =3D A_BIGENDIAN, + .rsvd =3D 0xfffffffe, + },{ .name =3D "COHERENCY", .addr =3D A_COHERENCY, + .rsvd =3D 0xfffffffe, + },{ .name =3D "XHC_BME", .addr =3D A_XHC_BME, + .reset =3D 0x1, + .rsvd =3D 0xfffffffe, + },{ .name =3D "REG_CTRL", .addr =3D A_REG_CTRL, + .rsvd =3D 0xfffffffe, + },{ .name =3D "IR_STATUS", .addr =3D A_IR_STATUS, + .rsvd =3D 0xfffffffc, + .w1c =3D 0x3, + .post_write =3D ir_status_postw, + },{ .name =3D "IR_MASK", .addr =3D A_IR_MASK, + .reset =3D 0x3, + .rsvd =3D 0xfffffffc, + .ro =3D 0x3, + },{ .name =3D "IR_ENABLE", .addr =3D A_IR_ENABLE, + .rsvd =3D 0xfffffffc, + .pre_write =3D ir_enable_prew, + },{ .name =3D "IR_DISABLE", .addr =3D A_IR_DISABLE, + .rsvd =3D 0xfffffffc, + .pre_write =3D ir_disable_prew, + },{ .name =3D "USB3", .addr =3D A_USB3, + } +}; + +static void usb2_ctrl_regs_reset_init(Object *obj, ResetType type) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void usb2_ctrl_regs_reset_hold(Object *obj) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + + ir_update_irq(s); +} + +static const MemoryRegionOps usb2_ctrl_regs_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void usb2_ctrl_regs_init(Object *obj) +{ + VersalUsb2CtrlRegs *s =3D XILINX_VERSAL_USB2_CTRL_REGS(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + USB2_REGS_R_MAX * 4); + reg_array =3D + register_init_block32(DEVICE(obj), usb2_ctrl_regs_regs_info, + ARRAY_SIZE(usb2_ctrl_regs_regs_info), + s->regs_info, s->regs, + &usb2_ctrl_regs_ops, + XILINX_VERSAL_USB2_CTRL_REGS_ERR_DEBUG, + USB2_REGS_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + 0x0, + ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq_ir); +} + +static const VMStateDescription vmstate_usb2_ctrl_regs =3D { + .name =3D TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, VersalUsb2CtrlRegs, USB2_REGS_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void usb2_ctrl_regs_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D usb2_ctrl_regs_reset_init; + rc->phases.hold =3D usb2_ctrl_regs_reset_hold; + dc->vmsd =3D &vmstate_usb2_ctrl_regs; +} + +static const TypeInfo usb2_ctrl_regs_info =3D { + .name =3D TYPE_XILINX_VERSAL_USB2_CTRL_REGS, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(VersalUsb2CtrlRegs), + .class_init =3D usb2_ctrl_regs_class_init, + .instance_init =3D usb2_ctrl_regs_init, +}; + +static void usb2_ctrl_regs_register_types(void) +{ + type_register_static(&usb2_ctrl_regs_info); +} + +type_init(usb2_ctrl_regs_register_types) diff --git a/include/hw/misc/xlnx-versal-usb2-ctrl-regs.h b/include/hw/misc= /xlnx-versal-usb2-ctrl-regs.h new file mode 100644 index 0000000..975a717 --- /dev/null +++ b/include/hw/misc/xlnx-versal-usb2-ctrl-regs.h @@ -0,0 +1,45 @@ +/* + * QEMU model of the VersalUsb2CtrlRegs Register control/Status block for + * USB2.0 controller + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef _XLNX_USB2_REGS_H_ +#define _XLNX_USB2_REGS_H_ + +#define TYPE_XILINX_VERSAL_USB2_CTRL_REGS "xlnx.versal-usb2-ctrl-regs" + +#define XILINX_VERSAL_USB2_CTRL_REGS(obj) \ + OBJECT_CHECK(VersalUsb2CtrlRegs, (obj), TYPE_XILINX_VERSAL_USB2_CTRL_= REGS) + +#define USB2_REGS_R_MAX ((0x78 / 4) + 1) + +typedef struct VersalUsb2CtrlRegs { + SysBusDevice parent_obj; + MemoryRegion iomem; + qemu_irq irq_ir; + + uint32_t regs[USB2_REGS_R_MAX]; + RegisterInfo regs_info[USB2_REGS_R_MAX]; +} VersalUsb2CtrlRegs; + +#endif --=20 2.7.4 From nobody Sat May 18 18:27:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1603369225; cv=pass; d=zohomail.com; s=zohoarc; b=eTF13UnX3OKPNin5Xp1upHxqLFzK/onllwpdQ39t2FouDQ0zafLIhxLGDXN1eHkxglQFrV0KfA3xOL0oG1Ay6mxg/yagxKtAoHN/KTkbzCYL6DeCcAwDXmDzb9PbNSd1Putl+ucRb/eA/fo+QpZRUeZrVvbnYYW+ECmXRc+Yxfo= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603369225; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SvVho3XztQ2OTXdj8vZ3iYymzDSo7QbgvwZEfnExtAg=; b=AXMbh0BCIkBwecPZozBo6CI0W8dniG+3pXx/hmTkMJ9pwCY1k7bGBn3WuOPZ3xLtLrvpDE8UUKX2cwQ5xWj2guoL0TtzB+klgJRSXjfmGJcHImnMOuxEkXxHo8z6X0Y994T+1bZs7HzzDomScch94TfjuR/qsx61pxn8Z1P0QYc= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1603369225066986.9375993105717; Thu, 22 Oct 2020 05:20:25 -0700 (PDT) Received: from localhost ([::1]:48758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVZZv-0004qi-VV for importer@patchew.org; Thu, 22 Oct 2020 08:20:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVZT3-0007C9-6B for qemu-devel@nongnu.org; Thu, 22 Oct 2020 08:13:17 -0400 Received: from mail-bn7nam10on2057.outbound.protection.outlook.com ([40.107.92.57]:30305 helo=NAM10-BN7-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVZRY-000137-Tq for qemu-devel@nongnu.org; Thu, 22 Oct 2020 08:13:16 -0400 Received: from MN2PR03CA0024.namprd03.prod.outlook.com (2603:10b6:208:23a::29) by BL0PR02MB6547.namprd02.prod.outlook.com (2603:10b6:208:1c8::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.27; Thu, 22 Oct 2020 12:11:41 +0000 Received: from BL2NAM02FT047.eop-nam02.prod.protection.outlook.com (2603:10b6:208:23a:cafe::db) by MN2PR03CA0024.outlook.office365.com (2603:10b6:208:23a::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.22 via Frontend Transport; Thu, 22 Oct 2020 12:11:41 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT047.mail.protection.outlook.com (10.152.77.9) with Microsoft SMTP Server id 15.20.3499.20 via Frontend Transport; Thu, 22 Oct 2020 12:11:41 +0000 Received: from [149.199.38.66] (port=56482 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1kVZQY-0001kJ-Q2; Thu, 22 Oct 2020 05:10:42 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp2.xlnx.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.63) (envelope-from ) id 1kVZRU-0005qU-O9; Thu, 22 Oct 2020 05:11:40 -0700 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 09MCBdlw015660; Thu, 22 Oct 2020 05:11:39 -0700 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kVZRS-0005ps-UA; Thu, 22 Oct 2020 05:11:39 -0700 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 4044013C0939; Thu, 22 Oct 2020 17:47:51 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=l5VBa0eA2ACYp2ogay8W4PjXD9hVnbacuHlVZga19+Wqxzt6dztGcHToFdeJILPau+urhCwcR4a12M/s5nbQEjHMrL6vgvz1a6XIORVfHZYEvcOhKPQve5z5YU9Lhj3oOhdZxUGT7B9kZnfo5CnsiHYa/X1dW5xT3lU9JfXoC5a2sRQFNy6eDamVhg7GopiZ5gwbRGSuXRtpivfRfNxG47jOvyb1ZF8IKWilP2lcgszLFUemukOo2lWG6oWvD1oKaMMGGm5SX6oz0KJVrBCKP6hoWbrY45DecgCEFzZyqrbK9CosEFAP3hXrmIcq801I17sbYy//CnBGRXS08BzO1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SvVho3XztQ2OTXdj8vZ3iYymzDSo7QbgvwZEfnExtAg=; b=SJAaKKAv7NoLRBvQez9oLdSLzOdnIIaZZhfFsRp+IqpF0XnVcxQP3gGRr5wX+UJxzDxYkUOKGJN/qxN5pkJ5KcKjBrLql9yu/TfjaTsoB+M31hAos48zUWXwDrLQSwHNr/wW5/sUeLTpQS989yEmgBJs0Hzd3vj1Lh+hExfkNt6g7L+g4xnLaqd1G/XZXvCMZxpEw6uf/LlMgOzNycj2cGYLLqR7WoaT4ncLwSr1k6tmOJJT4vvycXYPfCHaHW+1N0m0BDeMI9XctJDzG+YsQqBWMiMV3qO5RCB8wnteSzb89FE9KFnGAweH6nWfOyJ76Ztnjvw/Ozc86tY0gTwSOA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=wdc.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=SvVho3XztQ2OTXdj8vZ3iYymzDSo7QbgvwZEfnExtAg=; b=YiwgIpsVmxUcVpNQv4L0WeTuT787avhJC50sPXWVOWNYDGLwDvanJQedOX/5f6SlwWpyrUwRpm0aLPLvBZSGDUG77+pVRvlowfDcGSrbHlx1WGJzBdXYOY2KAqPOZn9IEhzJylQbC0yTC+7abHj8UpLS1IAd7WmaP7iWBeFZLi4= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; wdc.com; dkim=none (message not signed) header.d=none;wdc.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?UTF-8?q?=27Marc-Andr=C3=A9=20Lureau=27?= , Paolo Bonzini , Gerd Hoffmann , Edgar Iglesias , Francisco Eduardo Iglesias Subject: [PATCH v12 2/3] usb: Add DWC3 model Date: Thu, 22 Oct 2020 17:47:35 +0530 Message-Id: <1603369056-4168-3-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1603369056-4168-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1603369056-4168-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: afc3d5e9-429c-43a4-fb4a-08d87683a28c X-MS-TrafficTypeDiagnostic: BL0PR02MB6547: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:254; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: iPP8+Fm6z9n64V9vm0S/oppak60iMToq6tGGYsaHqt9HFjVnrSK6FSbL+MzWhMBMkHOhfZLeeVHrj16y4txrJv1umezkWuiCp99hRO8iePkfrVhLk3ZtBEr1orO993+4TLOhxoxFVeAbrKEGHpXHgzjkFelL7uQq+enbekxK1hk5BrBf/qFKx7tzoS6+NNVbrbFth1P1O1na8xGPrUzovQvdgOFsYFFBcTH3bVPLIAWLfSvdV7mhHXQ/Zw4M57ur4h3Cv5bN+v/yPJJaCo4SWfBDDZJ09izNrN45xHzlqhvdcETniXqZUUCGDdsVXiT/0OndozPfH2Oj5oOZK03xhcYuzsq0YcAUgDV0Wx1w86XFqxEO9w2YF87pKQHpCycBbujw4gwPngpcCHPsB3nK7Q== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(376002)(136003)(39860400002)(396003)(346002)(46966005)(2906002)(110136005)(426003)(356005)(6666004)(8676002)(8936002)(336012)(82310400003)(42186006)(70586007)(36756003)(70206006)(7416002)(186003)(82740400003)(2616005)(4326008)(54906003)(81166007)(30864003)(107886003)(83380400001)(478600001)(5660300002)(6266002)(6636002)(26005)(47076004)(316002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2020 12:11:41.2716 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: afc3d5e9-429c-43a4-fb4a-08d87683a28c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT047.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL0PR02MB6547 Received-SPF: pass client-ip=40.107.92.57; envelope-from=saipava@xilinx.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/22 08:11:44 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Vikram Garhwal , qemu-devel@nongnu.org, Paul Zimmerman , Sai Pavan Boddu , Alistair Francis , Ying Fang , =?UTF-8?q?=27Philippe=20Mathieu-Daud=C3=A9=27?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal This patch adds skeleton model of dwc3 usb controller attached to xhci-sysbus device. It defines global register space of DWC3 controller, global registers control the AXI/AHB interfaces properties, external FIFO support and event count support. All of which are unimplemented at present,we are only supporting core reset and read of ID register. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- hw/usb/Kconfig | 6 + hw/usb/hcd-dwc3.c | 666 ++++++++++++++++++++++++++++++++++++++++++= ++++ hw/usb/meson.build | 1 + include/hw/usb/hcd-dwc3.h | 55 ++++ 4 files changed, 728 insertions(+) create mode 100644 hw/usb/hcd-dwc3.c create mode 100644 include/hw/usb/hcd-dwc3.h diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 4dd2ba9..f5762f0 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -116,3 +116,9 @@ config IMX_USBPHY bool default y depends on USB + +config USB_DWC3 + bool + default y if USB_XHCI_SYSBUS + select USB + select REGISTER diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c new file mode 100644 index 0000000..775b7a7 --- /dev/null +++ b/hw/usb/hcd-dwc3.c @@ -0,0 +1,666 @@ +/* + * QEMU model of the USB DWC3 host controller emulation. + * + * This model defines global register space of DWC3 controller. Global + * registers control the AXI/AHB interfaces properties, external FIFO supp= ort + * and event count support. All of which are unimplemented at present. We = are + * only supporting core reset and read of ID register. + * + * Copyright (c) 2020 Xilinx Inc. Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/usb/hcd-dwc3.h" +#include "qapi/error.h" + +#ifndef USB_DWC3_ERR_DEBUG +#define USB_DWC3_ERR_DEBUG 0 +#endif + +#define HOST_MODE 1 +#define FIFO_LEN 0x1000 + +REG32(GSBUSCFG0, 0x00) + FIELD(GSBUSCFG0, DATRDREQINFO, 28, 4) + FIELD(GSBUSCFG0, DESRDREQINFO, 24, 4) + FIELD(GSBUSCFG0, DATWRREQINFO, 20, 4) + FIELD(GSBUSCFG0, DESWRREQINFO, 16, 4) + FIELD(GSBUSCFG0, RESERVED_15_12, 12, 4) + FIELD(GSBUSCFG0, DATBIGEND, 11, 1) + FIELD(GSBUSCFG0, DESBIGEND, 10, 1) + FIELD(GSBUSCFG0, RESERVED_9_8, 8, 2) + FIELD(GSBUSCFG0, INCR256BRSTENA, 7, 1) + FIELD(GSBUSCFG0, INCR128BRSTENA, 6, 1) + FIELD(GSBUSCFG0, INCR64BRSTENA, 5, 1) + FIELD(GSBUSCFG0, INCR32BRSTENA, 4, 1) + FIELD(GSBUSCFG0, INCR16BRSTENA, 3, 1) + FIELD(GSBUSCFG0, INCR8BRSTENA, 2, 1) + FIELD(GSBUSCFG0, INCR4BRSTENA, 1, 1) + FIELD(GSBUSCFG0, INCRBRSTENA, 0, 1) +REG32(GSBUSCFG1, 0x04) + FIELD(GSBUSCFG1, RESERVED_31_13, 13, 19) + FIELD(GSBUSCFG1, EN1KPAGE, 12, 1) + FIELD(GSBUSCFG1, PIPETRANSLIMIT, 8, 4) + FIELD(GSBUSCFG1, RESERVED_7_0, 0, 8) +REG32(GTXTHRCFG, 0x08) + FIELD(GTXTHRCFG, RESERVED_31, 31, 1) + FIELD(GTXTHRCFG, RESERVED_30, 30, 1) + FIELD(GTXTHRCFG, USBTXPKTCNTSEL, 29, 1) + FIELD(GTXTHRCFG, RESERVED_28, 28, 1) + FIELD(GTXTHRCFG, USBTXPKTCNT, 24, 4) + FIELD(GTXTHRCFG, USBMAXTXBURSTSIZE, 16, 8) + FIELD(GTXTHRCFG, RESERVED_15, 15, 1) + FIELD(GTXTHRCFG, RESERVED_14, 14, 1) + FIELD(GTXTHRCFG, RESERVED_13_11, 11, 3) + FIELD(GTXTHRCFG, RESERVED_10_0, 0, 11) +REG32(GRXTHRCFG, 0x0c) + FIELD(GRXTHRCFG, RESERVED_31_30, 30, 2) + FIELD(GRXTHRCFG, USBRXPKTCNTSEL, 29, 1) + FIELD(GRXTHRCFG, RESERVED_28, 28, 1) + FIELD(GRXTHRCFG, USBRXPKTCNT, 24, 4) + FIELD(GRXTHRCFG, USBMAXRXBURSTSIZE, 19, 5) + FIELD(GRXTHRCFG, RESERVED_18_16, 16, 3) + FIELD(GRXTHRCFG, RESERVED_15, 15, 1) + FIELD(GRXTHRCFG, RESERVED_14_13, 13, 2) + FIELD(GRXTHRCFG, RESVISOCOUTSPC, 0, 13) +REG32(GCTL, 0x10) + FIELD(GCTL, PWRDNSCALE, 19, 13) + FIELD(GCTL, MASTERFILTBYPASS, 18, 1) + FIELD(GCTL, BYPSSETADDR, 17, 1) + FIELD(GCTL, U2RSTECN, 16, 1) + FIELD(GCTL, FRMSCLDWN, 14, 2) + FIELD(GCTL, PRTCAPDIR, 12, 2) + FIELD(GCTL, CORESOFTRESET, 11, 1) + FIELD(GCTL, U1U2TIMERSCALE, 9, 1) + FIELD(GCTL, DEBUGATTACH, 8, 1) + FIELD(GCTL, RAMCLKSEL, 6, 2) + FIELD(GCTL, SCALEDOWN, 4, 2) + FIELD(GCTL, DISSCRAMBLE, 3, 1) + FIELD(GCTL, U2EXIT_LFPS, 2, 1) + FIELD(GCTL, GBLHIBERNATIONEN, 1, 1) + FIELD(GCTL, DSBLCLKGTNG, 0, 1) +REG32(GPMSTS, 0x14) +REG32(GSTS, 0x18) + FIELD(GSTS, CBELT, 20, 12) + FIELD(GSTS, RESERVED_19_12, 12, 8) + FIELD(GSTS, SSIC_IP, 11, 1) + FIELD(GSTS, OTG_IP, 10, 1) + FIELD(GSTS, BC_IP, 9, 1) + FIELD(GSTS, ADP_IP, 8, 1) + FIELD(GSTS, HOST_IP, 7, 1) + FIELD(GSTS, DEVICE_IP, 6, 1) + FIELD(GSTS, CSRTIMEOUT, 5, 1) + FIELD(GSTS, BUSERRADDRVLD, 4, 1) + FIELD(GSTS, RESERVED_3_2, 2, 2) + FIELD(GSTS, CURMOD, 0, 2) +REG32(GUCTL1, 0x1c) + FIELD(GUCTL1, RESUME_OPMODE_HS_HOST, 10, 1) +REG32(GSNPSID, 0x20) +REG32(GGPIO, 0x24) + FIELD(GGPIO, GPO, 16, 16) + FIELD(GGPIO, GPI, 0, 16) +REG32(GUID, 0x28) +REG32(GUCTL, 0x2c) + FIELD(GUCTL, REFCLKPER, 22, 10) + FIELD(GUCTL, NOEXTRDL, 21, 1) + FIELD(GUCTL, RESERVED_20_18, 18, 3) + FIELD(GUCTL, SPRSCTRLTRANSEN, 17, 1) + FIELD(GUCTL, RESBWHSEPS, 16, 1) + FIELD(GUCTL, RESERVED_15, 15, 1) + FIELD(GUCTL, USBHSTINAUTORETRYEN, 14, 1) + FIELD(GUCTL, ENOVERLAPCHK, 13, 1) + FIELD(GUCTL, EXTCAPSUPPTEN, 12, 1) + FIELD(GUCTL, INSRTEXTRFSBODI, 11, 1) + FIELD(GUCTL, DTCT, 9, 2) + FIELD(GUCTL, DTFT, 0, 9) +REG32(GBUSERRADDRLO, 0x30) +REG32(GBUSERRADDRHI, 0x34) +REG32(GHWPARAMS0, 0x40) + FIELD(GHWPARAMS0, GHWPARAMS0_31_24, 24, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_23_16, 16, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_15_8, 8, 8) + FIELD(GHWPARAMS0, GHWPARAMS0_7_6, 6, 2) + FIELD(GHWPARAMS0, GHWPARAMS0_5_3, 3, 3) + FIELD(GHWPARAMS0, GHWPARAMS0_2_0, 0, 3) +REG32(GHWPARAMS1, 0x44) + FIELD(GHWPARAMS1, GHWPARAMS1_31, 31, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_30, 30, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_29, 29, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_28, 28, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_27, 27, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_26, 26, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_25_24, 24, 2) + FIELD(GHWPARAMS1, GHWPARAMS1_23, 23, 1) + FIELD(GHWPARAMS1, GHWPARAMS1_22_21, 21, 2) + FIELD(GHWPARAMS1, GHWPARAMS1_20_15, 15, 6) + FIELD(GHWPARAMS1, GHWPARAMS1_14_12, 12, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_11_9, 9, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_8_6, 6, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_5_3, 3, 3) + FIELD(GHWPARAMS1, GHWPARAMS1_2_0, 0, 3) +REG32(GHWPARAMS2, 0x48) +REG32(GHWPARAMS3, 0x4c) + FIELD(GHWPARAMS3, GHWPARAMS3_31, 31, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_30_23, 23, 8) + FIELD(GHWPARAMS3, GHWPARAMS3_22_18, 18, 5) + FIELD(GHWPARAMS3, GHWPARAMS3_17_12, 12, 6) + FIELD(GHWPARAMS3, GHWPARAMS3_11, 11, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_10, 10, 1) + FIELD(GHWPARAMS3, GHWPARAMS3_9_8, 8, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_7_6, 6, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_5_4, 4, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_3_2, 2, 2) + FIELD(GHWPARAMS3, GHWPARAMS3_1_0, 0, 2) +REG32(GHWPARAMS4, 0x50) + FIELD(GHWPARAMS4, GHWPARAMS4_31_28, 28, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_27_24, 24, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_23, 23, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_22, 22, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_21, 21, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_20_17, 17, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_16_13, 13, 4) + FIELD(GHWPARAMS4, GHWPARAMS4_12, 12, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_11, 11, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_10_9, 9, 2) + FIELD(GHWPARAMS4, GHWPARAMS4_8_7, 7, 2) + FIELD(GHWPARAMS4, GHWPARAMS4_6, 6, 1) + FIELD(GHWPARAMS4, GHWPARAMS4_5_0, 0, 6) +REG32(GHWPARAMS5, 0x54) + FIELD(GHWPARAMS5, GHWPARAMS5_31_28, 28, 4) + FIELD(GHWPARAMS5, GHWPARAMS5_27_22, 22, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_21_16, 16, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_15_10, 10, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_9_4, 4, 6) + FIELD(GHWPARAMS5, GHWPARAMS5_3_0, 0, 4) +REG32(GHWPARAMS6, 0x58) + FIELD(GHWPARAMS6, GHWPARAMS6_31_16, 16, 16) + FIELD(GHWPARAMS6, BUSFLTRSSUPPORT, 15, 1) + FIELD(GHWPARAMS6, BCSUPPORT, 14, 1) + FIELD(GHWPARAMS6, OTG_SS_SUPPORT, 13, 1) + FIELD(GHWPARAMS6, ADPSUPPORT, 12, 1) + FIELD(GHWPARAMS6, HNPSUPPORT, 11, 1) + FIELD(GHWPARAMS6, SRPSUPPORT, 10, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_9_8, 8, 2) + FIELD(GHWPARAMS6, GHWPARAMS6_7, 7, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_6, 6, 1) + FIELD(GHWPARAMS6, GHWPARAMS6_5_0, 0, 6) +REG32(GHWPARAMS7, 0x5c) + FIELD(GHWPARAMS7, GHWPARAMS7_31_16, 16, 16) + FIELD(GHWPARAMS7, GHWPARAMS7_15_0, 0, 16) +REG32(GDBGFIFOSPACE, 0x60) + FIELD(GDBGFIFOSPACE, SPACE_AVAILABLE, 16, 16) + FIELD(GDBGFIFOSPACE, RESERVED_15_9, 9, 7) + FIELD(GDBGFIFOSPACE, FIFO_QUEUE_SELECT, 0, 9) +REG32(GUCTL2, 0x9c) + FIELD(GUCTL2, RESERVED_31_26, 26, 6) + FIELD(GUCTL2, EN_HP_PM_TIMER, 19, 7) + FIELD(GUCTL2, NOLOWPWRDUR, 15, 4) + FIELD(GUCTL2, RST_ACTBITLATER, 14, 1) + FIELD(GUCTL2, RESERVED_13, 13, 1) + FIELD(GUCTL2, DISABLECFC, 11, 1) +REG32(GUSB2PHYCFG, 0x100) + FIELD(GUSB2PHYCFG, U2_FREECLK_EXISTS, 30, 1) + FIELD(GUSB2PHYCFG, ULPI_LPM_WITH_OPMODE_CHK, 29, 1) + FIELD(GUSB2PHYCFG, RESERVED_25, 25, 1) + FIELD(GUSB2PHYCFG, LSTRD, 22, 3) + FIELD(GUSB2PHYCFG, LSIPD, 19, 3) + FIELD(GUSB2PHYCFG, ULPIEXTVBUSINDIACTOR, 18, 1) + FIELD(GUSB2PHYCFG, ULPIEXTVBUSDRV, 17, 1) + FIELD(GUSB2PHYCFG, RESERVED_16, 16, 1) + FIELD(GUSB2PHYCFG, ULPIAUTORES, 15, 1) + FIELD(GUSB2PHYCFG, RESERVED_14, 14, 1) + FIELD(GUSB2PHYCFG, USBTRDTIM, 10, 4) + FIELD(GUSB2PHYCFG, XCVRDLY, 9, 1) + FIELD(GUSB2PHYCFG, ENBLSLPM, 8, 1) + FIELD(GUSB2PHYCFG, PHYSEL, 7, 1) + FIELD(GUSB2PHYCFG, SUSPENDUSB20, 6, 1) + FIELD(GUSB2PHYCFG, FSINTF, 5, 1) + FIELD(GUSB2PHYCFG, ULPI_UTMI_SEL, 4, 1) + FIELD(GUSB2PHYCFG, PHYIF, 3, 1) + FIELD(GUSB2PHYCFG, TOUTCAL, 0, 3) +REG32(GUSB2I2CCTL, 0x140) +REG32(GUSB2PHYACC_ULPI, 0x180) + FIELD(GUSB2PHYACC_ULPI, RESERVED_31_27, 27, 5) + FIELD(GUSB2PHYACC_ULPI, DISUIPIDRVR, 26, 1) + FIELD(GUSB2PHYACC_ULPI, NEWREGREQ, 25, 1) + FIELD(GUSB2PHYACC_ULPI, VSTSDONE, 24, 1) + FIELD(GUSB2PHYACC_ULPI, VSTSBSY, 23, 1) + FIELD(GUSB2PHYACC_ULPI, REGWR, 22, 1) + FIELD(GUSB2PHYACC_ULPI, REGADDR, 16, 6) + FIELD(GUSB2PHYACC_ULPI, EXTREGADDR, 8, 8) + FIELD(GUSB2PHYACC_ULPI, REGDATA, 0, 8) +REG32(GTXFIFOSIZ0, 0x200) + FIELD(GTXFIFOSIZ0, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ0, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ1, 0x204) + FIELD(GTXFIFOSIZ1, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ1, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ2, 0x208) + FIELD(GTXFIFOSIZ2, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ2, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ3, 0x20c) + FIELD(GTXFIFOSIZ3, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ3, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ4, 0x210) + FIELD(GTXFIFOSIZ4, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ4, TXFDEP_N, 0, 16) +REG32(GTXFIFOSIZ5, 0x214) + FIELD(GTXFIFOSIZ5, TXFSTADDR_N, 16, 16) + FIELD(GTXFIFOSIZ5, TXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ0, 0x280) + FIELD(GRXFIFOSIZ0, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ0, RXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ1, 0x284) + FIELD(GRXFIFOSIZ1, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ1, RXFDEP_N, 0, 16) +REG32(GRXFIFOSIZ2, 0x288) + FIELD(GRXFIFOSIZ2, RXFSTADDR_N, 16, 16) + FIELD(GRXFIFOSIZ2, RXFDEP_N, 0, 16) +REG32(GEVNTADRLO_0, 0x300) +REG32(GEVNTADRHI_0, 0x304) +REG32(GEVNTSIZ_0, 0x308) + FIELD(GEVNTSIZ_0, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_0, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_0, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_0, 0x30c) + FIELD(GEVNTCOUNT_0, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_0, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_0, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_1, 0x310) +REG32(GEVNTADRHI_1, 0x314) +REG32(GEVNTSIZ_1, 0x318) + FIELD(GEVNTSIZ_1, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_1, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_1, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_1, 0x31c) + FIELD(GEVNTCOUNT_1, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_1, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_1, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_2, 0x320) +REG32(GEVNTADRHI_2, 0x324) +REG32(GEVNTSIZ_2, 0x328) + FIELD(GEVNTSIZ_2, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_2, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_2, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_2, 0x32c) + FIELD(GEVNTCOUNT_2, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_2, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_2, EVNTCOUNT, 0, 16) +REG32(GEVNTADRLO_3, 0x330) +REG32(GEVNTADRHI_3, 0x334) +REG32(GEVNTSIZ_3, 0x338) + FIELD(GEVNTSIZ_3, EVNTINTRPTMASK, 31, 1) + FIELD(GEVNTSIZ_3, RESERVED_30_16, 16, 15) + FIELD(GEVNTSIZ_3, EVENTSIZ, 0, 16) +REG32(GEVNTCOUNT_3, 0x33c) + FIELD(GEVNTCOUNT_3, EVNT_HANDLER_BUSY, 31, 1) + FIELD(GEVNTCOUNT_3, RESERVED_30_16, 16, 15) + FIELD(GEVNTCOUNT_3, EVNTCOUNT, 0, 16) +REG32(GHWPARAMS8, 0x500) +REG32(GTXFIFOPRIDEV, 0x510) + FIELD(GTXFIFOPRIDEV, RESERVED_31_N, 6, 26) + FIELD(GTXFIFOPRIDEV, GTXFIFOPRIDEV, 0, 6) +REG32(GTXFIFOPRIHST, 0x518) + FIELD(GTXFIFOPRIHST, RESERVED_31_16, 3, 29) + FIELD(GTXFIFOPRIHST, GTXFIFOPRIHST, 0, 3) +REG32(GRXFIFOPRIHST, 0x51c) + FIELD(GRXFIFOPRIHST, RESERVED_31_16, 3, 29) + FIELD(GRXFIFOPRIHST, GRXFIFOPRIHST, 0, 3) +REG32(GDMAHLRATIO, 0x524) + FIELD(GDMAHLRATIO, RESERVED_31_13, 13, 19) + FIELD(GDMAHLRATIO, HSTRXFIFO, 8, 5) + FIELD(GDMAHLRATIO, RESERVED_7_5, 5, 3) + FIELD(GDMAHLRATIO, HSTTXFIFO, 0, 5) +REG32(GFLADJ, 0x530) + FIELD(GFLADJ, GFLADJ_REFCLK_240MHZDECR_PLS1, 31, 1) + FIELD(GFLADJ, GFLADJ_REFCLK_240MHZ_DECR, 24, 7) + FIELD(GFLADJ, GFLADJ_REFCLK_LPM_SEL, 23, 1) + FIELD(GFLADJ, RESERVED_22, 22, 1) + FIELD(GFLADJ, GFLADJ_REFCLK_FLADJ, 8, 14) + FIELD(GFLADJ, GFLADJ_30MHZ_SDBND_SEL, 7, 1) + FIELD(GFLADJ, GFLADJ_30MHZ, 0, 6) + +static void reset_csr(USBDWC3 * s) +{ + int i =3D 0; + /* + * We reset all CSR regs except GCTL, GUCTL, GSTS, GSNPSID, GGPIO, GUI= D, + * GUSB2PHYCFGn registers and GUSB3PIPECTLn registers. We will skip PHY + * register as we don't implement them. + */ + for (i =3D 0; i < USB_DWC3_R_MAX; i++) { + switch (i) { + case R_GCTL: + break; + case R_GSTS: + break; + case R_GSNPSID: + break; + case R_GGPIO: + break; + case R_GUID: + break; + case R_GUCTL: + break; + case R_GHWPARAMS0...R_GHWPARAMS7: + break; + case R_GHWPARAMS8: + break; + default: + register_reset(&s->regs_info[i]); + break; + } + } + + xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); +} + +static void usb_dwc3_gctl_postw(RegisterInfo *reg, uint64_t val64) +{ + USBDWC3 *s =3D USB_DWC3(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, GCTL, CORESOFTRESET)) { + reset_csr(s); + } +} + +static void usb_dwc3_guid_postw(RegisterInfo *reg, uint64_t val64) +{ + USBDWC3 *s =3D USB_DWC3(reg->opaque); + + s->regs[R_GUID] =3D s->cfg.dwc_usb3_user; +} + +static const RegisterAccessInfo usb_dwc3_regs_info[] =3D { + { .name =3D "GSBUSCFG0", .addr =3D A_GSBUSCFG0, + .ro =3D 0xf300, + .unimp =3D 0xffffffff, + },{ .name =3D "GSBUSCFG1", .addr =3D A_GSBUSCFG1, + .reset =3D 0x300, + .ro =3D 0xffffe0ff, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXTHRCFG", .addr =3D A_GTXTHRCFG, + .ro =3D 0xd000ffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXTHRCFG", .addr =3D A_GRXTHRCFG, + .ro =3D 0xd007e000, + .unimp =3D 0xffffffff, + },{ .name =3D "GCTL", .addr =3D A_GCTL, + .reset =3D 0x30c13004, .post_write =3D usb_dwc3_gctl_postw, + },{ .name =3D "GPMSTS", .addr =3D A_GPMSTS, + .ro =3D 0xfffffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GSTS", .addr =3D A_GSTS, + .reset =3D 0x7e800000, + .ro =3D 0xffffffcf, + .w1c =3D 0x30, + .unimp =3D 0xffffffff, + },{ .name =3D "GUCTL1", .addr =3D A_GUCTL1, + .reset =3D 0x198a, + .ro =3D 0x7800, + .unimp =3D 0xffffffff, + },{ .name =3D "GSNPSID", .addr =3D A_GSNPSID, + .reset =3D 0x5533330a, + .ro =3D 0xffffffff, + },{ .name =3D "GGPIO", .addr =3D A_GGPIO, + .ro =3D 0xffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GUID", .addr =3D A_GUID, + .reset =3D 0x12345678, .post_write =3D usb_dwc3_guid_postw, + },{ .name =3D "GUCTL", .addr =3D A_GUCTL, + .reset =3D 0x0c808010, + .ro =3D 0x1c8000, + .unimp =3D 0xffffffff, + },{ .name =3D "GBUSERRADDRLO", .addr =3D A_GBUSERRADDRLO, + .ro =3D 0xffffffff, + },{ .name =3D "GBUSERRADDRHI", .addr =3D A_GBUSERRADDRHI, + .ro =3D 0xffffffff, + },{ .name =3D "GHWPARAMS0", .addr =3D A_GHWPARAMS0, + .ro =3D 0xffffffff, + .reset =3D 0x40204048, + },{ .name =3D "GHWPARAMS1", .addr =3D A_GHWPARAMS1, + .ro =3D 0xffffffff, + .reset =3D 0x222493b, + },{ .name =3D "GHWPARAMS2", .addr =3D A_GHWPARAMS2, + .ro =3D 0xffffffff, + .reset =3D 0x12345678, + },{ .name =3D "GHWPARAMS3", .addr =3D A_GHWPARAMS3, + .ro =3D 0xffffffff, + .reset =3D 0x618c088, + },{ .name =3D "GHWPARAMS4", .addr =3D A_GHWPARAMS4, + .ro =3D 0xffffffff, + .reset =3D 0x47822004, + },{ .name =3D "GHWPARAMS5", .addr =3D A_GHWPARAMS5, + .ro =3D 0xffffffff, + .reset =3D 0x4202088, + },{ .name =3D "GHWPARAMS6", .addr =3D A_GHWPARAMS6, + .ro =3D 0xffffffff, + .reset =3D 0x7850c20, + },{ .name =3D "GHWPARAMS7", .addr =3D A_GHWPARAMS7, + .ro =3D 0xffffffff, + .reset =3D 0x0, + },{ .name =3D "GDBGFIFOSPACE", .addr =3D A_GDBGFIFOSPACE, + .reset =3D 0xa0000, + .ro =3D 0xfffffe00, + .unimp =3D 0xffffffff, + },{ .name =3D "GUCTL2", .addr =3D A_GUCTL2, + .reset =3D 0x40d, + .ro =3D 0x2000, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2PHYCFG", .addr =3D A_GUSB2PHYCFG, + .reset =3D 0x40102410, + .ro =3D 0x1e014030, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2I2CCTL", .addr =3D A_GUSB2I2CCTL, + .ro =3D 0xffffffff, + .unimp =3D 0xffffffff, + },{ .name =3D "GUSB2PHYACC_ULPI", .addr =3D A_GUSB2PHYACC_ULPI, + .ro =3D 0xfd000000, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ0", .addr =3D A_GTXFIFOSIZ0, + .reset =3D 0x2c7000a, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ1", .addr =3D A_GTXFIFOSIZ1, + .reset =3D 0x2d10103, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ2", .addr =3D A_GTXFIFOSIZ2, + .reset =3D 0x3d40103, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ3", .addr =3D A_GTXFIFOSIZ3, + .reset =3D 0x4d70083, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ4", .addr =3D A_GTXFIFOSIZ4, + .reset =3D 0x55a0083, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOSIZ5", .addr =3D A_GTXFIFOSIZ5, + .reset =3D 0x5dd0083, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ0", .addr =3D A_GRXFIFOSIZ0, + .reset =3D 0x1c20105, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ1", .addr =3D A_GRXFIFOSIZ1, + .reset =3D 0x2c70000, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOSIZ2", .addr =3D A_GRXFIFOSIZ2, + .reset =3D 0x2c70000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_0", .addr =3D A_GEVNTADRLO_0, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_0", .addr =3D A_GEVNTADRHI_0, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_0", .addr =3D A_GEVNTSIZ_0, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_0", .addr =3D A_GEVNTCOUNT_0, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_1", .addr =3D A_GEVNTADRLO_1, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_1", .addr =3D A_GEVNTADRHI_1, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_1", .addr =3D A_GEVNTSIZ_1, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_1", .addr =3D A_GEVNTCOUNT_1, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_2", .addr =3D A_GEVNTADRLO_2, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_2", .addr =3D A_GEVNTADRHI_2, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_2", .addr =3D A_GEVNTSIZ_2, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_2", .addr =3D A_GEVNTCOUNT_2, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRLO_3", .addr =3D A_GEVNTADRLO_3, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTADRHI_3", .addr =3D A_GEVNTADRHI_3, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTSIZ_3", .addr =3D A_GEVNTSIZ_3, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GEVNTCOUNT_3", .addr =3D A_GEVNTCOUNT_3, + .ro =3D 0x7fff0000, + .unimp =3D 0xffffffff, + },{ .name =3D "GHWPARAMS8", .addr =3D A_GHWPARAMS8, + .ro =3D 0xffffffff, + .reset =3D 0x478, + },{ .name =3D "GTXFIFOPRIDEV", .addr =3D A_GTXFIFOPRIDEV, + .ro =3D 0xffffffc0, + .unimp =3D 0xffffffff, + },{ .name =3D "GTXFIFOPRIHST", .addr =3D A_GTXFIFOPRIHST, + .ro =3D 0xfffffff8, + .unimp =3D 0xffffffff, + },{ .name =3D "GRXFIFOPRIHST", .addr =3D A_GRXFIFOPRIHST, + .ro =3D 0xfffffff8, + .unimp =3D 0xffffffff, + },{ .name =3D "GDMAHLRATIO", .addr =3D A_GDMAHLRATIO, + .ro =3D 0xffffe0e0, + .unimp =3D 0xffffffff, + },{ .name =3D "GFLADJ", .addr =3D A_GFLADJ, + .reset =3D 0xc83f020, + .rsvd =3D 0x40, + .ro =3D 0x400040, + .unimp =3D 0xffffffff, + } +}; + +static void usb_dwc3_reset(DeviceState *dev) +{ + USBDWC3 *s =3D USB_DWC3(dev); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } + + /* + * Device Configuration + */ + s->regs[R_GHWPARAMS0] |=3D s->cfg.mode; + xhci_sysbus_reset(DEVICE(&s->sysbus_xhci)); +} + +static const MemoryRegionOps usb_dwc3_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void usb_dwc3_realize(DeviceState *dev, Error **errp) +{ + USBDWC3 *s =3D USB_DWC3(dev); + Error *err =3D NULL; + + sysbus_realize(SYS_BUS_DEVICE(&s->sysbus_xhci), &err); + if (err) { + error_propagate(errp, err); + return; + } +} + +static void usb_dwc3_init(Object *obj) +{ + USBDWC3 *s =3D USB_DWC3(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_USB_DWC3, USB_DWC3_R_MAX * 4); + reg_array =3D + register_init_block32(DEVICE(obj), usb_dwc3_regs_info, + ARRAY_SIZE(usb_dwc3_regs_info), + s->regs_info, s->regs, + &usb_dwc3_ops, + USB_DWC3_ERR_DEBUG, + USB_DWC3_R_MAX * 4); + memory_region_add_subregion(&s->iomem, + 0x0, + ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + object_initialize_child(obj, "dwc3-xhci", &s->sysbus_xhci, + TYPE_XHCI_SYSBUS); + qdev_alias_all_properties(DEVICE(&s->sysbus_xhci), obj); + + s->cfg.mode =3D HOST_MODE; +} + +static Property usb_dwc3_properties[] =3D { + DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user, + 0x12345678), + DEFINE_PROP_END_OF_LIST(), +}; + +static void usb_dwc3_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D usb_dwc3_reset; + dc->realize =3D usb_dwc3_realize; + device_class_set_props(dc, usb_dwc3_properties); +} + +static const TypeInfo usb_dwc3_info =3D { + .name =3D TYPE_USB_DWC3, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(USBDWC3), + .class_init =3D usb_dwc3_class_init, + .instance_init =3D usb_dwc3_init, +}; + +static void usb_dwc3_register_types(void) +{ + type_register_static(&usb_dwc3_info); +} + +type_init(usb_dwc3_register_types) diff --git a/hw/usb/meson.build b/hw/usb/meson.build index 934e4fa..962fbc0 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -26,6 +26,7 @@ softmmu_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: f= iles('hcd-xhci-sysbus.c softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c= ')) softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c')) softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c')) +softmmu_ss.add(when: 'CONFIG_USB_DWC3', if_true: files('hcd-dwc3.c')) =20 softmmu_ss.add(when: 'CONFIG_TUSB6010', if_true: files('tusb6010.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('chipidea.c')) diff --git a/include/hw/usb/hcd-dwc3.h b/include/hw/usb/hcd-dwc3.h new file mode 100644 index 0000000..586968d --- /dev/null +++ b/include/hw/usb/hcd-dwc3.h @@ -0,0 +1,55 @@ +/* + * QEMU model of the USB DWC3 host controller emulation. + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written by Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ +#ifndef HCD_DWC3_H +#define HCD_DWC3_H + +#include "hw/usb/hcd-xhci.h" +#include "hw/usb/hcd-xhci-sysbus.h" + +#define TYPE_USB_DWC3 "usb_dwc3" + +#define USB_DWC3(obj) \ + OBJECT_CHECK(USBDWC3, (obj), TYPE_USB_DWC3) + +#define USB_DWC3_R_MAX ((0x530 / 4) + 1) + +typedef struct USBDWC3 { + SysBusDevice parent_obj; + MemoryRegion iomem; + MemoryRegion fifos; + XHCISysbusState sysbus_xhci; + + uint32_t regs[USB_DWC3_R_MAX]; + RegisterInfo regs_info[USB_DWC3_R_MAX]; + + struct { + uint8_t mode; + uint32_t dwc_usb3_user; + } cfg; + +} USBDWC3; + +#endif --=20 2.7.4 From nobody Sat May 18 18:27:41 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1603369353; cv=pass; d=zohomail.com; s=zohoarc; b=ZE5ESp/a3zKAcbiGFv7bSJo6UolIDr4QqDscWGicBYZzh/Pc7LFnLWF6u1sUtyWezegey6DAMjr33KETGUUq90Y/mnrgU7J5UhAqHOSrcJ7qKPw/GpLC+T8p8JPNgHXOAN0spgQBCCrTc8yWA+sSIrqYTC7pYdVcdOGD50uwFXA= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1603369353; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CpS5wTrc2KnbUEerqqlBfQebpwWGtlC+idsmUxiPWHU=; b=mTsUx7jKNGEEYGGDDivwkxUP4aEFdP+OFbdO2CF4vIN/D68L5ZxKU9ZgxTuIkB8lJrI3jISbCns5SVfzRAuMRdALSzGSvVwu2hOqPvuksiS2nTT0mS9oFYViOOyFBSqxbUzYpJZeOoDrAeWxlBnx873k0TxG2q3zSecoApcoiKA= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16033693531971009.126611967441; Thu, 22 Oct 2020 05:22:33 -0700 (PDT) Received: from localhost ([::1]:52862 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kVZc0-0006hk-0B for importer@patchew.org; Thu, 22 Oct 2020 08:22:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVZTF-0007h2-W7 for qemu-devel@nongnu.org; Thu, 22 Oct 2020 08:13:30 -0400 Received: from mail-mw2nam10on2068.outbound.protection.outlook.com ([40.107.94.68]:23921 helo=NAM10-MW2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kVZRZ-00013E-Oc for qemu-devel@nongnu.org; Thu, 22 Oct 2020 08:13:29 -0400 Received: from MN2PR06CA0001.namprd06.prod.outlook.com (2603:10b6:208:23d::6) by MWHPR02MB2383.namprd02.prod.outlook.com (2603:10b6:300:5c::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3477.20; Thu, 22 Oct 2020 12:11:42 +0000 Received: from BL2NAM02FT064.eop-nam02.prod.protection.outlook.com (2603:10b6:208:23d:cafe::9) by MN2PR06CA0001.outlook.office365.com (2603:10b6:208:23d::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3499.18 via Frontend Transport; Thu, 22 Oct 2020 12:11:42 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT064.mail.protection.outlook.com (10.152.77.119) with Microsoft SMTP Server id 15.20.3477.23 via Frontend Transport; Thu, 22 Oct 2020 12:11:41 +0000 Received: from [149.199.38.66] (port=56481 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1kVZQY-0001kC-NU; Thu, 22 Oct 2020 05:10:42 -0700 Received: from [127.0.0.1] (helo=xsj-smtp-dlp1.xlnx.xilinx.com) by smtp.xilinx.com with esmtp (Exim 4.63) (envelope-from ) id 1kVZRU-0005qS-GQ; Thu, 22 Oct 2020 05:11:40 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp1.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 09MCBdkv022867; Thu, 22 Oct 2020 05:11:39 -0700 Received: from [10.140.6.35] (helo=xhdsaipava40.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kVZRS-0005pv-VX; Thu, 22 Oct 2020 05:11:39 -0700 Received: by xhdsaipava40.xilinx.com (Postfix, from userid 14131) id 47BD913C0964; Thu, 22 Oct 2020 17:47:51 +0530 (IST) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=kRHCrAULw/HZVHEVhVbFrvBjupRG4YaQhRyj51726O7j47nXM7MVJIcnkHSeEalSpnotGRuRNvzmESlHp5pZw3VCpebqK4f7PhOq1XQVj+Q7EuKLTwDeyHwjw3+m91NuLG1IPak8Fqb0pWfFZgQhr8C5JLZwMDO7ufYvHHu5d5zwRXCtP8mdDNI57DX8Ub3JpCuGh9j05UDMmQYhr/0CuCkm03hxTeaDw9xRRlfmQYFaB2WZ331TdFBW5ZcoDcLRqb2GmdS6w2+3cmH+1buydFyOFmQFUbGn/a1arWHGaRcr3aYGNlXxxkugx5kqldPRtVRGQZn3Q0E9uDiWb+oUhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CpS5wTrc2KnbUEerqqlBfQebpwWGtlC+idsmUxiPWHU=; b=aYeMxAAbU+rbmlE0RwAKLOoHyHhqIGMwLJzJ/t8cE77ucJH62xcETqQkSE6zMUQiFglB81rifTMIoh18QNDyEuy/l8ape654I/7lWOsqwQNP8W6R0IC6nsjit5M/oFdNH5QkIBC7w7W9dVoMTEqOlXJxi+22QBRHHNtlksRD6W48RCier515wt6xGr0+TtAPHpmFd+LVfeYirmHB/abOIu1hTFaQvldYahWgz1HnBngMIo5PwlJajajY96KTIl9D1xAGsMHIxJ3EzQhoxA9VNZ/+WEiDryKOyW0V8tIA28GQO9K78zxo4Ym17w1l+NWfUMkcRVdjayd4a0CWfP7FUw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=wdc.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CpS5wTrc2KnbUEerqqlBfQebpwWGtlC+idsmUxiPWHU=; b=L1KtskaapEV6XGVsJZJemuYUfkWIrunHgq+E/xHwEo0M0x1MXIFt3p6pTg09TZRsAa/EVcG4DJcUltX6eIe0BHIaRDfWyE0vNV+qHvRBKpP6nIzLmxjgGWCajffUWtkkYLrqNUbcXnPLCX5tnHi0mAUVd90640Y3T8PBeARA7sI= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; wdc.com; dkim=none (message not signed) header.d=none;wdc.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; From: Sai Pavan Boddu To: Peter Maydell , Markus Armbruster , =?UTF-8?q?=27Marc-Andr=C3=A9=20Lureau=27?= , Paolo Bonzini , Gerd Hoffmann , Edgar Iglesias , Francisco Eduardo Iglesias Subject: [PATCH v12 3/3] Versal: Connect DWC3 controller with virt-versal Date: Thu, 22 Oct 2020 17:47:36 +0530 Message-Id: <1603369056-4168-4-git-send-email-sai.pavan.boddu@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1603369056-4168-1-git-send-email-sai.pavan.boddu@xilinx.com> References: <1603369056-4168-1-git-send-email-sai.pavan.boddu@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: c4fdbe98-34d1-49b4-af85-08d87683a27d X-MS-TrafficTypeDiagnostic: MWHPR02MB2383: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:142; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: sQcjN1E85REXmzKP2nJzGjJkvzbyWHdl3zYrkhGuO3c2EnKcruNNTYsYiSoGxmn6WijuWf2Kuh7ajax4aYLKUaQ/CuIXfRaenmsb/pvUsxVRBflCBkHB2iCld8xkV9P7S/1PXk87vygy1GpWZ6EvHauY9aX5AhQr8thP4sJQlraSJ9AUyRtCpVDyrWR/XjRPbgyt/P2K7lpwuBaQKs966Kf2oM0XrhjyHJR+HVhhBASY7GiQknGsQLWh0FT25ezRlSYviCWFER37aX5mft1hX9nh868NSiwFCM6lKtUNoS/f3ezJLJtD+Ud6VTdV5BetlOh6a1qd8Wm3Lz84MA8GAcf7XhqCIPWYGQA9uTETWm0OkeZLA88YUEerkIX9MERkmhLqv15GoJ4eVy1gU8n08w== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:ErrorRetry; CAT:NONE; SFS:(39860400002)(376002)(396003)(346002)(136003)(46966005)(36756003)(2906002)(5660300002)(336012)(82310400003)(110136005)(316002)(70586007)(70206006)(42186006)(83380400001)(356005)(6666004)(8676002)(26005)(2616005)(8936002)(4326008)(7416002)(82740400003)(186003)(54906003)(6636002)(426003)(19627235002)(47076004)(6266002)(478600001)(107886003)(81166007); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Oct 2020 12:11:41.1684 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c4fdbe98-34d1-49b4-af85-08d87683a27d X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT064.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR02MB2383 Received-SPF: pass client-ip=40.107.94.68; envelope-from=saipava@xilinx.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/10/22 08:11:44 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Eduardo Habkost , Vikram Garhwal , qemu-devel@nongnu.org, Paul Zimmerman , Sai Pavan Boddu , Alistair Francis , Ying Fang , =?UTF-8?q?=27Philippe=20Mathieu-Daud=C3=A9=27?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Vikram Garhwal Connect dwc3 controller and usb2-reg module to xlnx-versal SOC, its placed in iou of lpd domain and configure it as dual port host controller. Add the respective guest dts nodes for "xlnx-versal-virt" machine. Signed-off-by: Vikram Garhwal Signed-off-by: Sai Pavan Boddu Reviewed-by: Edgar E. Iglesias --- hw/arm/xlnx-versal-virt.c | 58 ++++++++++++++++++++++++++++++++++++++++= ++++ hw/arm/xlnx-versal.c | 34 ++++++++++++++++++++++++++ include/hw/arm/xlnx-versal.h | 14 +++++++++++ 3 files changed, 106 insertions(+) diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 03e2320..f0ac5ba 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -39,6 +39,8 @@ struct VersalVirt { uint32_t ethernet_phy[2]; uint32_t clk_125Mhz; uint32_t clk_25Mhz; + uint32_t usb; + uint32_t dwc; } phandle; struct arm_boot_info binfo; =20 @@ -66,6 +68,8 @@ static void fdt_create(VersalVirt *s) s->phandle.clk_25Mhz =3D qemu_fdt_alloc_phandle(s->fdt); s->phandle.clk_125Mhz =3D qemu_fdt_alloc_phandle(s->fdt); =20 + s->phandle.usb =3D qemu_fdt_alloc_phandle(s->fdt); + s->phandle.dwc =3D qemu_fdt_alloc_phandle(s->fdt); /* Create /chosen node for load_dtb. */ qemu_fdt_add_subnode(s->fdt, "/chosen"); =20 @@ -148,6 +152,59 @@ static void fdt_add_timer_nodes(VersalVirt *s) compat, sizeof(compat)); } =20 +static void fdt_add_usb_xhci_nodes(VersalVirt *s) +{ + const char clocknames[] =3D "bus_clk\0ref_clk"; + char *name =3D g_strdup_printf("/usb@%" PRIx32, MM_USB2_CTRL_REGS); + const char compat[] =3D "xlnx,versal-dwc3"; + + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB2_CTRL_REGS, + 2, MM_USB2_CTRL_REGS_SIZE); + qemu_fdt_setprop(s->fdt, name, "clock-names", + clocknames, sizeof(clocknames)); + qemu_fdt_setprop_cells(s->fdt, name, "clocks", + s->phandle.clk_25Mhz, s->phandle.clk_125Mhz= ); + qemu_fdt_setprop(s->fdt, name, "ranges", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 2); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.usb); + g_free(name); + + { + const char irq_name[] =3D "dwc_usb3"; + const char compat[] =3D "snps,dwc3"; + + name =3D g_strdup_printf("/usb@%" PRIx32 "/dwc3@%" PRIx32, + MM_USB2_CTRL_REGS, MM_USB_XHCI_0); + qemu_fdt_add_subnode(s->fdt, name); + qemu_fdt_setprop(s->fdt, name, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", + 2, MM_USB_XHCI_0, 2, MM_USB_XHCI_0_SI= ZE); + qemu_fdt_setprop(s->fdt, name, "interrupt-names", + irq_name, sizeof(irq_name)); + qemu_fdt_setprop_cells(s->fdt, name, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, VERSAL_USB0_IRQ_0, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(s->fdt, name, + "snps,quirk-frame-length-adjustment", 0x20); + qemu_fdt_setprop_cells(s->fdt, name, "#stream-id-cells", 1); + qemu_fdt_setprop_string(s->fdt, name, "dr_mode", "host"); + qemu_fdt_setprop_string(s->fdt, name, "phy-names", "usb3-phy"); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u2_susphy_quirk", NULL, 0= ); + qemu_fdt_setprop(s->fdt, name, "snps,dis_u3_susphy_quirk", NULL, 0= ); + qemu_fdt_setprop(s->fdt, name, "snps,refclk_fladj", NULL, 0); + qemu_fdt_setprop(s->fdt, name, "snps,mask_phy_reset", NULL, 0); + qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); + qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed= "); + g_free(name); + } +} + static void fdt_add_uart_nodes(VersalVirt *s) { uint64_t addrs[] =3D { MM_UART1, MM_UART0 }; @@ -515,6 +572,7 @@ static void versal_virt_init(MachineState *machine) fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); fdt_add_zdma_nodes(s); + fdt_add_usb_xhci_nodes(s); fdt_add_sd_nodes(s); fdt_add_rtc_node(s); fdt_add_cpu_nodes(s, psci_conduit); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 12ba6c4..ddf43db 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -145,6 +145,39 @@ static void versal_create_uarts(Versal *s, qemu_irq *p= ic) } } =20 +static void versal_create_usbs(Versal *s, qemu_irq *pic) +{ + DeviceState *dev, *xhci_dev; + MemoryRegion *mr; + + object_initialize_child(OBJECT(s), "dwc3-0", &s->lpd.iou.usb.dwc3, + TYPE_USB_DWC3); + dev =3D DEVICE(&s->lpd.iou.usb.dwc3); + xhci_dev =3D DEVICE(&s->lpd.iou.usb.dwc3.sysbus_xhci); + + object_property_set_link(OBJECT(xhci_dev), "dma", OBJECT(&s->mr_ps), + &error_abort); + qdev_prop_set_uint32(xhci_dev, "intrs", 1); + qdev_prop_set_uint32(xhci_dev, "slots", 2); + + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0_DWC3_GLOBAL, mr); + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(xhci_dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB_XHCI_0, mr); + + sysbus_connect_irq(SYS_BUS_DEVICE(xhci_dev), 0, pic[VERSAL_USB0_IRQ_0]= ); + + object_initialize_child(OBJECT(s), "usb2ctrl-0", &s->lpd.iou.usb.ctrl, + TYPE_XILINX_VERSAL_USB2_CTRL_REGS); + dev =3D DEVICE(&s->lpd.iou.usb.ctrl); + sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); +} + static void versal_create_gems(Versal *s, qemu_irq *pic) { int i; @@ -333,6 +366,7 @@ static void versal_realize(DeviceState *dev, Error **er= rp) versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); versal_create_uarts(s, pic); + versal_create_usbs(s, pic); versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_sds(s, pic); diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 8ce8e63..e0a6c66 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -21,6 +21,8 @@ #include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" +#include "hw/usb/hcd-dwc3.h" +#include "hw/misc/xlnx-versal-usb2-ctrl-regs.h" =20 #define TYPE_XLNX_VERSAL "xlnx-versal" OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) @@ -59,6 +61,10 @@ struct Versal { PL011State uart[XLNX_VERSAL_NR_UARTS]; CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; + struct { + USBDWC3 dwc3; + VersalUsb2CtrlRegs ctrl; + } usb; } iou; } lpd; =20 @@ -88,6 +94,7 @@ struct Versal { =20 #define VERSAL_UART0_IRQ_0 18 #define VERSAL_UART1_IRQ_0 19 +#define VERSAL_USB0_IRQ_0 22 #define VERSAL_GEM0_IRQ_0 56 #define VERSAL_GEM0_WAKE_IRQ_0 57 #define VERSAL_GEM1_IRQ_0 58 @@ -125,6 +132,13 @@ struct Versal { #define MM_OCM 0xfffc0000U #define MM_OCM_SIZE 0x40000 =20 +#define MM_USB2_CTRL_REGS 0xFF9D0000 +#define MM_USB2_CTRL_REGS_SIZE 0x10000 + +#define MM_USB_XHCI_0 0xFE200000 +#define MM_USB_XHCI_0_SIZE 0x10000 +#define MM_USB_XHCI_0_DWC3_GLOBAL (MM_USB_XHCI_0 + 0xC100) + #define MM_TOP_DDR 0x0 #define MM_TOP_DDR_SIZE 0x80000000U #define MM_TOP_DDR_2 0x800000000ULL --=20 2.7.4