From nobody Sun May 19 02:38:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1600121491; cv=pass; d=zohomail.com; s=zohoarc; b=GgxjphwRQB2z4S/CJwtQjJ7clq7m4z4hyMkElPKZqpIiFArw7su+fGJ/NlZp/fW7UFEZIVzpXdJzxvNfUtPHhDffP/BLGPnUG+HxXfq8aLG0YnrWn/KHV1HxviEnVqNtBRH3fPUENQFzwqFc31ekOm+5Vz/IcCT3VCyCvtV/eXM= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600121491; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sb5xEgVsW8s8bV9cYfC02BH/t5eXdUooy9cbwpZHaGg=; b=B7iP/j+7ip3C+0gc2zuaSfWD1qcqdlajLHxHcmjeIotf5F6rCGAEAYE7+82DZcqO11QrP1vYtFSbp7VJmk8UjO3fMBc7b9lNGdQjsKE5gxgFy5hJ18FnEP5Wv71B5BMIL4CUsn019b4U8RE8E/38XBrtyYbonioH2o+coslFJik= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1600121491501665.2263661652296; Mon, 14 Sep 2020 15:11:31 -0700 (PDT) Received: from localhost ([::1]:38834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kHwh8-0003jw-8b for importer@patchew.org; Mon, 14 Sep 2020 18:11:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwfA-0001yb-HN; Mon, 14 Sep 2020 18:09:28 -0400 Received: from mail-bn8nam12on2066.outbound.protection.outlook.com ([40.107.237.66]:6049 helo=NAM12-BN8-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwf4-0000ZW-MK; Mon, 14 Sep 2020 18:09:28 -0400 Received: from DM6PR01CA0014.prod.exchangelabs.com (2603:10b6:5:296::19) by CY4PR02MB3224.namprd02.prod.outlook.com (2603:10b6:910:7a::12) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.19; Mon, 14 Sep 2020 22:09:18 +0000 Received: from CY1NAM02FT032.eop-nam02.prod.protection.outlook.com (2603:10b6:5:296:cafe::47) by DM6PR01CA0014.outlook.office365.com (2603:10b6:5:296::19) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:18 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT032.mail.protection.outlook.com (10.152.75.184) with Microsoft SMTP Server id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:17 +0000 Received: from [149.199.38.66] (port=48263 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1kHweu-0003rZ-4t; Mon, 14 Sep 2020 15:09:12 -0700 Received: from [127.0.0.1] (helo=localhost) by smtp.xilinx.com with smtp (Exim 4.63) (envelope-from ) id 1kHwey-0006ms-Uq; Mon, 14 Sep 2020 15:09:16 -0700 Received: from xsj-pvapsmtp01 (maildrop.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 08EM95uw011995; Mon, 14 Sep 2020 15:09:06 -0700 Received: from [172.19.2.115] (helo=xsjfnuv50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kHwen-0006b8-NJ; Mon, 14 Sep 2020 15:09:05 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=WKrDKiAn+DUR9q4wIcsN+72cZ4Mx/9V5srKlUwLE1gU6LiY9Pu4aQ3Adq1AMougmF8Up/GEiLRQxDhXua4Cq+A8AnF29/LVF1nta2GN/GmylZuDX3eILdA4xSUOzSnlMbLxF5gOxI0ByUwINRHo8MKi4tnWT3FhtEFY3s2IMlSeX7beGazF5/UnW6IjDkFUHfJgVaJsCHY4EZ6boLgsCFA7un134LHnNHK1mjQCd17gW6XXQsnKQKeckBOgvkVJaZgubv5m9cRt5BdKarvFKjJTD5A1ju7UyxVSnci/Sq/6/hxc82rWOCcqeXAvOQlZznBuI8EUxeP142gt/mV/Rrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sb5xEgVsW8s8bV9cYfC02BH/t5eXdUooy9cbwpZHaGg=; b=DRdJ8m8+L+h2/VVyNj2hDIvoDKX2q1V8OGA0Rrw5TIFmGZ8DsLDqPH9mQ2pUpdhbWQu3JpT9onBEto1zI9MpFbwU/RYJ6rKL3LIlcegnjniLNPUP8kpx9UF/au2Gtw9Y0fxtEAVi6Um+ZoCX90kGlgUoZcq3DWr1dghqb8ToPqVLnpI2ciqw/3hITWBCZfrjWCLdQH7mgdgyCsp48iOl8hLgK0oa1FoPlpHkAGtzGX4inkADxAzJrtOI2Jni5CguXOD4N22Ym0AUN3TPrOHBNyFgFkweM70/rxQaU4pxh4v3gzsPL7drNQCLe4aLHag0IN3+1VcktflzxZoUf+57bg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=sb5xEgVsW8s8bV9cYfC02BH/t5eXdUooy9cbwpZHaGg=; b=pJX7X+qQfxOJEgYOPOBhxi6nDEy597iF8fcrvd3Vsahfsk7nAWYdMOqGpbFTrpKqiD7OLlWsGoKBY1blxlWWhDlJC4VbQ/9/E0BpwtFD8k4hO7sfSRTUn0BM1+1xGqlLVhasxrN8uqiCuO4kpRzFmoP6EPQORhjXUSZBM1Njh5E= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; nongnu.org; dkim=none (message not signed) header.d=none;nongnu.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; From: Vikram Garhwal To: qemu-devel@nongnu.org Subject: [PATCH v10 1/4] hw/net/can: Introduce Xilinx ZynqMP CAN controller Date: Mon, 14 Sep 2020 15:08:41 -0700 Message-Id: <1600121324-31337-2-git-send-email-fnu.vikram@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> References: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 0960c855-47ca-4678-d529-08d858fad2a0 X-MS-TrafficTypeDiagnostic: CY4PR02MB3224: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:3044; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +iQTwhC4rkpkaOvKhAbUiop5PncakUHsE6QmyOEo7RCw/7sSNCiwFRvQL3wtoYuXewSwgLOi006E2nqq5uPVeCFyRA670UW0koH3IvHKY0mQnRYP7BjYsUvDvNcM53Qp0BxxO4+H/jaN5mn33Kq9KjtaKw9OkYQCnbvgZeN7GxvHrKCFkOVSohjaa9tYcZJePewQstXV1M+KyeAewJL+T+g7e9vkSzCwaxkWVnnDPHAD54dTPU4rGU/7Gjy0Ute8s1ndWZFU64FTQGL4sjwYAACNe7jDsk//pBuPTwlA6ZV98JoQc+2boR9jv4Lmv8oy2uphXLhvh6xIn/Z7+LF/4x2ApZJFTn5MOX0U9fi8PLyUu+V+URf9GhxLCOgChpD17zBSJNyCMarHOExxGCcluGRxH5MILwQPvCYb5xhHm0VA42Q5CFRvXy4Y0D+aj4MfIiNK9Llv3IuMRt2x1K+S/aFfaALjPG/SQvlp+rpXDZZ7rLIjh3oeEPiGY1q2bTGf X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(136003)(396003)(376002)(346002)(39860400002)(46966005)(4326008)(426003)(336012)(966005)(8676002)(9786002)(8936002)(2906002)(26005)(54906003)(478600001)(6916009)(36756003)(186003)(2616005)(316002)(7696005)(83380400001)(5660300002)(30864003)(47076004)(82740400003)(70586007)(82310400003)(356005)(6666004)(81166007)(70206006)(579004)(6606295002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2020 22:09:17.1669 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0960c855-47ca-4678-d529-08d858fad2a0 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT032.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR02MB3224 Received-SPF: pass client-ip=40.107.237.66; envelope-from=fnuv@xilinx.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/14 18:09:21 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Vikram Garhwal , Jason Wang , Alistair Francis , francisco.iglesias@xilinx.com, "open list:Xilinx ZynqMP and..." , "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Xilinx ZynqMP CAN controller is developed based on SocketCAN, QEMU CAN = bus implementation. Bus connection and socketCAN connection for each CAN module can be set through command lines. Example for using single CAN: -object can-bus,id=3Dcanbus0 \ -machine xlnx-zcu102.canbus0=3Dcanbus0 \ -object can-host-socketcan,id=3Dsocketcan0,if=3Dvcan0,canbus=3Dcanbus0 Example for connecting both CAN to same virtual CAN on host machine: -object can-bus,id=3Dcanbus0 -object can-bus,id=3Dcanbus1 \ -machine xlnx-zcu102.canbus0=3Dcanbus0 \ -machine xlnx-zcu102.canbus1=3Dcanbus1 \ -object can-host-socketcan,id=3Dsocketcan0,if=3Dvcan0,canbus=3Dcanbus0 \ -object can-host-socketcan,id=3Dsocketcan1,if=3Dvcan0,canbus=3Dcanbus1 To create virtual CAN on the host machine, please check the QEMU CAN docs: https://github.com/qemu/qemu/blob/master/docs/can.txt Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Vikram Garhwal --- hw/Kconfig | 1 + hw/net/can/meson.build | 1 + hw/net/can/xlnx-zynqmp-can.c | 1165 ++++++++++++++++++++++++++++++++++= ++++ include/hw/net/xlnx-zynqmp-can.h | 78 +++ 4 files changed, 1245 insertions(+) create mode 100644 hw/net/can/xlnx-zynqmp-can.c create mode 100644 include/hw/net/xlnx-zynqmp-can.h diff --git a/hw/Kconfig b/hw/Kconfig index 4de1797..5ad3c6b 100644 --- a/hw/Kconfig +++ b/hw/Kconfig @@ -80,3 +80,4 @@ config XILINX_AXI config XLNX_ZYNQMP bool select REGISTER + select CAN_BUS diff --git a/hw/net/can/meson.build b/hw/net/can/meson.build index c9cfeb7..efb07cb 100644 --- a/hw/net/can/meson.build +++ b/hw/net/can/meson.build @@ -2,3 +2,4 @@ softmmu_ss.add(when: 'CONFIG_CAN_SJA1000', if_true: files('= can_sja1000.c')) softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_kvaser_pci.c')) softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_pcm3680_pci.c')) softmmu_ss.add(when: 'CONFIG_CAN_PCI', if_true: files('can_mioe3680_pci.c'= )) +softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP', if_true: files('xlnx-zynqmp-can= .c')) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c new file mode 100644 index 0000000..367230c --- /dev/null +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -0,0 +1,1165 @@ +/* + * QEMU model of the Xilinx ZynqMP CAN controller. + * This implementation is based on the following datasheet: + * https://www.xilinx.com/support/documentation/user_guides/ug1085-zynq-ul= trascale-trm.pdf + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written-by: Vikram Garhwal + * + * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren = and + * Pavel Pisa + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "hw/register.h" +#include "hw/irq.h" +#include "qapi/error.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qemu/cutils.h" +#include "sysemu/sysemu.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "net/can_emu.h" +#include "net/can_host.h" +#include "qemu/event_notifier.h" +#include "qom/object_interfaces.h" +#include "hw/net/xlnx-zynqmp-can.h" + +#ifndef XLNX_ZYNQMP_CAN_ERR_DEBUG +#define XLNX_ZYNQMP_CAN_ERR_DEBUG 0 +#endif + +#define DB_PRINT(dev, ...) do { \ + if (XLNX_ZYNQMP_CAN_ERR_DEBUG) { \ + g_autofree char *path =3D object_get_canonical_path(OBJECT(dev)); \ + qemu_log("%s: %s", path, ## __VA_ARGS__); \ + } \ +} while (0) + +#define MAX_DLC 8 +#undef ERROR + +REG32(SOFTWARE_RESET_REGISTER, 0x0) + FIELD(SOFTWARE_RESET_REGISTER, CEN, 1, 1) + FIELD(SOFTWARE_RESET_REGISTER, SRST, 0, 1) +REG32(MODE_SELECT_REGISTER, 0x4) + FIELD(MODE_SELECT_REGISTER, SNOOP, 2, 1) + FIELD(MODE_SELECT_REGISTER, LBACK, 1, 1) + FIELD(MODE_SELECT_REGISTER, SLEEP, 0, 1) +REG32(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, 0x8) + FIELD(ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, BRP, 0, 8) +REG32(ARBITRATION_PHASE_BIT_TIMING_REGISTER, 0xc) + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, SJW, 7, 2) + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS2, 4, 3) + FIELD(ARBITRATION_PHASE_BIT_TIMING_REGISTER, TS1, 0, 4) +REG32(ERROR_COUNTER_REGISTER, 0x10) + FIELD(ERROR_COUNTER_REGISTER, REC, 8, 8) + FIELD(ERROR_COUNTER_REGISTER, TEC, 0, 8) +REG32(ERROR_STATUS_REGISTER, 0x14) + FIELD(ERROR_STATUS_REGISTER, ACKER, 4, 1) + FIELD(ERROR_STATUS_REGISTER, BERR, 3, 1) + FIELD(ERROR_STATUS_REGISTER, STER, 2, 1) + FIELD(ERROR_STATUS_REGISTER, FMER, 1, 1) + FIELD(ERROR_STATUS_REGISTER, CRCER, 0, 1) +REG32(STATUS_REGISTER, 0x18) + FIELD(STATUS_REGISTER, SNOOP, 12, 1) + FIELD(STATUS_REGISTER, ACFBSY, 11, 1) + FIELD(STATUS_REGISTER, TXFLL, 10, 1) + FIELD(STATUS_REGISTER, TXBFLL, 9, 1) + FIELD(STATUS_REGISTER, ESTAT, 7, 2) + FIELD(STATUS_REGISTER, ERRWRN, 6, 1) + FIELD(STATUS_REGISTER, BBSY, 5, 1) + FIELD(STATUS_REGISTER, BIDLE, 4, 1) + FIELD(STATUS_REGISTER, NORMAL, 3, 1) + FIELD(STATUS_REGISTER, SLEEP, 2, 1) + FIELD(STATUS_REGISTER, LBACK, 1, 1) + FIELD(STATUS_REGISTER, CONFIG, 0, 1) +REG32(INTERRUPT_STATUS_REGISTER, 0x1c) + FIELD(INTERRUPT_STATUS_REGISTER, TXFEMP, 14, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXFWMEMP, 13, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXFWMFLL, 12, 1) + FIELD(INTERRUPT_STATUS_REGISTER, WKUP, 11, 1) + FIELD(INTERRUPT_STATUS_REGISTER, SLP, 10, 1) + FIELD(INTERRUPT_STATUS_REGISTER, BSOFF, 9, 1) + FIELD(INTERRUPT_STATUS_REGISTER, ERROR, 8, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXNEMP, 7, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXOFLW, 6, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXUFLW, 5, 1) + FIELD(INTERRUPT_STATUS_REGISTER, RXOK, 4, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXBFLL, 3, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXFLL, 2, 1) + FIELD(INTERRUPT_STATUS_REGISTER, TXOK, 1, 1) + FIELD(INTERRUPT_STATUS_REGISTER, ARBLST, 0, 1) +REG32(INTERRUPT_ENABLE_REGISTER, 0x20) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFEMP, 14, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFWMEMP, 13, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXFWMFLL, 12, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EWKUP, 11, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ESLP, 10, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EBSOFF, 9, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EERROR, 8, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXNEMP, 7, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXOFLW, 6, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXUFLW, 5, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ERXOK, 4, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXBFLL, 3, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXFLL, 2, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, ETXOK, 1, 1) + FIELD(INTERRUPT_ENABLE_REGISTER, EARBLST, 0, 1) +REG32(INTERRUPT_CLEAR_REGISTER, 0x24) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFEMP, 14, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFWMEMP, 13, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXFWMFLL, 12, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CWKUP, 11, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CSLP, 10, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CBSOFF, 9, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CERROR, 8, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXNEMP, 7, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXOFLW, 6, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXUFLW, 5, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CRXOK, 4, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXBFLL, 3, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXFLL, 2, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CTXOK, 1, 1) + FIELD(INTERRUPT_CLEAR_REGISTER, CARBLST, 0, 1) +REG32(TIMESTAMP_REGISTER, 0x28) + FIELD(TIMESTAMP_REGISTER, CTS, 0, 1) +REG32(WIR, 0x2c) + FIELD(WIR, EW, 8, 8) + FIELD(WIR, FW, 0, 8) +REG32(TXFIFO_ID, 0x30) + FIELD(TXFIFO_ID, IDH, 21, 11) + FIELD(TXFIFO_ID, SRRRTR, 20, 1) + FIELD(TXFIFO_ID, IDE, 19, 1) + FIELD(TXFIFO_ID, IDL, 1, 18) + FIELD(TXFIFO_ID, RTR, 0, 1) +REG32(TXFIFO_DLC, 0x34) + FIELD(TXFIFO_DLC, DLC, 28, 4) +REG32(TXFIFO_DATA1, 0x38) + FIELD(TXFIFO_DATA1, DB0, 24, 8) + FIELD(TXFIFO_DATA1, DB1, 16, 8) + FIELD(TXFIFO_DATA1, DB2, 8, 8) + FIELD(TXFIFO_DATA1, DB3, 0, 8) +REG32(TXFIFO_DATA2, 0x3c) + FIELD(TXFIFO_DATA2, DB4, 24, 8) + FIELD(TXFIFO_DATA2, DB5, 16, 8) + FIELD(TXFIFO_DATA2, DB6, 8, 8) + FIELD(TXFIFO_DATA2, DB7, 0, 8) +REG32(TXHPB_ID, 0x40) + FIELD(TXHPB_ID, IDH, 21, 11) + FIELD(TXHPB_ID, SRRRTR, 20, 1) + FIELD(TXHPB_ID, IDE, 19, 1) + FIELD(TXHPB_ID, IDL, 1, 18) + FIELD(TXHPB_ID, RTR, 0, 1) +REG32(TXHPB_DLC, 0x44) + FIELD(TXHPB_DLC, DLC, 28, 4) +REG32(TXHPB_DATA1, 0x48) + FIELD(TXHPB_DATA1, DB0, 24, 8) + FIELD(TXHPB_DATA1, DB1, 16, 8) + FIELD(TXHPB_DATA1, DB2, 8, 8) + FIELD(TXHPB_DATA1, DB3, 0, 8) +REG32(TXHPB_DATA2, 0x4c) + FIELD(TXHPB_DATA2, DB4, 24, 8) + FIELD(TXHPB_DATA2, DB5, 16, 8) + FIELD(TXHPB_DATA2, DB6, 8, 8) + FIELD(TXHPB_DATA2, DB7, 0, 8) +REG32(RXFIFO_ID, 0x50) + FIELD(RXFIFO_ID, IDH, 21, 11) + FIELD(RXFIFO_ID, SRRRTR, 20, 1) + FIELD(RXFIFO_ID, IDE, 19, 1) + FIELD(RXFIFO_ID, IDL, 1, 18) + FIELD(RXFIFO_ID, RTR, 0, 1) +REG32(RXFIFO_DLC, 0x54) + FIELD(RXFIFO_DLC, DLC, 28, 4) + FIELD(RXFIFO_DLC, RXT, 0, 16) +REG32(RXFIFO_DATA1, 0x58) + FIELD(RXFIFO_DATA1, DB0, 24, 8) + FIELD(RXFIFO_DATA1, DB1, 16, 8) + FIELD(RXFIFO_DATA1, DB2, 8, 8) + FIELD(RXFIFO_DATA1, DB3, 0, 8) +REG32(RXFIFO_DATA2, 0x5c) + FIELD(RXFIFO_DATA2, DB4, 24, 8) + FIELD(RXFIFO_DATA2, DB5, 16, 8) + FIELD(RXFIFO_DATA2, DB6, 8, 8) + FIELD(RXFIFO_DATA2, DB7, 0, 8) +REG32(AFR, 0x60) + FIELD(AFR, UAF4, 3, 1) + FIELD(AFR, UAF3, 2, 1) + FIELD(AFR, UAF2, 1, 1) + FIELD(AFR, UAF1, 0, 1) +REG32(AFMR1, 0x64) + FIELD(AFMR1, AMIDH, 21, 11) + FIELD(AFMR1, AMSRR, 20, 1) + FIELD(AFMR1, AMIDE, 19, 1) + FIELD(AFMR1, AMIDL, 1, 18) + FIELD(AFMR1, AMRTR, 0, 1) +REG32(AFIR1, 0x68) + FIELD(AFIR1, AIIDH, 21, 11) + FIELD(AFIR1, AISRR, 20, 1) + FIELD(AFIR1, AIIDE, 19, 1) + FIELD(AFIR1, AIIDL, 1, 18) + FIELD(AFIR1, AIRTR, 0, 1) +REG32(AFMR2, 0x6c) + FIELD(AFMR2, AMIDH, 21, 11) + FIELD(AFMR2, AMSRR, 20, 1) + FIELD(AFMR2, AMIDE, 19, 1) + FIELD(AFMR2, AMIDL, 1, 18) + FIELD(AFMR2, AMRTR, 0, 1) +REG32(AFIR2, 0x70) + FIELD(AFIR2, AIIDH, 21, 11) + FIELD(AFIR2, AISRR, 20, 1) + FIELD(AFIR2, AIIDE, 19, 1) + FIELD(AFIR2, AIIDL, 1, 18) + FIELD(AFIR2, AIRTR, 0, 1) +REG32(AFMR3, 0x74) + FIELD(AFMR3, AMIDH, 21, 11) + FIELD(AFMR3, AMSRR, 20, 1) + FIELD(AFMR3, AMIDE, 19, 1) + FIELD(AFMR3, AMIDL, 1, 18) + FIELD(AFMR3, AMRTR, 0, 1) +REG32(AFIR3, 0x78) + FIELD(AFIR3, AIIDH, 21, 11) + FIELD(AFIR3, AISRR, 20, 1) + FIELD(AFIR3, AIIDE, 19, 1) + FIELD(AFIR3, AIIDL, 1, 18) + FIELD(AFIR3, AIRTR, 0, 1) +REG32(AFMR4, 0x7c) + FIELD(AFMR4, AMIDH, 21, 11) + FIELD(AFMR4, AMSRR, 20, 1) + FIELD(AFMR4, AMIDE, 19, 1) + FIELD(AFMR4, AMIDL, 1, 18) + FIELD(AFMR4, AMRTR, 0, 1) +REG32(AFIR4, 0x80) + FIELD(AFIR4, AIIDH, 21, 11) + FIELD(AFIR4, AISRR, 20, 1) + FIELD(AFIR4, AIIDE, 19, 1) + FIELD(AFIR4, AIIDL, 1, 18) + FIELD(AFIR4, AIRTR, 0, 1) + +static void can_update_irq(XlnxZynqMPCANState *s) +{ + uint32_t irq; + + /* Watermark register interrupts. */ + if ((fifo32_num_free(&s->tx_fifo) / CAN_FRAME_SIZE) > + ARRAY_FIELD_EX32(s->regs, WIR, EW)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFWMEMP, 1); + } + + if ((fifo32_num_used(&s->rx_fifo) / CAN_FRAME_SIZE) > + ARRAY_FIELD_EX32(s->regs, WIR, FW)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXFWMFLL, 1); + } + + /* RX Interrupts. */ + if (fifo32_num_used(&s->rx_fifo) >=3D CAN_FRAME_SIZE) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXNEMP, 1); + } + + /* TX interrupts. */ + if (fifo32_is_empty(&s->tx_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFEMP, 1); + } + + if (fifo32_is_full(&s->tx_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXFLL, 1); + } + + if (fifo32_is_full(&s->txhpb_fifo)) { + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXBFLL, 1); + } + + irq =3D s->regs[R_INTERRUPT_STATUS_REGISTER]; + irq &=3D s->regs[R_INTERRUPT_ENABLE_REGISTER]; + + qemu_set_irq(s->irq, irq); +} + +static void can_ier_post_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + can_update_irq(s); +} + +static uint64_t can_icr_pre_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_INTERRUPT_STATUS_REGISTER] &=3D ~val; + can_update_irq(s); + + return 0; +} + +static void can_config_reset(XlnxZynqMPCANState *s) +{ + /* Reset all the configuration registers. */ + register_reset(&s->reg_info[R_SOFTWARE_RESET_REGISTER]); + register_reset(&s->reg_info[R_MODE_SELECT_REGISTER]); + register_reset( + &s->reg_info[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTE= R]); + register_reset(&s->reg_info[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]); + register_reset(&s->reg_info[R_STATUS_REGISTER]); + register_reset(&s->reg_info[R_INTERRUPT_STATUS_REGISTER]); + register_reset(&s->reg_info[R_INTERRUPT_ENABLE_REGISTER]); + register_reset(&s->reg_info[R_INTERRUPT_CLEAR_REGISTER]); + register_reset(&s->reg_info[R_WIR]); +} + +static void can_config_mode(XlnxZynqMPCANState *s) +{ + register_reset(&s->reg_info[R_ERROR_COUNTER_REGISTER]); + register_reset(&s->reg_info[R_ERROR_STATUS_REGISTER]); + + /* Put XlnxZynqMPCAN in configuration mode. */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 1); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, BSOFF, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ERROR, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 0); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, ARBLST, 0); + + can_update_irq(s); +} + +static void update_status_register_mode_bits(XlnxZynqMPCANState *s) +{ + bool sleep_status =3D ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP= ); + bool sleep_mode =3D ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SL= EEP); + /* Wake up interrupt bit. */ + bool wakeup_irq_val =3D sleep_status && (sleep_mode =3D=3D 0); + /* Sleep interrupt bit. */ + bool sleep_irq_val =3D sleep_mode && (sleep_status =3D=3D 0); + + /* Clear previous core mode status bits. */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 0); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 0); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 0); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 0); + + /* set current mode bit and generate irqs accordingly. */ + if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, LBACK)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, LBACK, 1); + } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SLEEP)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SLEEP, 1); + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, SLP, + sleep_irq_val); + } else if (ARRAY_FIELD_EX32(s->regs, MODE_SELECT_REGISTER, SNOOP)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, SNOOP, 1); + } else { + /* + * If all bits are zero then XlnxZynqMPCAN is set in normal mode. + */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, NORMAL, 1); + /* Set wakeup interrupt bit. */ + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, WKUP, + wakeup_irq_val); + } + + can_update_irq(s); +} + +static void can_exit_sleep_mode(XlnxZynqMPCANState *s) +{ + ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, 0); + update_status_register_mode_bits(s); +} + +static void generate_frame(qemu_can_frame *frame, uint32_t *data) +{ + frame->can_id =3D data[0]; + frame->can_dlc =3D FIELD_EX32(data[1], TXFIFO_DLC, DLC); + + frame->data[0] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB3); + frame->data[1] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB2); + frame->data[2] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB1); + frame->data[3] =3D FIELD_EX32(data[2], TXFIFO_DATA1, DB0); + + frame->data[4] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB7); + frame->data[5] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB6); + frame->data[6] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB5); + frame->data[7] =3D FIELD_EX32(data[3], TXFIFO_DATA2, DB4); +} + +static bool tx_ready_check(XlnxZynqMPCANState *s) +{ + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer data wh= ile" + " data while controller is in reset mode.\n", + path); + return false; + } + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) =3D=3D 0) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer" + " data while controller is in configuration mode. Re= set" + " the core so operations can start fresh.\n", + path); + return false; + } + + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to transfer" + " data while controller is in SNOOP MODE.\n", + path); + return false; + } + + return true; +} + +static void transfer_fifo(XlnxZynqMPCANState *s, Fifo32 *fifo) +{ + qemu_can_frame frame; + uint32_t data[CAN_FRAME_SIZE]; + int i; + bool can_tx =3D tx_ready_check(s); + + if (can_tx) { + while (!fifo32_is_empty(fifo)) { + for (i =3D 0; i < CAN_FRAME_SIZE; i++) { + data[i] =3D fifo32_pop(fifo); + } + + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { + /* + * Controller is in loopback. In Loopback mode, the CAN co= re + * transmits a recessive bitstream on to the XlnxZynqMPCAN= Bus. + * Any message transmitted is looped back to the RX line a= nd + * acknowledged. The XlnxZynqMPCAN core receives any messa= ge + * that it transmits. + */ + if (fifo32_is_full(&s->rx_fifo)) { + DB_PRINT(s, "Loopback: RX FIFO is full." + " TX FIFO will be flushed.\n"); + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, + RXOFLW, 1); + } else { + for (i =3D 0; i < CAN_FRAME_SIZE; i++) { + fifo32_push(&s->rx_fifo, data[i]); + } + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, + RXOK, 1); + } + } else { + /* Normal mode Tx. */ + generate_frame(&frame, data); + + can_bus_client_send(&s->bus_client, &frame, 1); + } + } + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, TXOK, 1); + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, TXBFLL, 0); + + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) { + can_exit_sleep_mode(s); + } + } else { + DB_PRINT(s, "Not enabled for data transfer.\n"); + } + + can_update_irq(s); +} + +static uint64_t can_srr_pre_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t val =3D val64; + + ARRAY_FIELD_DP32(s->regs, SOFTWARE_RESET_REGISTER, CEN, + FIELD_EX32(val, SOFTWARE_RESET_REGISTER, CEN)); + + if (FIELD_EX32(val, SOFTWARE_RESET_REGISTER, SRST)) { + DB_PRINT(s, "Resetting controller.\n"); + + /* First, core will do software reset then will enter in config mo= de. */ + can_config_reset(s); + } + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) =3D=3D 0) { + can_config_mode(s); + } else { + /* + * Leave config mode. Now XlnxZynqMPCAN core will enter normal, + * sleep, snoop or loopback mode depending upon LBACK, SLEEP, SNOOP + * register states. + */ + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, CONFIG, 0); + + ptimer_transaction_begin(s->can_timer); + ptimer_set_count(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); + + /* XlnxZynqMPCAN is out of config mode. It will send pending data.= */ + transfer_fifo(s, &s->txhpb_fifo); + transfer_fifo(s, &s->tx_fifo); + } + + update_status_register_mode_bits(s); + + return s->regs[R_SOFTWARE_RESET_REGISTER]; +} + +static uint64_t can_msr_pre_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t val =3D val64; + uint8_t multi_mode; + + /* + * Multiple mode set check. This is done to make sure user doesn't set + * multiple modes. + */ + multi_mode =3D FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK) + + FIELD_EX32(val, MODE_SELECT_REGISTER, SLEEP) + + FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP); + + if (multi_mode > 1) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to config" + " several modes simultaneously. One mode will be sel= ected" + " according to their priority: LBACK > SLEEP > SNOOP= .\n", + path); + } + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN) =3D=3D 0) { + /* We are in configuration mode, any mode can be selected. */ + s->regs[R_MODE_SELECT_REGISTER] =3D val; + } else { + bool sleep_mode_bit =3D FIELD_EX32(val, MODE_SELECT_REGISTER, SLEE= P); + + ARRAY_FIELD_DP32(s->regs, MODE_SELECT_REGISTER, SLEEP, sleep_mode_= bit); + + if (FIELD_EX32(val, MODE_SELECT_REGISTER, LBACK)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set" + " LBACK mode without setting CEN bit as 0.\n", + path); + } else if (FIELD_EX32(val, MODE_SELECT_REGISTER, SNOOP)) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Attempting to set" + " SNOOP mode without setting CEN bit as 0.\n", + path); + } + + update_status_register_mode_bits(s); + } + + return s->regs[R_MODE_SELECT_REGISTER]; +} + +static uint64_t can_brpr_pre_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t val =3D val64; + + /* Only allow writes when in config mode. */ + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { + val =3D s->regs[R_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER]; + } + + return val; +} + +static uint64_t can_btr_pre_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t val =3D val64; + + /* Only allow writes when in config mode. */ + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { + val =3D s->regs[R_ARBITRATION_PHASE_BIT_TIMING_REGISTER]; + } + + return val; +} + +static uint64_t can_tcr_pre_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t val =3D val64; + + if (FIELD_EX32(val, TIMESTAMP_REGISTER, CTS)) { + ptimer_transaction_begin(s->can_timer); + ptimer_set_count(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); + } + + return 0; +} + +static void update_rx_fifo(XlnxZynqMPCANState *s, const qemu_can_frame *fr= ame) +{ + bool filter_pass =3D false; + uint16_t timestamp =3D 0; + + /* If no filter is enabled. Message will be stored in FIFO. */ + if (!((ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) | + (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)))) { + filter_pass =3D true; + } + + /* + * Messages that pass any of the acceptance filters will be stored in + * the RX FIFO. + */ + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1)) { + uint32_t id_masked =3D s->regs[R_AFMR1] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR1] & s->regs[R_AFIR1]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF2)) { + uint32_t id_masked =3D s->regs[R_AFMR2] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR2] & s->regs[R_AFIR2]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF3)) { + uint32_t id_masked =3D s->regs[R_AFMR3] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR3] & s->regs[R_AFIR3]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { + uint32_t id_masked =3D s->regs[R_AFMR4] & frame->can_id; + uint32_t filter_id_masked =3D s->regs[R_AFMR4] & s->regs[R_AFIR4]; + + if (filter_id_masked =3D=3D id_masked) { + filter_pass =3D true; + } + } + + /* Store the message in fifo if it passed through any of the filters. = */ + if (filter_pass && frame->can_dlc <=3D MAX_DLC) { + + if (fifo32_is_full(&s->rx_fifo)) { + DB_PRINT(s, "RX FIFO is full.\n"); + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOFLW, 1= ); + } else { + timestamp =3D CAN_TIMER_MAX - ptimer_get_count(s->can_timer); + + fifo32_push(&s->rx_fifo, frame->can_id); + + fifo32_push(&s->rx_fifo, deposit32(0, R_RXFIFO_DLC_DLC_SHIFT, + R_RXFIFO_DLC_DLC_LENGTH, + frame->can_dlc) | + deposit32(0, R_RXFIFO_DLC_RXT_SHIFT, + R_RXFIFO_DLC_RXT_LENGTH, + timestamp)); + + /* First 32 bit of the data. */ + fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA1_DB3_SHIFT, + R_TXFIFO_DATA1_DB3_LENGTH, + frame->data[0]) | + deposit32(0, R_TXFIFO_DATA1_DB2_SHIFT, + R_TXFIFO_DATA1_DB2_LENGTH, + frame->data[1]) | + deposit32(0, R_TXFIFO_DATA1_DB1_SHIFT, + R_TXFIFO_DATA1_DB1_LENGTH, + frame->data[2]) | + deposit32(0, R_TXFIFO_DATA1_DB0_SHIFT, + R_TXFIFO_DATA1_DB0_LENGTH, + frame->data[3])); + /* Last 32 bit of the data. */ + fifo32_push(&s->rx_fifo, deposit32(0, R_TXFIFO_DATA2_DB7_SHIFT, + R_TXFIFO_DATA2_DB7_LENGTH, + frame->data[4]) | + deposit32(0, R_TXFIFO_DATA2_DB6_SHIFT, + R_TXFIFO_DATA2_DB6_LENGTH, + frame->data[5]) | + deposit32(0, R_TXFIFO_DATA2_DB5_SHIFT, + R_TXFIFO_DATA2_DB5_LENGTH, + frame->data[6]) | + deposit32(0, R_TXFIFO_DATA2_DB4_SHIFT, + R_TXFIFO_DATA2_DB4_LENGTH, + frame->data[7])); + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXOK, 1); + } + + can_update_irq(s); + } else { + DB_PRINT(s, "Message didn't pass through any filter or dlc" + " is not in range.\n"); + } +} + +static uint64_t can_rxfifo_pre_read(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t r =3D 0; + + if (!fifo32_is_empty(&s->rx_fifo)) { + r =3D fifo32_pop(&s->rx_fifo); + } else { + DB_PRINT(s, "No message in RXFIFO.\n"); + + ARRAY_FIELD_DP32(s->regs, INTERRUPT_STATUS_REGISTER, RXUFLW, 1); + } + + can_update_irq(s); + return r; +} + +static void can_filter_enable_post_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + + if (ARRAY_FIELD_EX32(s->regs, AFR, UAF1) && + ARRAY_FIELD_EX32(s->regs, AFR, UAF2) && + ARRAY_FIELD_EX32(s->regs, AFR, UAF3) && + ARRAY_FIELD_EX32(s->regs, AFR, UAF4)) { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 1); + } else { + ARRAY_FIELD_DP32(s->regs, STATUS_REGISTER, ACFBSY, 0); + } +} + +static uint64_t can_filter_mask_pre_write(RegisterInfo *reg, uint64_t val6= 4) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t reg_idx =3D (reg->access->addr) / 4; + uint32_t val =3D val64; + uint32_t filter_number =3D (reg_idx - R_AFMR1) / 2; + + /* modify an acceptance filter, the corresponding UAF bit should be '0= .' */ + if (!(s->regs[R_AFR] & (1 << filter_number))) { + s->regs[reg_idx] =3D val; + } else { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d" + " mask is not set as corresponding UAF bit is not 0.= \n", + path, filter_number + 1); + } + + return s->regs[reg_idx]; +} + +static uint64_t can_filter_id_pre_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t reg_idx =3D (reg->access->addr) / 4; + uint32_t val =3D val64; + uint32_t filter_number =3D (reg_idx - R_AFIR1) / 2; + + if (!(s->regs[R_AFR] & (1 << filter_number))) { + s->regs[reg_idx] =3D val; + } else { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: Acceptance filter %d" + " id is not set as corresponding UAF bit is not 0.\n= ", + path, filter_number + 1); + } + + return s->regs[reg_idx]; +} + +static void can_tx_post_write(RegisterInfo *reg, uint64_t val64) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(reg->opaque); + uint32_t val =3D val64; + + bool is_txhpb =3D reg->access->addr > A_TXFIFO_DATA2; + + bool initiate_transfer =3D (reg->access->addr =3D=3D A_TXFIFO_DATA2) || + (reg->access->addr =3D=3D A_TXHPB_DATA2); + + Fifo32 *f =3D is_txhpb ? &s->txhpb_fifo : &s->tx_fifo; + + DB_PRINT(s, "TX FIFO write.\n"); + + if (!fifo32_is_full(f)) { + fifo32_push(f, val); + } else { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + qemu_log_mask(LOG_GUEST_ERROR, "%s: TX FIFO is full.\n", path); + } + + /* Initiate the message send if TX register is written. */ + if (initiate_transfer && + ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) { + transfer_fifo(s, f); + } + + can_update_irq(s); +} + +static const RegisterAccessInfo can_regs_info[] =3D { + { .name =3D "SOFTWARE_RESET_REGISTER", + .addr =3D A_SOFTWARE_RESET_REGISTER, + .rsvd =3D 0xfffffffc, + .pre_write =3D can_srr_pre_write, + },{ .name =3D "MODE_SELECT_REGISTER", + .addr =3D A_MODE_SELECT_REGISTER, + .rsvd =3D 0xfffffff8, + .pre_write =3D can_msr_pre_write, + },{ .name =3D "ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER", + .addr =3D A_ARBITRATION_PHASE_BAUD_RATE_PRESCALER_REGISTER, + .rsvd =3D 0xffffff00, + .pre_write =3D can_brpr_pre_write, + },{ .name =3D "ARBITRATION_PHASE_BIT_TIMING_REGISTER", + .addr =3D A_ARBITRATION_PHASE_BIT_TIMING_REGISTER, + .rsvd =3D 0xfffffe00, + .pre_write =3D can_btr_pre_write, + },{ .name =3D "ERROR_COUNTER_REGISTER", + .addr =3D A_ERROR_COUNTER_REGISTER, + .rsvd =3D 0xffff0000, + .ro =3D 0xffffffff, + },{ .name =3D "ERROR_STATUS_REGISTER", + .addr =3D A_ERROR_STATUS_REGISTER, + .rsvd =3D 0xffffffe0, + .w1c =3D 0x1f, + },{ .name =3D "STATUS_REGISTER", .addr =3D A_STATUS_REGISTER, + .reset =3D 0x1, + .rsvd =3D 0xffffe000, + .ro =3D 0x1fff, + },{ .name =3D "INTERRUPT_STATUS_REGISTER", + .addr =3D A_INTERRUPT_STATUS_REGISTER, + .reset =3D 0x6000, + .rsvd =3D 0xffff8000, + .ro =3D 0x7fff, + },{ .name =3D "INTERRUPT_ENABLE_REGISTER", + .addr =3D A_INTERRUPT_ENABLE_REGISTER, + .rsvd =3D 0xffff8000, + .post_write =3D can_ier_post_write, + },{ .name =3D "INTERRUPT_CLEAR_REGISTER", + .addr =3D A_INTERRUPT_CLEAR_REGISTER, + .rsvd =3D 0xffff8000, + .pre_write =3D can_icr_pre_write, + },{ .name =3D "TIMESTAMP_REGISTER", + .addr =3D A_TIMESTAMP_REGISTER, + .rsvd =3D 0xfffffffe, + .pre_write =3D can_tcr_pre_write, + },{ .name =3D "WIR", .addr =3D A_WIR, + .reset =3D 0x3f3f, + .rsvd =3D 0xffff0000, + },{ .name =3D "TXFIFO_ID", .addr =3D A_TXFIFO_ID, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXFIFO_DLC", .addr =3D A_TXFIFO_DLC, + .rsvd =3D 0xfffffff, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXFIFO_DATA1", .addr =3D A_TXFIFO_DATA1, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXFIFO_DATA2", .addr =3D A_TXFIFO_DATA2, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_ID", .addr =3D A_TXHPB_ID, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_DLC", .addr =3D A_TXHPB_DLC, + .rsvd =3D 0xfffffff, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_DATA1", .addr =3D A_TXHPB_DATA1, + .post_write =3D can_tx_post_write, + },{ .name =3D "TXHPB_DATA2", .addr =3D A_TXHPB_DATA2, + .post_write =3D can_tx_post_write, + },{ .name =3D "RXFIFO_ID", .addr =3D A_RXFIFO_ID, + .ro =3D 0xffffffff, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "RXFIFO_DLC", .addr =3D A_RXFIFO_DLC, + .rsvd =3D 0xfff0000, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "RXFIFO_DATA1", .addr =3D A_RXFIFO_DATA1, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "RXFIFO_DATA2", .addr =3D A_RXFIFO_DATA2, + .post_read =3D can_rxfifo_pre_read, + },{ .name =3D "AFR", .addr =3D A_AFR, + .rsvd =3D 0xfffffff0, + .post_write =3D can_filter_enable_post_write, + },{ .name =3D "AFMR1", .addr =3D A_AFMR1, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR1", .addr =3D A_AFIR1, + .pre_write =3D can_filter_id_pre_write, + },{ .name =3D "AFMR2", .addr =3D A_AFMR2, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR2", .addr =3D A_AFIR2, + .pre_write =3D can_filter_id_pre_write, + },{ .name =3D "AFMR3", .addr =3D A_AFMR3, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR3", .addr =3D A_AFIR3, + .pre_write =3D can_filter_id_pre_write, + },{ .name =3D "AFMR4", .addr =3D A_AFMR4, + .pre_write =3D can_filter_mask_pre_write, + },{ .name =3D "AFIR4", .addr =3D A_AFIR4, + .pre_write =3D can_filter_id_pre_write, + } +}; + +static void xlnx_zynqmp_can_ptimer_cb(void *opaque) +{ + /* No action required on the timer rollover. */ +} + +static const MemoryRegionOps can_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void xlnx_zynqmp_can_reset_init(Object *obj, ResetType type) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(obj); + unsigned int i; + + for (i =3D R_RXFIFO_ID; i < ARRAY_SIZE(s->reg_info); ++i) { + register_reset(&s->reg_info[i]); + } + + ptimer_transaction_begin(s->can_timer); + ptimer_set_count(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); +} + +static void xlnx_zynqmp_can_reset_hold(Object *obj) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(obj); + unsigned int i; + + for (i =3D 0; i < R_RXFIFO_ID; ++i) { + register_reset(&s->reg_info[i]); + } + + /* + * Reset FIFOs when CAN model is reset. This will clear the fifo writes + * done by post_write which gets called from register_reset function, + * post_write handle will not be able to trigger tx because CAN will be + * disabled when software_reset_register is cleared first. + */ + fifo32_reset(&s->rx_fifo); + fifo32_reset(&s->tx_fifo); + fifo32_reset(&s->txhpb_fifo); +} + +static bool xlnx_zynqmp_can_can_receive(CanBusClientState *client) +{ + XlnxZynqMPCANState *s =3D container_of(client, XlnxZynqMPCANState, + bus_client); + + if (ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, SRST)) { + DB_PRINT(s, "Controller is in reset.\n"); + return false; + } else if ((ARRAY_FIELD_EX32(s->regs, SOFTWARE_RESET_REGISTER, CEN)) = =3D=3D 0) { + DB_PRINT(s, "Controller is disabled. Incoming messages" + " will be discarded.\n"); + return false; + } else { + return true; + } +} + +static ssize_t xlnx_zynqmp_can_receive(CanBusClientState *client, + const qemu_can_frame *buf, size_t buf_size)= { + XlnxZynqMPCANState *s =3D container_of(client, XlnxZynqMPCANState, + bus_client); + const qemu_can_frame *frame =3D buf; + + DB_PRINT(s, "Incoming data.\n"); + + if (buf_size <=3D 0) { + DB_PRINT(s, "Junk data received.\n"); + return 0; + } + if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, LBACK)) { + /* + * XlnxZynqMPCAN will not participate in normal bus communication + * and will not receive any messages transmitted by other CAN node= s. + */ + DB_PRINT(s, "Controller is in loopback mode. It will not" + " receive data.\n"); + + } else if (ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SNOOP)) { + /* Snoop Mode: Just keep the data. no response back. */ + update_rx_fifo(s, frame); + } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP))) { + /* + * XlnxZynqMPCAN is in sleep mode. Any data on bus will bring it t= o wake + * up state. + */ + can_exit_sleep_mode(s); + update_rx_fifo(s, frame); + } else if ((ARRAY_FIELD_EX32(s->regs, STATUS_REGISTER, SLEEP)) =3D=3D = 0) { + update_rx_fifo(s, frame); + } else { + DB_PRINT(s, "Cannot receive data as controller is not configured" + " correctly.\n"); + } + + return 1; +} + +static CanBusClientInfo can_xilinx_bus_client_info =3D { + .can_receive =3D xlnx_zynqmp_can_can_receive, + .receive =3D xlnx_zynqmp_can_receive, +}; + +static int xlnx_zynqmp_can_connect_to_bus(XlnxZynqMPCANState *s, + CanBusState *bus) +{ + s->bus_client.info =3D &can_xilinx_bus_client_info; + + if (can_bus_insert_client(bus, &s->bus_client) < 0) { + return -1; + } + return 0; +} + +static void xlnx_zynqmp_can_realize(DeviceState *dev, Error **errp) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(dev); + + if (s->canbus) { + if (xlnx_zynqmp_can_connect_to_bus(s, s->canbus) < 0) { + g_autofree char *path =3D object_get_canonical_path(OBJECT(s)); + + error_setg(errp, "%s: xlnx_zynqmp_can_connect_to_bus" + " failed.", path); + return; + } + + } else { + /* If no bus is set. */ + DB_PRINT(s, "Canbus property is not set.\n"); + } + + /* Create RX FIFO, TXFIFO, TXHPB storage. */ + fifo32_create(&s->rx_fifo, RXFIFO_SIZE); + fifo32_create(&s->tx_fifo, RXFIFO_SIZE); + fifo32_create(&s->txhpb_fifo, CAN_FRAME_SIZE); + + /* Allocate a new timer. */ + s->can_timer =3D ptimer_init(xlnx_zynqmp_can_ptimer_cb, s, + PTIMER_POLICY_DEFAULT); + + ptimer_transaction_begin(s->can_timer); + + ptimer_set_freq(s->can_timer, s->cfg.ext_clk_freq); + ptimer_set_limit(s->can_timer, CAN_TIMER_MAX, 1); + ptimer_run(s->can_timer, 0); + ptimer_transaction_commit(s->can_timer); +} + +static void xlnx_zynqmp_can_init(Object *obj) +{ + XlnxZynqMPCANState *s =3D XLNX_ZYNQMP_CAN(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + + RegisterInfoArray *reg_array; + + memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_CAN, + XLNX_ZYNQMP_CAN_R_MAX * 4); + reg_array =3D register_init_block32(DEVICE(obj), can_regs_info, + ARRAY_SIZE(can_regs_info), + s->reg_info, s->regs, + &can_ops, + XLNX_ZYNQMP_CAN_ERR_DEBUG, + XLNX_ZYNQMP_CAN_R_MAX * 4); + + memory_region_add_subregion(&s->iomem, 0x00, ®_array->mem); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); +} + +static const VMStateDescription vmstate_can =3D { + .name =3D TYPE_XLNX_ZYNQMP_CAN, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_FIFO32(rx_fifo, XlnxZynqMPCANState), + VMSTATE_FIFO32(tx_fifo, XlnxZynqMPCANState), + VMSTATE_FIFO32(txhpb_fifo, XlnxZynqMPCANState), + VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPCANState, XLNX_ZYNQMP_CAN_R_M= AX), + VMSTATE_PTIMER(can_timer, XlnxZynqMPCANState), + VMSTATE_END_OF_LIST(), + } +}; + +static Property xlnx_zynqmp_can_properties[] =3D { + DEFINE_PROP_UINT32("ext_clk_freq", XlnxZynqMPCANState, cfg.ext_clk_fre= q, + CAN_DEFAULT_CLOCK), + DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS, + CanBusState *), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + + rc->phases.enter =3D xlnx_zynqmp_can_reset_init; + rc->phases.hold =3D xlnx_zynqmp_can_reset_hold; + dc->realize =3D xlnx_zynqmp_can_realize; + device_class_set_props(dc, xlnx_zynqmp_can_properties); + dc->vmsd =3D &vmstate_can; +} + +static const TypeInfo can_info =3D { + .name =3D TYPE_XLNX_ZYNQMP_CAN, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxZynqMPCANState), + .class_init =3D xlnx_zynqmp_can_class_init, + .instance_init =3D xlnx_zynqmp_can_init, +}; + +static void can_register_types(void) +{ + type_register_static(&can_info); +} + +type_init(can_register_types) diff --git a/include/hw/net/xlnx-zynqmp-can.h b/include/hw/net/xlnx-zynqmp-= can.h new file mode 100644 index 0000000..eb15587 --- /dev/null +++ b/include/hw/net/xlnx-zynqmp-can.h @@ -0,0 +1,78 @@ +/* + * QEMU model of the Xilinx ZynqMP CAN controller. + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written-by: Vikram Garhwal + * + * Based on QEMU CAN Device emulation implemented by Jin Yang, Deniz Eren = and + * Pavel Pisa. + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef XLNX_ZYNQMP_CAN_H +#define XLNX_ZYNQMP_CAN_H + +#include "hw/register.h" +#include "net/can_emu.h" +#include "net/can_host.h" +#include "qemu/fifo32.h" +#include "hw/ptimer.h" +#include "hw/qdev-clock.h" + +#define TYPE_XLNX_ZYNQMP_CAN "xlnx.zynqmp-can" + +#define XLNX_ZYNQMP_CAN(obj) \ + OBJECT_CHECK(XlnxZynqMPCANState, (obj), TYPE_XLNX_ZYNQMP_CAN) + +#define MAX_CAN_CTRLS 2 +#define XLNX_ZYNQMP_CAN_R_MAX (0x84 / 4) +#define MAILBOX_CAPACITY 64 +#define CAN_TIMER_MAX 0XFFFFUL +#define CAN_DEFAULT_CLOCK (24 * 1000 * 1000) + +/* Each CAN_FRAME will have 4 * 32bit size. */ +#define CAN_FRAME_SIZE 4 +#define RXFIFO_SIZE (MAILBOX_CAPACITY * CAN_FRAME_SIZE) + +typedef struct XlnxZynqMPCANState { + SysBusDevice parent_obj; + MemoryRegion iomem; + + qemu_irq irq; + + CanBusClientState bus_client; + CanBusState *canbus; + + struct { + uint32_t ext_clk_freq; + } cfg; + + RegisterInfo reg_info[XLNX_ZYNQMP_CAN_R_MAX]; + uint32_t regs[XLNX_ZYNQMP_CAN_R_MAX]; + + Fifo32 rx_fifo; + Fifo32 tx_fifo; + Fifo32 txhpb_fifo; + + ptimer_state *can_timer; +} XlnxZynqMPCANState; + +#endif --=20 2.7.4 From nobody Sun May 19 02:38:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1600121468; cv=pass; d=zohomail.com; s=zohoarc; b=b94CU/7ap99HkBEzlhNgMpzWoIv3VN1mMDbjdIhTXLg4gnXWPGy7DJdql4SNb00xS42a/cN7F4YXZy3bQA/4xi/rh7e5j2alxDyPhBOV8G0+/krDOmjiKBKltQKSaWZGBDDHfnslf56w6YPCvfLdEfYP7Qr/cd7SAY3clGrnhKg= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600121468; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R5o2BH4H16hNvgbWdLBjKXwDZeYei+QOB7tl1xYlzy4=; b=G25QVE1AWJ5yoqcj1lqIt/LJwSXCgMbzW4LI5QujpTjp+fjruGTC5WlR2ADIMjhafwNkipKEz9c7JBNvPlUZpcFN1rtOlBZLInVDBqHFZ6feX5B2Z9S8auCXx13rCnl9xhC0OEZzpGCD/USGIxaVyrTD/t9Ua8jM+BHiBqdP0Ak= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1600121468836582.5910123894354; Mon, 14 Sep 2020 15:11:08 -0700 (PDT) Received: from localhost ([::1]:37864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kHwgl-0003GO-JL for importer@patchew.org; Mon, 14 Sep 2020 18:11:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwfC-00020w-AW; Mon, 14 Sep 2020 18:09:30 -0400 Received: from mail-dm6nam10on2075.outbound.protection.outlook.com ([40.107.93.75]:40096 helo=NAM10-DM6-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwf8-0000b3-20; Mon, 14 Sep 2020 18:09:30 -0400 Received: from CY4PR02CA0019.namprd02.prod.outlook.com (2603:10b6:903:18::29) by SN6PR02MB5390.namprd02.prod.outlook.com (2603:10b6:805:ea::31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16; Mon, 14 Sep 2020 22:09:17 +0000 Received: from CY1NAM02FT016.eop-nam02.prod.protection.outlook.com (2603:10b6:903:18:cafe::e9) by CY4PR02CA0019.outlook.office365.com (2603:10b6:903:18::29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:17 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT016.mail.protection.outlook.com (10.152.75.164) with Microsoft SMTP Server id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:17 +0000 Received: from [149.199.38.66] (port=48267 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1kHweu-0003rb-6N; Mon, 14 Sep 2020 15:09:12 -0700 Received: from [127.0.0.1] (helo=localhost) by smtp.xilinx.com with smtp (Exim 4.63) (envelope-from ) id 1kHwey-0006ms-VH; Mon, 14 Sep 2020 15:09:17 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp1.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 08EM979H016761; Mon, 14 Sep 2020 15:09:07 -0700 Received: from [172.19.2.115] (helo=xsjfnuv50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kHwep-0006b8-4c; Mon, 14 Sep 2020 15:09:07 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=JR3yU5F8Pe9vThgMzwoZYOBz1PfPhPyNszhu+CIZgwNcwvpJkLCPnd7as9I9Enh1wuR3DXZe9zqMyGJq5+8bVyYSQokSZ+qoqt6m4RrzOzHRX3JT93v59RKF0u1ORHmhA651CxFjg7XcLgBK49HwQiCwqrqokacRQV9ArJcjD+TcCF17LMsFaslBtaBmIz/+b/q9zmDSgwXeqYo2AJr77YqrxwQ21VpQRtXRlGe6Wb/+zrUYC+GcvTqZrWEiRtOxF6vbY++bByqvgK/Lw4uJIJXGCEu8saF+Dymp3+GvXZaoGoB+t2u5lojmjBQf+Py+9HK3QfK7D4v1TMs+r3j1xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R5o2BH4H16hNvgbWdLBjKXwDZeYei+QOB7tl1xYlzy4=; b=Mwd8qeIvU4ao1SfF+aGlEVD6jcTJKGMsYTtmu+8Why/ag7CEMIel4GI5+4pYzJXeguXrgJMXgkbIluTCrVZFgj3heqWMTdCCBlOhkmmx9Y+dYSX10jJ3lCQsmGRfCvx+9TPg6kZ8t5HCXdOYdiihR4K94NOUmPR5x8G1iN1XhArEu7fgnGIZxpblyt0ef6VpXlPalXY3kgI3FIFYZZG2sB3Dadp9VCgP0CyQOwmrWFH8OtiLMjBR8Hkn2U/Pu1gkwxMrIZKY2i9uCFBQU7RkPJ7SlUtrZPCPaogUMdeEWn7BO6/UgBzE8YDIFdum7VV+vS01V/cNbwSEx1pa8JRtag== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=nongnu.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=R5o2BH4H16hNvgbWdLBjKXwDZeYei+QOB7tl1xYlzy4=; b=XXqX8K91xtNhJznXx84CKjRsGGVVzJ53G5o1CWJZUfPV8UESpGdNmnvDk/UccDPWppioth62JatIKVhkJVmRLRdsgNdhoP0J0fxEOKFkAG3W1CvHP67q7a6oRpnOGCmgPi5xwebDVG8CiyzvppCRyNznWbMV1SrPpteCrtlA1bs= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; nongnu.org; dkim=none (message not signed) header.d=none;nongnu.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; From: Vikram Garhwal To: qemu-devel@nongnu.org Subject: [PATCH v10 2/4] xlnx-zynqmp: Connect Xilinx ZynqMP CAN controllers Date: Mon, 14 Sep 2020 15:08:42 -0700 Message-Id: <1600121324-31337-3-git-send-email-fnu.vikram@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> References: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: a0310f8f-f962-4d9d-bcbc-08d858fad2a7 X-MS-TrafficTypeDiagnostic: SN6PR02MB5390: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:114; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4VWOAt5lu1j6LGMRegsRRPvDlYJ/WYCzhwm405fy64nG9YUYpKSk3t7qIwEbJyt78BE9KRo+zeoSy8VrFmH6blbm3r8HYDUWLcfZgagRuVNL9aDyWpNOfbHZOVVTZ5xyqI+rgF1eCQKqn19/hmQsLFJu3XGIxauIph7is3Xg5RnRzrk0zLYTuQATc518tRU4kGmqtydaWNCF3BYsxzaZLPU2M0pAF44thCmxouOnPB3QB0kc1tv/zFN2P95ZIovLg2ppqeZ/zBizbsl+OeGW3silLZcgnhHSfIu2MZA7IAQnssyNeWkDVJfSTAeM4WoAacUtamHp4yjRBTWAFiF3PZld9m4yV/lt97oysWW/97L190LsZQ2j8rsjJ2kEoxq6DUKszuVL01vkU4DEy8ut0Q== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(396003)(376002)(39860400002)(136003)(346002)(46966005)(2616005)(8936002)(4326008)(316002)(6666004)(478600001)(54906003)(70586007)(82310400003)(70206006)(6916009)(356005)(36756003)(9786002)(47076004)(186003)(8676002)(26005)(81166007)(336012)(7696005)(82740400003)(5660300002)(426003)(2906002); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2020 22:09:17.2141 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0310f8f-f962-4d9d-bcbc-08d858fad2a7 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT016.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN6PR02MB5390 Received-SPF: pass client-ip=40.107.93.75; envelope-from=fnuv@xilinx.com; helo=NAM10-DM6-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/14 18:09:24 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Vikram Garhwal , Alistair Francis , francisco.iglesias@xilinx.com, "open list:Xilinx ZynqMP and..." , "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Connect CAN0 and CAN1 on the ZynqMP. Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Vikram Garhwal --- hw/arm/xlnx-zcu102.c | 20 ++++++++++++++++++++ hw/arm/xlnx-zynqmp.c | 34 ++++++++++++++++++++++++++++++++++ include/hw/arm/xlnx-zynqmp.h | 8 ++++++++ 3 files changed, 62 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 19d5a4d..cb0fba7 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -25,6 +25,7 @@ #include "sysemu/qtest.h" #include "sysemu/device_tree.h" #include "qom/object.h" +#include "net/can_emu.h" =20 struct XlnxZCU102 { MachineState parent_obj; @@ -34,6 +35,8 @@ struct XlnxZCU102 { bool secure; bool virt; =20 + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; + struct arm_boot_info binfo; }; typedef struct XlnxZCU102 XlnxZCU102; @@ -127,6 +130,14 @@ static void xlnx_zcu102_init(MachineState *machine) object_property_set_bool(OBJECT(&s->soc), "virtualization", s->virt, &error_fatal); =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { + gchar *bus_name =3D g_strdup_printf("canbus%d", i); + + object_property_set_link(OBJECT(&s->soc), bus_name, + OBJECT(s->canbus[i]), &error_fatal); + g_free(bus_name); + } + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); =20 /* Create and plug in the SD cards */ @@ -222,6 +233,15 @@ static void xlnx_zcu102_machine_instance_init(Object *= obj) "Set on/off to enable/disable emulatin= g a " "guest CPU which implements the ARM " "Virtualization Extensions"); + object_property_add_link(obj, "xlnx-zcu102.canbus0", TYPE_CAN_BUS, + (Object **)&s->canbus[0], + object_property_allow_set_link, + 0); + + object_property_add_link(obj, "xlnx-zcu102.canbus1", TYPE_CAN_BUS, + (Object **)&s->canbus[1], + object_property_allow_set_link, + 0); } =20 static void xlnx_zcu102_machine_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 7885bb1..8818472 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -81,6 +81,14 @@ static const int uart_intr[XLNX_ZYNQMP_NUM_UARTS] =3D { 21, 22, }; =20 +static const uint64_t can_addr[XLNX_ZYNQMP_NUM_CAN] =3D { + 0xFF060000, 0xFF070000, +}; + +static const int can_intr[XLNX_ZYNQMP_NUM_CAN] =3D { + 23, 24, +}; + static const uint64_t sdhci_addr[XLNX_ZYNQMP_NUM_SDHCI] =3D { 0xFF160000, 0xFF170000, }; @@ -243,6 +251,11 @@ static void xlnx_zynqmp_init(Object *obj) TYPE_CADENCE_UART); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { + object_initialize_child(obj, "can[*]", &s->can[i], + TYPE_XLNX_ZYNQMP_CAN); + } + object_initialize_child(obj, "sata", &s->sata, TYPE_SYSBUS_AHCI); =20 for (i =3D 0; i < XLNX_ZYNQMP_NUM_SDHCI; i++) { @@ -482,6 +495,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Erro= r **errp) gic_spi[uart_intr[i]]); } =20 + for (i =3D 0; i < XLNX_ZYNQMP_NUM_CAN; i++) { + object_property_set_int(OBJECT(&s->can[i]), "ext_clk_freq", + XLNX_ZYNQMP_CAN_REF_CLK, &error_abort); + + object_property_set_link(OBJECT(&s->can[i]), "canbus", + OBJECT(s->canbus[i]), &error_fatal); + + sysbus_realize(SYS_BUS_DEVICE(&s->can[i]), &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->can[i]), 0, can_addr[i]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->can[i]), 0, + gic_spi[can_intr[i]]); + } + object_property_set_int(OBJECT(&s->sata), "num-ports", SATA_NUM_PORTS, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->sata), errp)) { @@ -619,6 +649,10 @@ static Property xlnx_zynqmp_props[] =3D { DEFINE_PROP_BOOL("has_rpu", XlnxZynqMPState, has_rpu, false), DEFINE_PROP_LINK("ddr-ram", XlnxZynqMPState, ddr_ram, TYPE_MEMORY_REGI= ON, MemoryRegion *), + DEFINE_PROP_LINK("canbus0", XlnxZynqMPState, canbus[0], TYPE_CAN_BUS, + CanBusState *), + DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, + CanBusState *), DEFINE_PROP_END_OF_LIST() }; =20 diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 4cc97b4..ae91480 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -22,6 +22,7 @@ #include "hw/intc/arm_gic.h" #include "hw/net/cadence_gem.h" #include "hw/char/cadence_uart.h" +#include "hw/net/xlnx-zynqmp-can.h" #include "hw/ide/ahci.h" #include "hw/sd/sdhci.h" #include "hw/ssi/xilinx_spips.h" @@ -33,6 +34,7 @@ #include "hw/cpu/cluster.h" #include "target/arm/cpu.h" #include "qom/object.h" +#include "net/can_emu.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" typedef struct XlnxZynqMPState XlnxZynqMPState; @@ -43,6 +45,8 @@ DECLARE_INSTANCE_CHECKER(XlnxZynqMPState, XLNX_ZYNQMP, #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 #define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_NUM_UARTS 2 +#define XLNX_ZYNQMP_NUM_CAN 2 +#define XLNX_ZYNQMP_CAN_REF_CLK (24 * 1000 * 1000) #define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SPIS 2 #define XLNX_ZYNQMP_NUM_GDMA_CH 8 @@ -94,6 +98,7 @@ struct XlnxZynqMPState { =20 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; + XlnxZynqMPCANState can[XLNX_ZYNQMP_NUM_CAN]; SysbusAHCIState sata; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; @@ -114,6 +119,9 @@ struct XlnxZynqMPState { bool virt; /* Has the RPU subsystem? */ bool has_rpu; + + /* CAN bus. */ + CanBusState *canbus[XLNX_ZYNQMP_NUM_CAN]; }; =20 #endif --=20 2.7.4 From nobody Sun May 19 02:38:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1600121553; cv=pass; d=zohomail.com; s=zohoarc; b=mx1MqtoCTPydgXcY4bAEQpYQoPXd6JyTFof+NP2sh6dXd2dAZXgRbA/IiUHl5auyGXlGLsR1oldFKngtTtke4/wvZXOYq/04StZfGCu6wEKJgC+Zu7UXpl2Ctm3xy8mMsEDMYJUPHjEM251dFfvMySfzKoUcrZju4jaHu5jMlAs= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600121553; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CyhHu+eGkVZJ0tiUHoEQRBGhHlzKcFKvvXgH63fXQzo=; b=T/0IKN3hCKYbKhnSTTfZqCo22Y683dFBielrQpVu9xpCAKCDTqAvZshHfBxxJKlOm0kcytsHjkmQgMi9b1xFXSUZgOJFXrde80M2H+79aEdH2/rhnG8pQj9tJxrO4Pb/ApAml44sKQf6OwgQ0z5xZAKdVDlVd1zJroV11pvYfH0= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1600121553588943.7471629985721; Mon, 14 Sep 2020 15:12:33 -0700 (PDT) Received: from localhost ([::1]:42968 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kHwi7-0005Pn-T5 for importer@patchew.org; Mon, 14 Sep 2020 18:12:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53468) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwfB-0001zm-Jt for qemu-devel@nongnu.org; Mon, 14 Sep 2020 18:09:29 -0400 Received: from mail-mw2nam10on2065.outbound.protection.outlook.com ([40.107.94.65]:27429 helo=NAM10-MW2-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwf7-0000ZX-Ov for qemu-devel@nongnu.org; Mon, 14 Sep 2020 18:09:29 -0400 Received: from MN2PR02CA0029.namprd02.prod.outlook.com (2603:10b6:208:fc::42) by CH2PR02MB6663.namprd02.prod.outlook.com (2603:10b6:610:7e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16; Mon, 14 Sep 2020 22:09:17 +0000 Received: from BL2NAM02FT031.eop-nam02.prod.protection.outlook.com (2603:10b6:208:fc:cafe::6d) by MN2PR02CA0029.outlook.office365.com (2603:10b6:208:fc::42) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:17 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by BL2NAM02FT031.mail.protection.outlook.com (10.152.77.173) with Microsoft SMTP Server id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:17 +0000 Received: from [149.199.38.66] (port=48269 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1kHweu-0003rf-7s; Mon, 14 Sep 2020 15:09:12 -0700 Received: from [127.0.0.1] (helo=localhost) by smtp.xilinx.com with smtp (Exim 4.63) (envelope-from ) id 1kHwez-0006ms-0V; Mon, 14 Sep 2020 15:09:17 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 08EM98uQ012052; Mon, 14 Sep 2020 15:09:08 -0700 Received: from [172.19.2.115] (helo=xsjfnuv50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kHweq-0006b8-MS; Mon, 14 Sep 2020 15:09:08 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=TlZRVFsKEiZcDqRAcqsuaHH6u/5UND+YoffdXQ0ykiR70KAQg8S5wtFU1u3SLJne/WoyKvCTvFfphYJNfpz1upb1hurOVQcD7H0PvmgukcXMQMtrk0Q4CcxJPWJLUsI4u/u4ceKfYcVNKeSbm3XqYqoqiFbW3AxQOQNA+PGncNG20BONw0LJGEgDXHLpwf3oDw6MQv2FqzQEApEU/KVw0sRtG89FEJb7IUilKwXS/KMRdRNXM+gQ4kS027Q0zfwhNCNG30l/eVjMZIj/nhavYV3h2QYYuWtXwoRg/OAegy5HjRo2e2jQYdgMxnUkxdMag/FvPPv8cNo4lNoZ6nZqJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CyhHu+eGkVZJ0tiUHoEQRBGhHlzKcFKvvXgH63fXQzo=; b=H//8isE4SP5Sk6JCH65Piit/d/AZsNdt7IvJVaCStVsuYfiZlk6LIqPV/bHmwAxlARolYiw3zLygEedXS1/ReD6TVFpj2IXDGouD0EPfSHT/pc3mHy9GwQzkKRqGk4qXEfs8xP/fYDlJz31RT2Ygdu1xT/HD1WGSIIQX3VhwIOZwHbSfEMvT6sQtj7j/S3UGzEuCXQvTBT09cRkLnVYvul63IbmmHdEpzPkl175l0btGyFWpt6HrXH5w4fcB8atYiLw1uXfHxbtQcqGGtLgxFKzsumjnIr63iKQ4bw0TIskCaWlNqKUediD1gHax7sYdSHochI8MzA+RW5xIvzp08Q== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=redhat.com smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=CyhHu+eGkVZJ0tiUHoEQRBGhHlzKcFKvvXgH63fXQzo=; b=rzmbqUtOPn1oiA65s0dcTbiGQ1r8NIALf5ekwd11EkPdjE4765ONueyo76om9s8XqVnVfBsmVQBxEzyaVBqIUX6zNcojNE72Yry/vRj6Pk8hzNlDT0+20OqvVR/Up2Wclu0XeAwYTmN1F5/Y2TUdj05oXGeNy++Iv6y/i5sDkxU= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; redhat.com; dkim=none (message not signed) header.d=none;redhat.com; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; From: Vikram Garhwal To: qemu-devel@nongnu.org Subject: [PATCH v10 3/4] tests/qtest: Introduce tests for Xilinx ZynqMP CAN controller Date: Mon, 14 Sep 2020 15:08:43 -0700 Message-Id: <1600121324-31337-4-git-send-email-fnu.vikram@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> References: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: bf9f7380-d469-4568-fc9b-08d858fad2c2 X-MS-TrafficTypeDiagnostic: CH2PR02MB6663: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:7691; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 3NNm4qp+zGARa7kxwTzBEoyvlaeYiANZzXn4Pc5SD0AYAklVMv/r7+RScPPelfOZNUie1wd0MJXYOZvooV0+2X6GMraQak8S8qQhCe8ot2mSC6EvOIKn/KT8Zze3LoacB+HbQR3QgpPxklN8Ij4I//OJN0C7p8Q/AEzIr9JhHsQnzVbz/FuL2/cS2PtCJSpqL/NqBrDyoL4z5Qi2bfBPo8ppegFjyv4Ph4muFnLWKX17YYmhKgM0/0ZFUdWMfvxlQznVUfS1NY3nx9duCw/v08mYbP039wKEFGFC/9jyJ2CoFPj68tiBB6rSxBCuGJCojoSVNmqgXbZ8bj+WeZmCW1S+2FxAZJkojMw6n5W1J9UJLdI6ufekVOVLN5b5oolnFkgVdajGZkwc+cRoKzrTNw== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(376002)(39860400002)(346002)(136003)(396003)(46966005)(6916009)(9786002)(82310400003)(47076004)(316002)(186003)(6666004)(8676002)(82740400003)(336012)(36756003)(2906002)(26005)(70586007)(70206006)(7696005)(8936002)(4326008)(356005)(5660300002)(478600001)(83380400001)(81166007)(426003)(54906003)(30864003)(2616005); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2020 22:09:17.3917 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bf9f7380-d469-4568-fc9b-08d858fad2c2 X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: BL2NAM02FT031.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR02MB6663 Received-SPF: pass client-ip=40.107.94.65; envelope-from=fnuv@xilinx.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/14 18:09:21 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , peter.maydell@linaro.org, Thomas Huth , Vikram Garhwal , francisco.iglesias@xilinx.com, Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The QTests perform five tests on the Xilinx ZynqMP CAN controller: Tests the CAN controller in loopback, sleep and snoop mode. Tests filtering of incoming CAN messages. Reviewed-by: Francisco Iglesias Signed-off-by: Vikram Garhwal Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- tests/qtest/meson.build | 1 + tests/qtest/xlnx-can-test.c | 359 ++++++++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 360 insertions(+) create mode 100644 tests/qtest/xlnx-can-test.c diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 874b5be..945f86c 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -148,6 +148,7 @@ qtests_aarch64 =3D \ (config_all_devices.has_key('CONFIG_TPM_TIS_SYSBUS') ? ['tpm-tis-device-= swtpm-test'] : []) + \ ['numa-test', 'boot-serial-test', + 'xlnx-can-test', 'migration-test'] =20 qtests_s390x =3D \ diff --git a/tests/qtest/xlnx-can-test.c b/tests/qtest/xlnx-can-test.c new file mode 100644 index 0000000..d04189f --- /dev/null +++ b/tests/qtest/xlnx-can-test.c @@ -0,0 +1,359 @@ +/* + * QTests for the Xilinx ZynqMP CAN controller. + * + * Copyright (c) 2020 Xilinx Inc. + * + * Written-by: Vikram Garhwal + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "libqos/libqtest.h" + +/* Base address. */ +#define CAN0_BASE_ADDR 0xFF060000 +#define CAN1_BASE_ADDR 0xFF070000 + +/* Register addresses. */ +#define R_SRR_OFFSET 0x00 +#define R_MSR_OFFSET 0x04 +#define R_SR_OFFSET 0x18 +#define R_ISR_OFFSET 0x1C +#define R_ICR_OFFSET 0x24 +#define R_TXID_OFFSET 0x30 +#define R_TXDLC_OFFSET 0x34 +#define R_TXDATA1_OFFSET 0x38 +#define R_TXDATA2_OFFSET 0x3C +#define R_RXID_OFFSET 0x50 +#define R_RXDLC_OFFSET 0x54 +#define R_RXDATA1_OFFSET 0x58 +#define R_RXDATA2_OFFSET 0x5C +#define R_AFR 0x60 +#define R_AFMR1 0x64 +#define R_AFIR1 0x68 +#define R_AFMR2 0x6C +#define R_AFIR2 0x70 +#define R_AFMR3 0x74 +#define R_AFIR3 0x78 +#define R_AFMR4 0x7C +#define R_AFIR4 0x80 + +/* CAN modes. */ +#define CONFIG_MODE 0x00 +#define NORMAL_MODE 0x00 +#define LOOPBACK_MODE 0x02 +#define SNOOP_MODE 0x04 +#define SLEEP_MODE 0x01 +#define ENABLE_CAN (1 << 1) +#define STATUS_NORMAL_MODE (1 << 3) +#define STATUS_LOOPBACK_MODE (1 << 1) +#define STATUS_SNOOP_MODE (1 << 12) +#define STATUS_SLEEP_MODE (1 << 2) +#define ISR_TXOK (1 << 1) +#define ISR_RXOK (1 << 4) + +static void match_rx_tx_data(uint32_t *buf_tx, uint32_t *buf_rx, + uint8_t can_timestamp) +{ + uint16_t size =3D 0; + uint8_t len =3D 4; + + while (size < len) { + if (R_RXID_OFFSET + 4 * size =3D=3D R_RXDLC_OFFSET) { + g_assert_cmpint(buf_rx[size], =3D=3D, buf_tx[size] + can_times= tamp); + } else { + g_assert_cmpint(buf_rx[size], =3D=3D, buf_tx[size]); + } + + size++; + } +} + +static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *b= uf_rx) +{ + uint32_t int_status; + + /* Read the interrupt on CAN rx. */ + int_status =3D qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RX= OK; + + g_assert_cmpint(int_status, =3D=3D, ISR_RXOK); + + /* Read the RX register data for CAN. */ + buf_rx[0] =3D qtest_readl(qts, can_base_addr + R_RXID_OFFSET); + buf_rx[1] =3D qtest_readl(qts, can_base_addr + R_RXDLC_OFFSET); + buf_rx[2] =3D qtest_readl(qts, can_base_addr + R_RXDATA1_OFFSET); + buf_rx[3] =3D qtest_readl(qts, can_base_addr + R_RXDATA2_OFFSET); + + /* Clear the RX interrupt. */ + qtest_writel(qts, CAN1_BASE_ADDR + R_ICR_OFFSET, ISR_RXOK); +} + +static void send_data(QTestState *qts, uint64_t can_base_addr, uint32_t *b= uf_tx) +{ + uint32_t int_status; + + /* Write the TX register data for CAN. */ + qtest_writel(qts, can_base_addr + R_TXID_OFFSET, buf_tx[0]); + qtest_writel(qts, can_base_addr + R_TXDLC_OFFSET, buf_tx[1]); + qtest_writel(qts, can_base_addr + R_TXDATA1_OFFSET, buf_tx[2]); + qtest_writel(qts, can_base_addr + R_TXDATA2_OFFSET, buf_tx[3]); + + /* Read the interrupt on CAN for tx. */ + int_status =3D qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_TX= OK; + + g_assert_cmpint(int_status, =3D=3D, ISR_TXOK); + + /* Clear the interrupt for tx. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_ICR_OFFSET, ISR_TXOK); +} + +/* + * This test will be transferring data from CAN0 and CAN1 through canbus. = CAN0 + * initiate the data transfer to can-bus, CAN1 receives the data. Test com= pares + * the data sent from CAN0 with received on CAN1. + */ +static void test_can_bus(void) +{ + uint32_t buf_tx[4] =3D { 0xFF, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0 and CAN1. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 and CAN1 are in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + send_data(qts, CAN0_BASE_ADDR, buf_tx); + + read_data(qts, CAN1_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +/* + * This test is performing loopback mode on CAN0 and CAN1. Data sent from = TX of + * each CAN0 and CAN1 are compared with RX register data for respective CA= N. + */ +static void test_can_loopback(void) +{ + uint32_t buf_tx[4] =3D { 0xFF, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0 in loopback mode. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + /* Check here if CAN0 is set in loopback mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + + g_assert_cmpint(status, =3D=3D, STATUS_LOOPBACK_MODE); + + send_data(qts, CAN0_BASE_ADDR, buf_tx); + read_data(qts, CAN0_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, 0); + + /* Configure the CAN1 in loopback mode. */ + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, LOOPBACK_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + /* Check here if CAN1 is set in loopback mode. */ + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + + g_assert_cmpint(status, =3D=3D, STATUS_LOOPBACK_MODE); + + send_data(qts, CAN1_BASE_ADDR, buf_tx); + read_data(qts, CAN1_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, 0); + + qtest_quit(qts); +} + +/* + * Enable filters for CAN1. This will filter incoming messages with ID. In= this + * test message will pass through filter 2. + */ +static void test_can_filter(void) +{ + uint32_t buf_tx[4] =3D { 0x14, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0 and CAN1. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 and CAN1 are in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + /* Set filter for CAN1 for incoming messages. */ + qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0x0); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR1, 0xF7); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR1, 0x121F); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR2, 0x5431); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR2, 0x14); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR3, 0x1234); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR3, 0x5431); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFMR4, 0xFFF); + qtest_writel(qts, CAN1_BASE_ADDR + R_AFIR4, 0x1234); + + qtest_writel(qts, CAN1_BASE_ADDR + R_AFR, 0xF); + + send_data(qts, CAN0_BASE_ADDR, buf_tx); + + read_data(qts, CAN1_BASE_ADDR, buf_rx); + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +/* Testing sleep mode on CAN0 while CAN1 is in normal mode. */ +static void test_can_sleepmode(void) +{ + uint32_t buf_tx[4] =3D { 0x14, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SLEEP_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 is in SLEEP mode and CAN1 in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_SLEEP_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + send_data(qts, CAN1_BASE_ADDR, buf_tx); + + /* + * Once CAN1 sends data on can-bus. CAN0 should exit sleep mode. + * Check the CAN0 status now. It should exit the sleep mode and receiv= e the + * incoming data. + */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + read_data(qts, CAN0_BASE_ADDR, buf_rx); + + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +/* Testing Snoop mode on CAN0 while CAN1 is in normal mode. */ +static void test_can_snoopmode(void) +{ + uint32_t buf_tx[4] =3D { 0x14, 0x80000000, 0x12345678, 0x87654321 }; + uint32_t buf_rx[4] =3D { 0x00, 0x00, 0x00, 0x00 }; + uint32_t status =3D 0; + uint8_t can_timestamp =3D 1; + + QTestState *qts =3D qtest_init("-machine xlnx-zcu102" + " -object can-bus,id=3Dcanbus0" + " -machine xlnx-zcu102.canbus0=3Dcanbus0" + " -machine xlnx-zcu102.canbus1=3Dcanbus0" + ); + + /* Configure the CAN0. */ + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, CONFIG_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_MSR_OFFSET, SNOOP_MODE); + qtest_writel(qts, CAN0_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + + qtest_writel(qts, CAN1_BASE_ADDR + R_SRR_OFFSET, ENABLE_CAN); + qtest_writel(qts, CAN1_BASE_ADDR + R_MSR_OFFSET, NORMAL_MODE); + + /* Check here if CAN0 is in SNOOP mode and CAN1 in normal mode. */ + status =3D qtest_readl(qts, CAN0_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_SNOOP_MODE); + + status =3D qtest_readl(qts, CAN1_BASE_ADDR + R_SR_OFFSET); + g_assert_cmpint(status, =3D=3D, STATUS_NORMAL_MODE); + + send_data(qts, CAN1_BASE_ADDR, buf_tx); + + read_data(qts, CAN0_BASE_ADDR, buf_rx); + + match_rx_tx_data(buf_tx, buf_rx, can_timestamp); + + qtest_quit(qts); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("/net/can/can_bus", test_can_bus); + qtest_add_func("/net/can/can_loopback", test_can_loopback); + qtest_add_func("/net/can/can_filter", test_can_filter); + qtest_add_func("/net/can/can_test_snoopmode", test_can_snoopmode); + qtest_add_func("/net/can/can_test_sleepmode", test_can_sleepmode); + + return g_test_run(); +} --=20 2.7.4 From nobody Sun May 19 02:38:15 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) ARC-Seal: i=2; a=rsa-sha256; t=1600121611; cv=pass; d=zohomail.com; s=zohoarc; b=mTrwO+CFsKjbXtSI3Uh08Mc1zEuPTE4cEyo14AHMGuExL8P9KvWvx2wOWmnqyp2K+an4FQRW56P7F6XKM2YjFfV1HrzmkzZb3mYYfVm8Abxp0dwkBnpEacBqLcZx49ge0IvWBspa3RtX+g+LPBcEH8UmSAtNZt36pgv7UVSCCVU= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1600121611; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p4PNk8X1Y6UouQFxlXBjBuJd7p/B5lfjCLCLCsGHQYM=; b=eYXk6neLJPVN9njVkhgkq/aS6a4lEnxXuqmJ6h6lB9V/BLx2Mr41vKFsHNYOzMvP4oSdcQK3joj69gGiqQTYz2y6pChm0sFAwCs0+6BOifHUxDfpw0VTQ6p5drDP0LxtX8vVft+RDX+aR3Khj3At0UpsKstMrY8B2lXgPGz1Xr0= ARC-Authentication-Results: i=2; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=xilinx.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 160012161121118.965147743521356; Mon, 14 Sep 2020 15:13:31 -0700 (PDT) Received: from localhost ([::1]:44806 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kHwj4-0006AV-4H for importer@patchew.org; Mon, 14 Sep 2020 18:13:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53484) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwfD-00023R-K8 for qemu-devel@nongnu.org; Mon, 14 Sep 2020 18:09:31 -0400 Received: from mail-bn7nam10on2041.outbound.protection.outlook.com ([40.107.92.41]:30816 helo=NAM10-BN7-obe.outbound.protection.outlook.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kHwfB-0000bG-Kp for qemu-devel@nongnu.org; Mon, 14 Sep 2020 18:09:31 -0400 Received: from CY4PR18CA0025.namprd18.prod.outlook.com (2603:10b6:903:9a::11) by DM5PR0201MB3478.namprd02.prod.outlook.com (2603:10b6:4:76::32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16; Mon, 14 Sep 2020 22:09:28 +0000 Received: from CY1NAM02FT008.eop-nam02.prod.protection.outlook.com (2603:10b6:903:9a:cafe::b2) by CY4PR18CA0025.outlook.office365.com (2603:10b6:903:9a::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:28 +0000 Received: from xsj-pvapsmtpgw01 (149.199.60.83) by CY1NAM02FT008.mail.protection.outlook.com (10.152.75.59) with Microsoft SMTP Server id 15.20.3370.16 via Frontend Transport; Mon, 14 Sep 2020 22:09:27 +0000 Received: from [149.199.38.66] (port=48402 helo=smtp.xilinx.com) by xsj-pvapsmtpgw01 with esmtp (Exim 4.90) (envelope-from ) id 1kHwf4-0003rr-VJ; Mon, 14 Sep 2020 15:09:22 -0700 Received: from [127.0.0.1] (helo=localhost) by smtp.xilinx.com with smtp (Exim 4.63) (envelope-from ) id 1kHwf9-0006oW-9x; Mon, 14 Sep 2020 15:09:27 -0700 Received: from xsj-pvapsmtp01 (smtp.xilinx.com [149.199.38.66]) by xsj-smtp-dlp2.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id 08EM9IcT016843; Mon, 14 Sep 2020 15:09:18 -0700 Received: from [172.19.2.115] (helo=xsjfnuv50.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1kHwez-0006b8-UB; Mon, 14 Sep 2020 15:09:17 -0700 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=Zy95rqLUDeBJGKC+3Hio239+uBtkz82ipA+ddA/YWArpo31KbST/LWvm5q4m9kN63Rei3Mf6nkKcy6iCRasiFgx3HEFgmAXJLYjUN9n1A6BjAiZ+R8a00VhNCPF6ND7QiHmzRIHUjtrX2d8VDcL3+lsHylcjjdOnPSH3Z2AIG0mBhYissPlMDMC5LiKTr2jlutrB1dNmwRREpKOPY89OOXmIS8GGehwCRhZR8UQ+G69OCuTqpFZ8V0k4b7yGQUk4DTD1Yo/IfAHOdu3U+8waVEQ/+P0MZ1Uhlp6YNFP+mufO6bkKi7LhAP06ywwvihf1+eLL1C0ib7TxV6WZwozK0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p4PNk8X1Y6UouQFxlXBjBuJd7p/B5lfjCLCLCsGHQYM=; b=QeYRqwJIBS3iS24TeBXRiJ4UgqdeavOi/RsZ5mQjxcq5jLs/bXH0USpevrUlp0aGSUC7M+wNQbclP6HG41w59nAoQnXYxi6Pd+BScVFAEqzZ7H6ovxViDvxsElmpdMWghfJIhKsUSYxaMm39F3j2to0wYmXb5jm1RtmmQSAUdczTXu/yaFuPKNQPGZA9c1tFJRdm3sFr+50wwraGsOSV+DemLH5Ky6eWiBjQ8skk6Z6wwXvUHdc5FzBA2R0mSOWtHG1x+YmMd2bvMmyrN7tEx014Tf+CLMLw6qCNyD0xy1FOyXQOhJq0SJkxBgTUAMyTbWU5i31EKHfmPJAB+WwWSA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 149.199.60.83) smtp.rcpttodomain=linaro.org smtp.mailfrom=xilinx.com; dmarc=bestguesspass action=none header.from=xilinx.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=xilinx.onmicrosoft.com; s=selector2-xilinx-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=p4PNk8X1Y6UouQFxlXBjBuJd7p/B5lfjCLCLCsGHQYM=; b=qWhA/yZnP1Z5DXMVEH/1dmEHQM1vSk1yPc0i2xSyMvbjyHEatorQ3/pBSjZebesSrvzEpl+rUQZ9HtTDhciwKw+IDJtv4d6L+afB3i/yfZjbrjyAj3EjqP0cPg8QC9u/ro6G9UI6vNhX9eiW/hXXkCBZua/vaD5NPjouKNo/uqg= X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 149.199.60.83) smtp.mailfrom=xilinx.com; linaro.org; dkim=none (message not signed) header.d=none;linaro.org; dmarc=bestguesspass action=none header.from=xilinx.com; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: Pass (protection.outlook.com: domain of xilinx.com designates 149.199.60.83 as permitted sender) receiver=protection.outlook.com; client-ip=149.199.60.83; helo=xsj-pvapsmtpgw01; From: Vikram Garhwal To: qemu-devel@nongnu.org Subject: [PATCH v10 4/4] MAINTAINERS: Add maintainer entry for Xilinx ZynqMP CAN controller Date: Mon, 14 Sep 2020 15:08:44 -0700 Message-Id: <1600121324-31337-5-git-send-email-fnu.vikram@xilinx.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> References: <1600121324-31337-1-git-send-email-fnu.vikram@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email MIME-Version: 1.0 X-MS-Office365-Filtering-Correlation-Id: 8af008e2-c20b-4dae-f647-08d858fad90e X-MS-TrafficTypeDiagnostic: DM5PR0201MB3478: X-Microsoft-Antispam-PRVS: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-Oob-TLC-OOBClassifiers: OLM:331; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Of7ZErmDB2e3zdOyzf7MkA1a3GSBbLRCgmcADzvRQx9eYkZvj6onoLSUe3irVQUlaPWprZddemiroBoS6lbYYUFixN5D7r6ZCIbN9rWJ5tsqPicY5MWSLGXPdnhWLkWsOaHsYysfx5A22buVC91ARuJAU146MPROAD5WqfzNPLyIgt+QOJovYdIYt2WTQi7vunxDtOp2T4XGbHPIC8b7goJBTberR/wtMOpNRKyLGIe17IqTfGmQi9HJoJSXnxPtNjK6ijFoOPBGfn3gSq0PHNAYTlSsXTvWy9Sl22IWazvRU8y2IMQziN55UPgJGOSiyxg7fsHdZ6b0+KKntvaZyCkOREjzKjuFOccs67UqAV/Gkii95F9a6RPJkpR6v6htY6hL+FGsjCKk5+F8Ew8kSw== X-Forefront-Antispam-Report: CIP:149.199.60.83; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:xsj-pvapsmtpgw01; PTR:unknown-60-83.xilinx.com; CAT:NONE; SFS:(346002)(39860400002)(376002)(136003)(396003)(46966005)(5660300002)(356005)(82310400003)(478600001)(4744005)(6916009)(82740400003)(81166007)(8936002)(8676002)(47076004)(9786002)(70206006)(6666004)(7696005)(186003)(426003)(26005)(2906002)(336012)(36756003)(316002)(70586007)(107886003)(4326008)(2616005); DIR:OUT; SFP:1101; X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2020 22:09:27.9599 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8af008e2-c20b-4dae-f647-08d858fad90e X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-AuthSource: CY1NAM02FT008.eop-nam02.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR0201MB3478 Received-SPF: pass client-ip=40.107.92.41; envelope-from=fnuv@xilinx.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/14 18:09:28 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: francisco.iglesias@xilinx.com, Vikram Garhwal , peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @xilinx.onmicrosoft.com) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Reviewed-by: Francisco Iglesias Reviewed-by: Edgar E. Iglesias Signed-off-by: Vikram Garhwal --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3d17cad..3ed61d9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1557,6 +1557,14 @@ F: hw/net/opencores_eth.c =20 Devices ------- +Xilinx CAN +M: Vikram Garhwal +M: Francisco Iglesias +S: Maintained +F: hw/net/can/xlnx-* +F: include/hw/net/xlnx-* +F: tests/qtest/xlnx-can-test* + EDU M: Jiri Slaby S: Maintained --=20 2.7.4