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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:40:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=f9xPWqK/SJaS8qAyoj5c6x49mf3bnJcQ9LW5OzQOSD0=; b=nonh+PiGReuSWRymd3lFRozWZXkix+l5P5P5aWFpez/GU7ZIFY1OY57XqWFWuXIzM9 98jfneisEVo+8lFbbldgStYm8cFLDWP15zwQbiPcPm95/tSFNqKQzESGkOC+IVGab2C+ xhj4u2k+NVDo+cXm3GFIfeiDlovRB/+1oGdW2oqCFFOud/497qUR2Ap40fxkANzpZMZP VWTFEweSk0TGFSOPZJH9urbMLHgiZIEDs2qBmxDH6xV71p/AI64aFi2aqJt0gWJdu6MZ Q+xv2jPfUBZK3igNnAno8k8hWLEbB6v8xYedojDLKNiwkPE86UejnEBUbuUb2nUm2ahb v/HQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=f9xPWqK/SJaS8qAyoj5c6x49mf3bnJcQ9LW5OzQOSD0=; b=CK2D8xZ0qkkUVfZDF2A1kCnl6NjpeAFEmFsBiA/2a24LPa8Hzyq1UiEAwQZzyb/l3u yubc2iEOQDlqsSh/jO5EhjQRrvM/9e4aF8oUs7ci98E2IBERnN8U7ogQPlL7eS+8yhd1 inOQMq3gOJaE+5CzYZYQAJQGQFS47WGAx7zyJFAJ1G/xNK2DXXL/KMJ1P/JhHZd/leJP 4FIOuS/TP9fDS5dh1BqFjgUlobfu/FGxCuurvJ+5Ymn9jknsLChoWCjpMoVY2PY3aFxz JayGggMWuu8Lqs8rPlvgeWAu5AsLtWQyrQHBJURZhEBCTmbrR4eymh1VYOtoCKBRqEnM R/zg== X-Gm-Message-State: AOAM532gTznLILcNCDHI5BPwfTDbuNnggX5elvVJdnomvqR4akCl4wPM cEYjzCw8fP/fRCUSQ9qNK+g= X-Google-Smtp-Source: ABdhPJyINGEjWpyWidqwfLsdiSUshWJe/hSO7swIoCy7m2uT6pGbVvQVGrvhCxIudf68WTd9MiJALg== X-Received: by 2002:a62:fb05:: with SMTP id x5mr3246869pfm.121.1599129641855; Thu, 03 Sep 2020 03:40:41 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 01/12] hw/riscv: Move sifive_e_prci model to hw/misc Date: Thu, 3 Sep 2020 18:40:12 +0800 Message-Id: <1599129623-68957-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_e_prci model to hw/misc directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/{riscv =3D> misc}/sifive_e_prci.h | 0 hw/{riscv =3D> misc}/sifive_e_prci.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/misc/Kconfig | 3 +++ hw/misc/meson.build | 3 +++ hw/riscv/Kconfig | 1 + hw/riscv/meson.build | 1 - 7 files changed, 9 insertions(+), 3 deletions(-) rename include/hw/{riscv =3D> misc}/sifive_e_prci.h (100%) rename hw/{riscv =3D> misc}/sifive_e_prci.c (99%) diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/misc/sifive_e_pr= ci.h similarity index 100% rename from include/hw/riscv/sifive_e_prci.h rename to include/hw/misc/sifive_e_prci.h diff --git a/hw/riscv/sifive_e_prci.c b/hw/misc/sifive_e_prci.c similarity index 99% rename from hw/riscv/sifive_e_prci.c rename to hw/misc/sifive_e_prci.c index 17dfa74..8ec4ee4 100644 --- a/hw/riscv/sifive_e_prci.c +++ b/hw/misc/sifive_e_prci.c @@ -24,7 +24,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "hw/hw.h" -#include "hw/riscv/sifive_e_prci.h" +#include "hw/misc/sifive_e_prci.h" =20 static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int= size) { diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 36ccfb2..7f43ed9 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -43,8 +43,8 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" -#include "hw/riscv/sifive_e_prci.h" #include "hw/riscv/boot.h" +#include "hw/misc/sifive_e_prci.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 92c397c..5073986 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -134,4 +134,7 @@ config MAC_VIA config AVR_POWER bool =20 +config SIFIVE_E_PRCI + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index e1576b8..b6b2e57 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -21,6 +21,9 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('a= rm11scu.c')) # Mac devices softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) =20 +# RISC-V devices +softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci= .c')) + # PKUnity SoC devices softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c')) =20 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index e53ab1e..5855e99 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E bool select HART select SIFIVE + select SIFIVE_E_PRCI select UNIMP =20 config SIFIVE_U diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index cf1aa99..d73ea99 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -10,7 +10,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifiv= e_plic.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.42 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:40:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=8Zj7s7kXmzr2lI2HnuVfE43cFixL7CM5rG/130yS5Ic=; b=J0hROt1ICD0aLJOruYu7Q1yyNWjz4OBJLkZjq/LIrJAjeSNRKrmDDkHVeSmT/i/VVM bF31KIQXJcleYHVDJ8E/FSmTpjwVQd9vKfsix9EnQvOyX+o7VUJ57maytuY7LSio/FXT ra2Qxtx1sh0GD9O1U7hBs0qcdkQTCfb7WD0njgSV21ay/JoqMwZPjv/Xknbc4I5lKPjV 63Nrmq16BDraOxtdE2x/j2yAh41lPxFSdH2afSSOoxPBUd/9B6EwRIpeKLdxSdFciwrw BvWNW64ToYWZjxYVzOthLqjnCc0KlwQGt9Kq+woNo+GS833E70gCUfDAAoEKmDyxEDFY DRzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=8Zj7s7kXmzr2lI2HnuVfE43cFixL7CM5rG/130yS5Ic=; b=FeaDxyKgT6+H3bg5dz3EV8W0EvVM35L5ifU3gWlgtOYKoANyWS8L2HBENzePB62OV5 Y+yVKiAaSmjQfHGeEHHyR1P4y4jHxmuRuxdVqYlFO5vfkL2GrcM7anMy/875zQLcw4EB sDH7g+XJYaYoVOl3ynexoSMsMHxQzp9wu3nTTqJq5FOOAiUXVsEhaIhjLsDQkcwtKKu2 Ls1JME+vyXfeIedoYFzMjJOSgoB/JBCGtSmEvmenVQcPM5ckrztcdJhbNH4rYkvBzQGY OBQzKX+ixQE3ASzTLNjv/3uwft3cq5kLPtnRyXUlicUix+UeERNlUWR8banRTJ4hAKUX JCIA== X-Gm-Message-State: AOAM5333DEiOVilzZFvH3DidIQGqNBEoGEhaNMGmjt8VGtOM/0ZNGg8k yhKQprL75KCrBKb5oWggPls= X-Google-Smtp-Source: ABdhPJwbiaMobmHaTg3eucQm8X2JetEdR1wfmEZhkHmGV877kXpPhLy6BhOx0dtfvUhLxAwLQUYKdg== X-Received: by 2002:a17:902:6bc2:: with SMTP id m2mr3303704plt.114.1599129644320; Thu, 03 Sep 2020 03:40:44 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 02/12] hw/riscv: Move sifive_u_prci model to hw/misc Date: Thu, 3 Sep 2020 18:40:13 +0800 Message-Id: <1599129623-68957-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::441; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x441.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_u_prci model to hw/misc directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/{riscv =3D> misc}/sifive_u_prci.h | 0 include/hw/riscv/sifive_u.h | 2 +- hw/{riscv =3D> misc}/sifive_u_prci.c | 2 +- hw/misc/Kconfig | 3 +++ hw/misc/meson.build | 1 + hw/riscv/Kconfig | 1 + hw/riscv/meson.build | 1 - 7 files changed, 7 insertions(+), 3 deletions(-) rename include/hw/{riscv =3D> misc}/sifive_u_prci.h (100%) rename hw/{riscv =3D> misc}/sifive_u_prci.c (99%) diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/misc/sifive_u_pr= ci.h similarity index 100% rename from include/hw/riscv/sifive_u_prci.h rename to include/hw/misc/sifive_u_prci.h diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 793000a..cbeb228 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -24,8 +24,8 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" -#include "hw/riscv/sifive_u_prci.h" #include "hw/riscv/sifive_u_otp.h" +#include "hw/misc/sifive_u_prci.h" =20 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ diff --git a/hw/riscv/sifive_u_prci.c b/hw/misc/sifive_u_prci.c similarity index 99% rename from hw/riscv/sifive_u_prci.c rename to hw/misc/sifive_u_prci.c index 4fa590c..5d9d446 100644 --- a/hw/riscv/sifive_u_prci.c +++ b/hw/misc/sifive_u_prci.c @@ -22,7 +22,7 @@ #include "hw/sysbus.h" #include "qemu/log.h" #include "qemu/module.h" -#include "hw/riscv/sifive_u_prci.h" +#include "hw/misc/sifive_u_prci.h" =20 static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int= size) { diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 5073986..65f3fdd 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -137,4 +137,7 @@ config AVR_POWER config SIFIVE_E_PRCI bool =20 +config SIFIVE_U_PRCI + bool + source macio/Kconfig diff --git a/hw/misc/meson.build b/hw/misc/meson.build index b6b2e57..9e9550e 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mo= s6522.c')) =20 # RISC-V devices softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci= .c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci= .c')) =20 # PKUnity SoC devices softmmu_ss.add(when: 'CONFIG_PUV3', if_true: files('puv3_pm.c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 5855e99..109364b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -24,6 +24,7 @@ config SIFIVE_U select HART select SIFIVE select SIFIVE_PDMA + select SIFIVE_U_PRCI select UNIMP =20 config SPIKE diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index d73ea99..e6c8af0 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -12,7 +12,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifiv= e_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=UwDaAVEiFSZ9mLDfhLuxqgfHtEhiPD/jjAdGrjSJZeM=; b=MUJOZ5EkSuzdSHnunCuf5vMZ9Zij4XlZmFWBqs/Cpe0Y8PwLvzpiK7lwEYNc5guKzX SFAwi2gF7BLR01tYb7VRdSod6OZ7ONeheIA/yRKQHGZKX93VH4352geQsgSSbUt00lo6 AITjWNwX347UMB4hoJOgBFEADb4GWGAc8pgT83AG+5DN3S9XJZOpX5/vm8Iru1ycDVSr zLC44udY/gBfb+6bYaOQZTrOnD4p4L0fOcZPEPF6cO5ZNQYdOlVbCg4PktWn75dkUoom Kt9ZTExf3ZA3sOdGYcNvDEWYrwFhevqGU8uB9yOP3ozoPRIZvvi8OK21Tf/WzJwTH/j9 srxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UwDaAVEiFSZ9mLDfhLuxqgfHtEhiPD/jjAdGrjSJZeM=; b=Wh3Y2mrcfifkXYXFF5pyNbGkcWu5VADb6wQ0qNZ6b6boFYv02PwtQp0NV3/j0W5Hei sG6QVamJ4gXsYxkmQs+bh0FAlpgwY9egVgaaAw5Vg74MPz0EQkG3MxRbamKcvONcgvTW xBmHOpaDs05FUQLTZMfvjGduq87HfulhU4CNtqhyqZVSx1nI6T2VYQmDi/BHBNgFxVMK 2swe/qYVG1763O08jWOGQ7w+DaWHOdAAPEM9RdqDmkB0k1JTx8UyYU4GRf9+3Nj1Oeil Es+cpj1c1dWfzChXoPKUEsCHWqknZeUorLc3qiorXiob+6Q9oFvhoihYD4cpaLULHuX+ 1qbw== X-Gm-Message-State: AOAM532eYXvJ4hfV/OCUHgbOy2umMKey+3T5BAI3KlC76NUXZysgCFy3 /E/90D1ld2ZHaFOnOkE3eZc= X-Google-Smtp-Source: ABdhPJwE+YW1cApRQ1X0cI4T4yjYdV5t8GsN7v7Er02oDQpSQOloAngYX78gXhSxx+TZy7RDIy+gkw== X-Received: by 2002:a17:902:ed13:b029:d0:89f1:9e32 with SMTP id b19-20020a170902ed13b02900d089f19e32mr1798757pld.14.1599129646795; Thu, 03 Sep 2020 03:40:46 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 03/12] hw/riscv: Move sifive_u_otp model to hw/misc Date: Thu, 3 Sep 2020 18:40:14 +0800 Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::444; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x444.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_u_otp model to hw/misc directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/{riscv =3D> misc}/sifive_u_otp.h | 0 include/hw/riscv/sifive_u.h | 2 +- hw/{riscv =3D> misc}/sifive_u_otp.c | 2 +- hw/misc/Kconfig | 3 +++ hw/misc/meson.build | 1 + hw/riscv/Kconfig | 1 + hw/riscv/meson.build | 1 - 7 files changed, 7 insertions(+), 3 deletions(-) rename include/hw/{riscv =3D> misc}/sifive_u_otp.h (100%) rename hw/{riscv =3D> misc}/sifive_u_otp.c (99%) diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/misc/sifive_u_otp= .h similarity index 100% rename from include/hw/riscv/sifive_u_otp.h rename to include/hw/misc/sifive_u_otp.h diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index cbeb228..936a3bd 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -24,7 +24,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" -#include "hw/riscv/sifive_u_otp.h" +#include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" =20 #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" diff --git a/hw/riscv/sifive_u_otp.c b/hw/misc/sifive_u_otp.c similarity index 99% rename from hw/riscv/sifive_u_otp.c rename to hw/misc/sifive_u_otp.c index f6ecbaa..c2f3c8e 100644 --- a/hw/riscv/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -23,7 +23,7 @@ #include "hw/sysbus.h" #include "qemu/log.h" #include "qemu/module.h" -#include "hw/riscv/sifive_u_otp.h" +#include "hw/misc/sifive_u_otp.h" =20 static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int = size) { diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index 65f3fdd..fa3d0f4 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -137,6 +137,9 @@ config AVR_POWER config SIFIVE_E_PRCI bool =20 +config SIFIVE_U_OTP + bool + config SIFIVE_U_PRCI bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 9e9550e..018a88c 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -23,6 +23,7 @@ softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mo= s6522.c')) =20 # RISC-V devices softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci= .c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c= ')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci= .c')) =20 # PKUnity SoC devices diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 109364b..76eaf77 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -24,6 +24,7 @@ config SIFIVE_U select HART select SIFIVE select SIFIVE_PDMA + select SIFIVE_U_OTP select SIFIVE_U_PRCI select UNIMP =20 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index e6c8af0..2ba4757 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -11,7 +11,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifiv= e_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_gpio model to hw/gpio directory. Note this also removes the trace-events in the hw/riscv directory, since gpio is the only supported trace target in that directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/trace.h | 1 - include/hw/{riscv =3D> gpio}/sifive_gpio.h | 0 include/hw/riscv/sifive_e.h | 2 +- include/hw/riscv/sifive_u.h | 2 +- hw/{riscv =3D> gpio}/sifive_gpio.c | 2 +- hw/gpio/Kconfig | 3 +++ hw/gpio/meson.build | 1 + hw/gpio/trace-events | 6 ++++++ hw/riscv/Kconfig | 2 ++ hw/riscv/meson.build | 1 - hw/riscv/trace-events | 7 ------- meson.build | 1 - 12 files changed, 15 insertions(+), 13 deletions(-) delete mode 100644 hw/riscv/trace.h rename include/hw/{riscv =3D> gpio}/sifive_gpio.h (100%) rename hw/{riscv =3D> gpio}/sifive_gpio.c (99%) delete mode 100644 hw/riscv/trace-events diff --git a/hw/riscv/trace.h b/hw/riscv/trace.h deleted file mode 100644 index 8c0e3ca..0000000 --- a/hw/riscv/trace.h +++ /dev/null @@ -1 +0,0 @@ -#include "trace/trace-hw_riscv.h" diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/gpio/sifive_gpio.h similarity index 100% rename from include/hw/riscv/sifive_gpio.h rename to include/hw/gpio/sifive_gpio.h diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 6374141..b140084 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -21,7 +21,7 @@ =20 #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" -#include "hw/riscv/sifive_gpio.h" +#include "hw/gpio/sifive_gpio.h" =20 #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" #define RISCV_E_SOC(obj) \ diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 936a3bd..fe5c580 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -23,7 +23,7 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" -#include "hw/riscv/sifive_gpio.h" +#include "hw/gpio/sifive_gpio.h" #include "hw/misc/sifive_u_otp.h" #include "hw/misc/sifive_u_prci.h" =20 diff --git a/hw/riscv/sifive_gpio.c b/hw/gpio/sifive_gpio.c similarity index 99% rename from hw/riscv/sifive_gpio.c rename to hw/gpio/sifive_gpio.c index aac6b44..78bf29e 100644 --- a/hw/riscv/sifive_gpio.c +++ b/hw/gpio/sifive_gpio.c @@ -15,7 +15,7 @@ #include "qemu/log.h" #include "hw/irq.h" #include "hw/qdev-properties.h" -#include "hw/riscv/sifive_gpio.h" +#include "hw/gpio/sifive_gpio.h" #include "migration/vmstate.h" #include "trace.h" =20 diff --git a/hw/gpio/Kconfig b/hw/gpio/Kconfig index 9227cb5..b6fdaa2 100644 --- a/hw/gpio/Kconfig +++ b/hw/gpio/Kconfig @@ -7,3 +7,6 @@ config PL061 =20 config GPIO_KEY bool + +config SIFIVE_GPIO + bool diff --git a/hw/gpio/meson.build b/hw/gpio/meson.build index 6bcdfa6..86cae9a 100644 --- a/hw/gpio/meson.build +++ b/hw/gpio/meson.build @@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_NRF51_SOC', if_true: files('= nrf51_gpio.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_gpio.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_gpio.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_gpio.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_GPIO', if_true: files('sifive_gpio.c')) diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index c1271fd..6e3f048 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -5,3 +5,9 @@ nrf51_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" P= RIx64 " value 0x%" PR nrf51_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " va= lue 0x%" PRIx64 nrf51_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PRI= i64 nrf51_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64 = " value %" PRIi64 + +# sifive_gpio.c +sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 +sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " v= alue 0x%" PRIx64 +sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PR= Ii64 +sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64= " value %" PRIi64 diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 76eaf77..5a8335b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E bool select HART select SIFIVE + select SIFIVE_GPIO select SIFIVE_E_PRCI select UNIMP =20 @@ -23,6 +24,7 @@ config SIFIVE_U select CADENCE select HART select SIFIVE + select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_U_OTP select SIFIVE_U_PRCI diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 2ba4757..24177ef 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_har= t.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events deleted file mode 100644 index 6d59233..0000000 --- a/hw/riscv/trace-events +++ /dev/null @@ -1,7 +0,0 @@ -# See docs/devel/tracing.txt for syntax documentation. - -# hw/gpio/sifive_gpio.c -sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%" PRIx64 " value = 0x%" PRIx64 -sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " v= alue 0x%" PRIx64 -sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PR= Ii64 -sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64= " value %" PRIi64 diff --git a/meson.build b/meson.build index 1e7aee8..66bbb75 100644 --- a/meson.build +++ b/meson.build @@ -706,7 +706,6 @@ if have_system 'hw/watchdog', 'hw/xen', 'hw/gpio', - 'hw/riscv', 'migration', 'net', 'ui', --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.49 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:40:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=j4GqdI2kBLXYKPblR8CoMHEGSszLQ6puCT6wgQ2l1hA=; b=iQgZSgtZMt6WHTdUdrTs0kHEiMr2H0rirjjxTLP3zCrnVtEz/uJiA/dsQLFPb4uo86 WbvsiifbImPZuiTwD0xxAOtzjjzbeDpVs8K4DlBPYMhawhezqkaO8Db5fldlozhZKUfr 5Y9epTQjUYOvGgDyldmEmYZOKQzWkOo/ciO4Af77zOW3UDdwynyiSFMFdHgPy/TaSLfL hh6cqwfmlu2a/kGFLRmqJ83YwOJ3jWbGXNIIOSV9W39bPP2ZqVsHyhBuoPqPytVo1k/c 89e4fdUtd8rxQdyIjbHFgDXbxd460BGQEqY8sp5kiC0Wx0IXr5GPLBLBOBzTZs7TLZZK 82nA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=j4GqdI2kBLXYKPblR8CoMHEGSszLQ6puCT6wgQ2l1hA=; b=Z/iz439bvKHNTAC4UZBAF3v7jachhCoWqX41ymTbXuYvla2/pjqs4xM4+2YwuDD06M r3GgwabCf10UnR18Cw8GbdlZm7SSgkWnmKPw54WYDoEE+jgxt4WlzfBEpL/08QYLHKPi JDkPfIN1PaX0UCrR8QjC0BbDSnBpQrhcALknnc8KVcYo7FWSyHlXVOsWm5eNkhjnBNsa f291y6U4T3/mV6qT7H8Fz+Cf92B+loXPSRNvFG8ISSg72Ytp8GbRaLOYBJMtoehDSYhq FVDQjAzyG0uFsgcQMpghm0j36ZakWFnzW74odis4c+nt8btLHmyFZcbrxnMLz/lfonae EqDw== X-Gm-Message-State: AOAM532NFW3lEOdNXCvhc1ed6SflaGBPHJXe5uxAN6Qo6bhrvvTzY6B1 dWyGzA33jYy88awPnr5yUJ8= X-Google-Smtp-Source: ABdhPJx0qQc8YkMdin7U+Zm5krgiflC7Jwr0wF2hro7MgdgOhr0tXlAUCrFYHb/5VT6uT6wMlTH7Zw== X-Received: by 2002:a17:902:b58a:: with SMTP id a10mr3272865pls.269.1599129651981; Thu, 03 Sep 2020 03:40:51 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 05/12] hw/riscv: Move sifive_clint model to hw/intc Date: Thu, 3 Sep 2020 18:40:16 +0800 Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::543; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x543.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_clint model to hw/intc directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/{riscv =3D> intc}/sifive_clint.h | 0 hw/{riscv =3D> intc}/sifive_clint.c | 2 +- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/spike.c | 2 +- hw/riscv/virt.c | 2 +- hw/intc/Kconfig | 3 +++ hw/intc/meson.build | 1 + hw/riscv/Kconfig | 5 +++++ hw/riscv/meson.build | 1 - 11 files changed, 15 insertions(+), 7 deletions(-) rename include/hw/{riscv =3D> intc}/sifive_clint.h (100%) rename hw/{riscv =3D> intc}/sifive_clint.c (99%) diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/intc/sifive_clint= .h similarity index 100% rename from include/hw/riscv/sifive_clint.h rename to include/hw/intc/sifive_clint.h diff --git a/hw/riscv/sifive_clint.c b/hw/intc/sifive_clint.c similarity index 99% rename from hw/riscv/sifive_clint.c rename to hw/intc/sifive_clint.c index fa1ddf2..0f41e5e 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/intc/sifive_clint.c @@ -26,7 +26,7 @@ #include "hw/sysbus.h" #include "target/riscv/cpu.h" #include "hw/qdev-properties.h" -#include "hw/riscv/sifive_clint.h" +#include "hw/intc/sifive_clint.h" #include "qemu/timer.h" =20 static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index da6bd29..131eea1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -48,9 +48,9 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/microchip_pfsoc.h" +#include "hw/intc/sifive_clint.h" #include "sysemu/sysemu.h" =20 /* diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 7f43ed9..3bdb16e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -40,10 +40,10 @@ #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" -#include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/intc/sifive_clint.h" #include "hw/misc/sifive_e_prci.h" #include "chardev/char.h" #include "sysemu/arch_init.h" diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7997537..7187d1a 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -47,10 +47,10 @@ #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" -#include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/intc/sifive_clint.h" #include "chardev/char.h" #include "net/eth.h" #include "sysemu/arch_init.h" diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index b54a396..59d9d87 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -33,10 +33,10 @@ #include "target/riscv/cpu.h" #include "hw/riscv/riscv_htif.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_clint.h" #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/intc/sifive_clint.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c67a910..bce2020 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -31,11 +31,11 @@ #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" -#include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/intc/sifive_clint.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 2ae1e89..f499d0f 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -67,3 +67,6 @@ config RX_ICU =20 config LOONGSON_LIOINTC bool + +config SIFIVE_CLINT + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index c16f7f0..1e20daa 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -47,6 +47,7 @@ specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx= _icu.c')) specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c')) specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kv= m.c')) specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c')) +specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.= c')) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c')) specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 5a8335b..f8bb7e7 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E bool select HART select SIFIVE + select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_E_PRCI select UNIMP @@ -24,6 +25,7 @@ config SIFIVE_U select CADENCE select HART select SIFIVE + select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_U_OTP @@ -35,6 +37,7 @@ config SPIKE select HART select HTIF select SIFIVE + select SIFIVE_CLINT =20 config OPENTITAN bool @@ -54,11 +57,13 @@ config RISCV_VIRT select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 select SIFIVE + select SIFIVE_CLINT =20 config MICROCHIP_PFSOC bool select HART select SIFIVE + select SIFIVE_CLINT select UNIMP select MCHP_PFSOC_MMUART select SIFIVE_PDMA diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 24177ef..ea72178 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.52 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:40:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VVHGFoHo2QIB2V4Pjw5ItIdHbPQBAH4Nd1LvnzoicGs=; b=uNSIF1bknDOHmynukwxVg0CLa2V646H7kuv+P0KrDfJCyQV7PGbxsGuKSmEmj9Iwny Scl+BLL3lzQ6fhiOCoivNPiBvvtEYtA03JufSYrLhekobIBzbAKa/36ZyMlxgT5HXu4I AhZxShxJzDEYn+asBq7QpaV68+/YkiRBiEru4T81KMCn8nOk1/ObHG4yyoQts4Wha+2V nQNwgNYWv8J25VU+GLsaLdIrsVNZBVwZzJ7COODrTJkLOIandvY5SlSzsuwnXWDM++HE laX/UuRjr6rrWl93dNrPY1swZoFiWqiiMddECcS4QyNGSRzrCw2la/OW7RzeJJUnHdmv ugLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VVHGFoHo2QIB2V4Pjw5ItIdHbPQBAH4Nd1LvnzoicGs=; b=Ju4e9t6UWL1Y1Y2DZZaz8lu/zMK/Ttyfp4SuuGTOiyDjQt+83nCL/MMjXZZt0QLMrh +EFRZByAlL2GFptr84yTRMT2+y1wXojFNdlV8BqoMlHBrq2+yufuc3WUne4NwfouL8Kl i7c12wZRCdFaHXzYX9GktH5Hc85mDRsXddBcNnNawz2+BwwFphXCtwGu4MzdUPV8AHF/ KHg0p55QgGYZ8Rcx9WgjX7T9LCOrHG2v2Wy37VQYrPnkevV3yFy2h+H1yMdWrxvsPs12 bRitb7cNuPIhVc4n3OYr/65gonyI1sB4Qj2cuT+hxJmfgxX9SwrF8C5EwyhBED28Fdgb x7RQ== X-Gm-Message-State: AOAM530X+5nSYmmsmUbRMPkCjr9PqzY1G7J3F4fh2l/lTFlypbf6+Wnh oQf9o/Pns4oOQFM7rYkvCGQ= X-Google-Smtp-Source: ABdhPJxuDzzsBymX0tTn0HnhRnbpkqj32RWlamu7y+HhHNERLmVQYWe3YeaHNDt/dW7KHVyfNxT4Rw== X-Received: by 2002:a05:6a00:811:: with SMTP id m17mr3216044pfk.20.1599129654540; Thu, 03 Sep 2020 03:40:54 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 06/12] hw/riscv: Move sifive_plic model to hw/intc Date: Thu, 3 Sep 2020 18:40:17 +0800 Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::541; envelope-from=bmeng.cn@gmail.com; helo=mail-pg1-x541.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_plic model to hw/intc directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- {include/hw/riscv =3D> hw/intc}/sifive_plic.h | 0 hw/{riscv =3D> intc}/sifive_plic.c | 2 +- hw/riscv/microchip_pfsoc.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/riscv/virt.c | 2 +- hw/intc/Kconfig | 3 +++ hw/intc/meson.build | 1 + hw/riscv/Kconfig | 5 +++++ hw/riscv/meson.build | 1 - 10 files changed, 14 insertions(+), 6 deletions(-) rename {include/hw/riscv =3D> hw/intc}/sifive_plic.h (100%) rename hw/{riscv =3D> intc}/sifive_plic.c (99%) diff --git a/include/hw/riscv/sifive_plic.h b/hw/intc/sifive_plic.h similarity index 100% rename from include/hw/riscv/sifive_plic.h rename to hw/intc/sifive_plic.h diff --git a/hw/riscv/sifive_plic.c b/hw/intc/sifive_plic.c similarity index 99% rename from hw/riscv/sifive_plic.c rename to hw/intc/sifive_plic.c index 11ef147..af611f8 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -27,9 +27,9 @@ #include "hw/pci/msi.h" #include "hw/boards.h" #include "hw/qdev-properties.h" +#include "hw/intc/sifive_plic.h" #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" -#include "hw/riscv/sifive_plic.h" =20 #define RISCV_DEBUG_PLIC 0 =20 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 131eea1..4627179 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -48,9 +48,9 @@ #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_plic.h" #include "hw/riscv/microchip_pfsoc.h" #include "hw/intc/sifive_clint.h" +#include "hw/intc/sifive_plic.h" #include "sysemu/sysemu.h" =20 /* diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 3bdb16e..0ddcf15 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -39,11 +39,11 @@ #include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" #include "hw/intc/sifive_clint.h" +#include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" #include "chardev/char.h" #include "sysemu/arch_init.h" diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7187d1a..faca2e8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -46,11 +46,11 @@ #include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" #include "hw/intc/sifive_clint.h" +#include "hw/intc/sifive_plic.h" #include "chardev/char.h" #include "net/eth.h" #include "sysemu/arch_init.h" diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bce2020..0caab8e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,12 +30,12 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/intc/sifive_clint.h" +#include "hw/intc/sifive_plic.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index f499d0f..d079540 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -70,3 +70,6 @@ config LOONGSON_LIOINTC =20 config SIFIVE_CLINT bool + +config SIFIVE_PLIC + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 1e20daa..3f82cc2 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -48,6 +48,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files(= 's390_flic.c')) specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: files('s390_flic_kv= m.c')) specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c')) specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.= c')) +specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'= )) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c')) specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index f8bb7e7..23b7027 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -17,6 +17,7 @@ config SIFIVE_E select SIFIVE select SIFIVE_CLINT select SIFIVE_GPIO + select SIFIVE_PLIC select SIFIVE_E_PRCI select UNIMP =20 @@ -28,6 +29,7 @@ config SIFIVE_U select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_PDMA + select SIFIVE_PLIC select SIFIVE_U_OTP select SIFIVE_U_PRCI select UNIMP @@ -38,6 +40,7 @@ config SPIKE select HTIF select SIFIVE select SIFIVE_CLINT + select SIFIVE_PLIC =20 config OPENTITAN bool @@ -58,6 +61,7 @@ config RISCV_VIRT select PFLASH_CFI01 select SIFIVE select SIFIVE_CLINT + select SIFIVE_PLIC =20 config MICROCHIP_PFSOC bool @@ -67,4 +71,5 @@ config MICROCHIP_PFSOC select UNIMP select MCHP_PFSOC_MMUART select SIFIVE_PDMA + select SIFIVE_PLIC select CADENCE_SDHCI diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index ea72178..535a142 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.54 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:40:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Bjt7/k4o145ugR9pJpMn6OkaWclyCj0SqUQ2K7UT0nQ=; b=YVTsZYB/NMVPkXRt7cS2WKL6n4Rgb9/27Tk7hkvn/mAX+6xldpqdqmc2Xj9pwfC6Yr FijeO7hfufcbkYNmSe5mehvsKmlTtm3DhPgF/brh2prk58Pb/jQ9g0aZMQFR7FqxrqYf 2oAdhMQnheJ2IfgSd5+7C2l4AGZcXCdHGtnNNhNWf6q2pahYEDtwiC/JVUXfSIIqJTXC SOg7nnblPCGdFSrIz/SeAP2ZKxsEs5XTYEYTTLIFGD2whEN59UUVVpM7WANODBJEDzzS uSafn/rnm6ZIfgbqxHUkRozF/JcKW1vPp5Id4zvqqAb2E0AKO7x4vQR6EGRyRyIOoT4n owWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Bjt7/k4o145ugR9pJpMn6OkaWclyCj0SqUQ2K7UT0nQ=; b=aM1lHLdJWyKo2n8HAk5U/0Yc2BOHHmc0I8fnyywajY1e8noACO0RMp4b7DuQLtlgJZ CWbc/3GyHYI6a2pvZVr4p02au8bk8vu/7mmqb2UEn6DcMLFnlFfIrv2VnWr/A+8ZO0dH DrB7ESCP4QGnrGNR5LDeBi1R7VdQWWbkX4Z6WBqWpwmCoM5gN7NizKiO87wa2BlJLNub EuwwtTclsKnul4u7cJ//GKPjAWdX2fDQOgMrZZnJOTLkD/BnY7fBcD+fJDa5CpnXoruP JVyvWvgUqLmvNbmltchD8oWmUJXzUmdi893X5VBmM4PGf3tO+1qpZMWirFUd8CCZ1Njb wyog== X-Gm-Message-State: AOAM532hQutQ6l9dPI4FVl4593RoYUC4OZGfOxTZ1RjcMzCH6JtUq2f0 7IIjFZW28xtZGS0RXMK3wM0= X-Google-Smtp-Source: ABdhPJz2S91eHhxsMfQJPN/k1KyLQyrMgaQ0UiVBcB47x2PGR9jxPtc1g0Q5I45ytBb9iSlMytuZqg== X-Received: by 2002:a17:90b:4c03:: with SMTP id na3mr2711748pjb.29.1599129656965; Thu, 03 Sep 2020 03:40:56 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 07/12] hw/riscv: Move riscv_htif model to hw/char Date: Thu, 3 Sep 2020 18:40:18 +0800 Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move riscv_htif model to hw/char directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/{riscv =3D> char}/riscv_htif.h | 0 hw/{riscv =3D> char}/riscv_htif.c | 2 +- hw/riscv/spike.c | 2 +- hw/char/Kconfig | 3 +++ hw/char/meson.build | 1 + hw/riscv/Kconfig | 3 --- hw/riscv/meson.build | 1 - 7 files changed, 6 insertions(+), 6 deletions(-) rename include/hw/{riscv =3D> char}/riscv_htif.h (100%) rename hw/{riscv =3D> char}/riscv_htif.c (99%) diff --git a/include/hw/riscv/riscv_htif.h b/include/hw/char/riscv_htif.h similarity index 100% rename from include/hw/riscv/riscv_htif.h rename to include/hw/char/riscv_htif.h diff --git a/hw/riscv/riscv_htif.c b/hw/char/riscv_htif.c similarity index 99% rename from hw/riscv/riscv_htif.c rename to hw/char/riscv_htif.c index ca87a5c..ba1af1c 100644 --- a/hw/riscv/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -24,10 +24,10 @@ #include "qapi/error.h" #include "qemu/log.h" #include "hw/sysbus.h" +#include "hw/char/riscv_htif.h" #include "hw/char/serial.h" #include "chardev/char.h" #include "chardev/char-fe.h" -#include "hw/riscv/riscv_htif.h" #include "qemu/timer.h" #include "qemu/error-report.h" =20 diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 59d9d87..3fd152a 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -31,11 +31,11 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" -#include "hw/riscv/riscv_htif.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/char/riscv_htif.h" #include "hw/intc/sifive_clint.h" #include "chardev/char.h" #include "sysemu/arch_init.h" diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 1d64555..91da92f 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -1,6 +1,9 @@ config ESCC bool =20 +config HTIF + bool + config PARALLEL bool default y diff --git a/hw/char/meson.build b/hw/char/meson.build index ae27932..3db623e 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -34,6 +34,7 @@ softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_ser= ial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_u= sart.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfso= c_mmuart.c')) =20 +specific_ss.add(when: 'CONFIG_HTIF', if_true: files('riscv_htif.c')) specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.= c')) specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c= ')) specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('spapr_vty.c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 23b7027..a0e256c 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -1,6 +1,3 @@ -config HTIF - bool - config HART bool =20 diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 535a142..619bf80 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -8,7 +8,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_= test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) =20 --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.57 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:40:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vLhkFcPRPjbFUkxZmeoav+dAcg9EN0kbL/fECyuDRas=; b=u86Kz2lsxqQ/2Fe2BOBRNaITiyZFjrkREy/6ThAPKzKVFRDKu4R+SfReEY7Kt3xOdg RDzZMFoWsAWi8LNp4hrqHYTDcGzLhhZhNbWZTlTntJBl+kmGUkxwrSMH3VTGAz5JeCxW vedtjtkEPttKP/iIgGsPkO4lXhljprZCGYQjHmC0pvQ+WRtgoAsxEN2t2hIq6i7AD0he +U+sy4Xkmx9/qPhu8ix94OR6kEAbOMsJkcDrRh4Wirzq3XYH+wGo83cauYK9YtoKFS9k 56VPm3ncXY/6qnMwOAnRsKOkn+5newtdOW8TTj1rgNAe4+GYHKBoLhAKlAiu3d4iuX3C 9jJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vLhkFcPRPjbFUkxZmeoav+dAcg9EN0kbL/fECyuDRas=; b=NNjP+BmcoyONpZl0lw0iiOC/UCilTtXSf1L3t8ZlHb51kT1aLpMdx9uaSGUCpndQnN JFj6/aXMXSQWX0ge8rwq7fcNkyn25nk9zHySEBHr6LLxRRRwy+d1J+KU0J3Tn1PcYVCv MOsRsea9JX5eQrAvuT9UX/930ybZMt6FdkI+rL4rwBcuvIDYxkcDuGNGzemdwaNqr3fj tX4xpG5qj6RLiQPf7d4hWZ/jdRjwj/GaKduU81XO9CyJl7owkFEI7Yir3VqH/YdR8osb N8EF1C2Urx5xQCS+lWJEnDIT4JY/aEYvmtN4SyD0Z9cvQSPXbmt/VAiSS1hSUT0xjL8R 4kuw== X-Gm-Message-State: AOAM533KvAan5BzPgrJCUZVqz3PNtTemTCM0wAmmY6dicGaUpsfRTeSd GC9rZdYwJviyc+vO8VImDMc= X-Google-Smtp-Source: ABdhPJx42XnrIqMOwceeXVXYoF6MUeWxHWsztreuUZoeDlmSdMu6BsWkALXhyUi/CO3kiio5J5+H5w== X-Received: by 2002:a17:90b:1a89:: with SMTP id ng9mr2637439pjb.202.1599129659384; Thu, 03 Sep 2020 03:40:59 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 08/12] hw/riscv: Move sifive_uart model to hw/char Date: Thu, 3 Sep 2020 18:40:19 +0800 Message-Id: <1599129623-68957-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_uart model to hw/char directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/{riscv =3D> char}/sifive_uart.h | 0 hw/{riscv =3D> char}/sifive_uart.c | 2 +- hw/riscv/sifive_e.c | 2 +- hw/riscv/sifive_u.c | 2 +- hw/char/Kconfig | 3 +++ hw/char/meson.build | 1 + hw/riscv/Kconfig | 2 ++ hw/riscv/meson.build | 1 - 8 files changed, 9 insertions(+), 4 deletions(-) rename include/hw/{riscv =3D> char}/sifive_uart.h (100%) rename hw/{riscv =3D> char}/sifive_uart.c (99%) diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/char/sifive_uart.h similarity index 100% rename from include/hw/riscv/sifive_uart.h rename to include/hw/char/sifive_uart.h diff --git a/hw/riscv/sifive_uart.c b/hw/char/sifive_uart.c similarity index 99% rename from hw/riscv/sifive_uart.c rename to hw/char/sifive_uart.c index 9350482..3a00ba7 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -24,7 +24,7 @@ #include "chardev/char-fe.h" #include "hw/hw.h" #include "hw/irq.h" -#include "hw/riscv/sifive_uart.h" +#include "hw/char/sifive_uart.h" =20 /* * Not yet implemented: diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 0ddcf15..40bbf53 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -39,9 +39,9 @@ #include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" #include "hw/riscv/boot.h" +#include "hw/char/sifive_uart.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_e_prci.h" diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index faca2e8..4f12a93 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -46,9 +46,9 @@ #include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" +#include "hw/char/sifive_uart.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" #include "chardev/char.h" diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 91da92f..939bc44 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -58,3 +58,6 @@ config AVR_USART =20 config MCHP_PFSOC_MMUART bool + +config SIFIVE_UART + bool diff --git a/hw/char/meson.build b/hw/char/meson.build index 3db623e..196ac91 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -30,6 +30,7 @@ softmmu_ss.add(when: 'CONFIG_EXYNOS4', if_true: files('ex= ynos4210_uart.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_uart.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_aux.c')) softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_UART', if_true: files('sifive_uart.c')) softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_u= sart.c')) softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfso= c_mmuart.c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a0e256c..a046157 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_PLIC + select SIFIVE_UART select SIFIVE_E_PRCI select UNIMP =20 @@ -27,6 +28,7 @@ config SIFIVE_U select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_PLIC + select SIFIVE_UART select SIFIVE_U_OTP select SIFIVE_U_PRCI select UNIMP diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 619bf80..da32148 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -5,7 +5,6 @@ riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_har= t.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.40.59 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:41:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=tu0atc0QVqkObDFB/8D8Fwge3UArGpjBnQ7mD77F3Sk=; b=rQbPvDP73DP6TA74RcYFhjSNHYq5tejkM1mDO9DgyxX1s9R6Sqb5FXFz1JIlEiRdrv dgv2ceU5kvT/pNMbqLmhLJljZjhSZIzldKcNoa5eHbklqdU4iV9+E+8EeGhC3GJDOiQb 5eQzy8taV49NWUlkLVsyIm1+n76vnPkTjLCmBYZbCJjrlFIUki1D28mqQzzDXJV4t48S bo1bQErZm4bW8AA6l9d/kHQypM8Yj9i/oK8dFAFxDeZH47ZapaO0z+ZZJpoT5lHOjGMY SVEwKayJJYOnj6zuj5CBnTQvqO0TVYPCmfyJ2SHn9roh3nZ0+TD0b7HwL8SxGsHGTadw giNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=tu0atc0QVqkObDFB/8D8Fwge3UArGpjBnQ7mD77F3Sk=; b=McP7vjYpulO66NjQLAO/XAIaVJ3AEJfX+ZbskvF6Lz9yYUO3DcjDkyeVu+Vij89x/e fhmT98H3cTVaDBP6PQYcPuKgqRFQwmo9YPqohoCyRCvGAOxHPiy7NqsUUsCNuEyKcR5+ vO4hHqzpu7PV4UdIO/1zGV6HzLa9dD0tXGfXGubEo+3ZGQGzvna4ZEIjoNc+8URUP+0V 1VgUldkhPL6uoTcbL/ZZTaGrRgcrL8pv2RpVoViyHGYsMd+TY+3yvx+qB3e6FGi4Aodu eFnKi3SuPncDEmRU/VDjHV0+3nK9O7M6T5uyTjeLZlTj9glqPCxmoMlxGL5rAsGF4Rsy 1LQg== X-Gm-Message-State: AOAM532jAWM4mCcEauxOFLIV6LTcB6+uhgyGi+M6VztoRY3CQUDte3B+ KFep08YDPmqlpvBPKpJ1djk= X-Google-Smtp-Source: ABdhPJw9vSjbXYlp/n+brmxuqm3nAWOXKXarotRIu7PzH7pnZbMEOlNKLBHeqcVBuHTS1iPbWdBfiQ== X-Received: by 2002:a17:90a:ed8e:: with SMTP id k14mr2745994pjy.178.1599129661654; Thu, 03 Sep 2020 03:41:01 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 09/12] hw/riscv: Move sifive_test model to hw/misc Date: Thu, 3 Sep 2020 18:40:20 +0800 Message-Id: <1599129623-68957-10-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1043; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1043.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an effort to clean up the hw/riscv directory. Ideally it should only contain the RISC-V SoC / machine codes plus generic codes. Let's move sifive_test model to hw/misc directory. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- include/hw/{riscv =3D> misc}/sifive_test.h | 0 hw/{riscv =3D> misc}/sifive_test.c | 2 +- hw/riscv/virt.c | 2 +- hw/misc/Kconfig | 3 +++ hw/misc/meson.build | 1 + hw/riscv/Kconfig | 1 + hw/riscv/meson.build | 1 - 7 files changed, 7 insertions(+), 3 deletions(-) rename include/hw/{riscv =3D> misc}/sifive_test.h (100%) rename hw/{riscv =3D> misc}/sifive_test.c (98%) diff --git a/include/hw/riscv/sifive_test.h b/include/hw/misc/sifive_test.h similarity index 100% rename from include/hw/riscv/sifive_test.h rename to include/hw/misc/sifive_test.h diff --git a/hw/riscv/sifive_test.c b/hw/misc/sifive_test.c similarity index 98% rename from hw/riscv/sifive_test.c rename to hw/misc/sifive_test.c index 0c78fb2..45d9399 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/misc/sifive_test.c @@ -25,7 +25,7 @@ #include "qemu/module.h" #include "sysemu/runstate.h" #include "hw/hw.h" -#include "hw/riscv/sifive_test.h" +#include "hw/misc/sifive_test.h" =20 static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int s= ize) { diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 0caab8e..41bd2f3 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,12 +30,12 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/intc/sifive_clint.h" #include "hw/intc/sifive_plic.h" +#include "hw/misc/sifive_test.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index fa3d0f4..3185456 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -134,6 +134,9 @@ config MAC_VIA config AVR_POWER bool =20 +config SIFIVE_TEST + bool + config SIFIVE_E_PRCI bool =20 diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 018a88c..bd24132 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -22,6 +22,7 @@ softmmu_ss.add(when: 'CONFIG_ARM11SCU', if_true: files('a= rm11scu.c')) softmmu_ss.add(when: 'CONFIG_MOS6522', if_true: files('mos6522.c')) =20 # RISC-V devices +softmmu_ss.add(when: 'CONFIG_SIFIVE_TEST', if_true: files('sifive_test.c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_E_PRCI', if_true: files('sifive_e_prci= .c')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_OTP', if_true: files('sifive_u_otp.c= ')) softmmu_ss.add(when: 'CONFIG_SIFIVE_U_PRCI', if_true: files('sifive_u_prci= .c')) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index a046157..8e07100 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -61,6 +61,7 @@ config RISCV_VIRT select SIFIVE select SIFIVE_CLINT select SIFIVE_PLIC + select SIFIVE_TEST =20 config MICROCHIP_PFSOC bool diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index da32148..3cf9380 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -4,7 +4,6 @@ riscv_ss.add(files('numa.c')) riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.41.02 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:41:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=heOhgRObAJzJHkeWliYEUi9AemgHGjnTQIUCrihpc0U=; b=dlnmce6fUvDYynwH9IGFFnqlQ8NQzgnbQUwmnJ9oTprSXlQeLXG/blQ+Jcz+a6ym3M PREni1QjXSC8FUL1GNH3sJuiiOFhgxa57V/L46itz8Nu/my8XHB5KGjzcS+P+KinkOsM qNLe7+PqZEtXLK1CEhLNFb0oxl4ugDoLIz0e6DZaJV3Yr/Dq9jojYmEkx5yBburyjqxZ OaVBJC6BgN3wteqJv/s2gMY1dint8fArXpQJYtfiJgJK+RGXIizQCNIIqYaSLIYjaZbv cSX174hE6jcx8yJvH5qNpo+p+eNw6fpPTZ4rUbU+kVUVJ7iezD1OhuEoYSNeuiEyjeb6 jweQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=heOhgRObAJzJHkeWliYEUi9AemgHGjnTQIUCrihpc0U=; b=aUmH7lsnR42p39jvdoruwWykTiWKB8JPs84s8A2rUjGCzcMmaSQozWIRA2c7kz5CX4 g1SYSHRXlhTtZ8cHZKjULcFrAcOr1pylLRHlb4f/2px7gthy1400joMyzt6bHXCcdvWh Q+1PR25AouX3fbYTpfbowHe0d5NiwqD+2SEPXLKTw+OQBACqojF+AshNVRPIXI49WJHt eE2zB8F57uIH8PFWOdDKJHfw3JlMLeshKIvE37qDOmXqiEo8FhlLK828b1yziJbbBEvz jWxomJ/z/MoRKuaqPAAlr21mS/5NwiRslmU9yf+6iWNSZvBqkHOnqzm62OaADsBa+ZJG xHtA== X-Gm-Message-State: AOAM530TFiH6LSlHoIE0NXUXx5C+P5Y24obRS5MvpLYeK9fm24oBs9in gHSI+0ARz5qtGUWGWumrPZs= X-Google-Smtp-Source: ABdhPJwsSlk7mxvG6EV7dXC/KlWU8CC08fayx64RrfJmwJpdmDNTJ3C7uXohRpqxPnMe+mXaEquciw== X-Received: by 2002:a17:90a:f286:: with SMTP id fs6mr2615596pjb.221.1599129664188; Thu, 03 Sep 2020 03:41:04 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 10/12] hw/riscv: Always build riscv_hart.c Date: Thu, 3 Sep 2020 18:40:21 +0800 Message-Id: <1599129623-68957-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Every RISC-V machine needs riscv_hart hence there is no need to have a dedicated Kconfig option for it. Drop the Kconfig option and always build riscv_hart.c. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/Kconfig | 9 --------- hw/riscv/meson.build | 2 +- 2 files changed, 1 insertion(+), 10 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 8e07100..7d017bc 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -1,6 +1,3 @@ -config HART - bool - config IBEX bool =20 @@ -10,7 +7,6 @@ config SIFIVE =20 config SIFIVE_E bool - select HART select SIFIVE select SIFIVE_CLINT select SIFIVE_GPIO @@ -22,7 +18,6 @@ config SIFIVE_E config SIFIVE_U bool select CADENCE - select HART select SIFIVE select SIFIVE_CLINT select SIFIVE_GPIO @@ -35,7 +30,6 @@ config SIFIVE_U =20 config SPIKE bool - select HART select HTIF select SIFIVE select SIFIVE_CLINT @@ -44,7 +38,6 @@ config SPIKE config OPENTITAN bool select IBEX - select HART select UNIMP =20 config RISCV_VIRT @@ -52,7 +45,6 @@ config RISCV_VIRT imply PCI_DEVICES imply TEST_DEVICES select PCI - select HART select SERIAL select GOLDFISH_RTC select VIRTIO_MMIO @@ -65,7 +57,6 @@ config RISCV_VIRT =20 config MICROCHIP_PFSOC bool - select HART select SIFIVE select SIFIVE_CLINT select UNIMP diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 3cf9380..dbedf9b 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -1,7 +1,7 @@ riscv_ss =3D ss.source_set() riscv_ss.add(files('boot.c')) riscv_ss.add(files('numa.c')) -riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) +riscv_ss.add(files('riscv_hart.c')) riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1599130243; cv=none; d=zohomail.com; s=zohoarc; b=cQq++NzO6yRL+/HpfmEe86ROb2AKNEuz8dV8KohI4PLixgBOw9MOZTlHzKkvfaYBlmHrsCtqVHYyHGGrVOdX9M0a6rIB+noTvp3aTMxR+Rd3Oz9Po74ZzMTDOpOqsCbLj2QWlKJyykavhOxm3E7plf3Vrsht/s0jwHemxWzvtbg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599130243; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=E0+89gACSq0DbIpTAUJ5ClPjbEgWU1Xtql9kIfdqQFA=; b=eC7VVJfwjqfWwvDMt/KSp/luAadHzSZWBNGGvOOuRvLLFD4CwUsZ4gvwSwoNnpR932vPKwa0YWyETAcWyHSycRgSw+7VrEMKQprlMvvA0woFLfa2hw9rjQWct/9onxgyLZgAKj2PfXD3DW31BOffxqN9o2sI8hTfo1/N0dHNL/I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1599130243268339.00416756512334; Thu, 3 Sep 2020 03:50:43 -0700 (PDT) Received: from localhost ([::1]:50426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kDmpG-0005Hj-1k for importer@patchew.org; Thu, 03 Sep 2020 06:50:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kDmg2-0006Nh-64; Thu, 03 Sep 2020 06:41:10 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:53984) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kDmg0-0002II-8L; Thu, 03 Sep 2020 06:41:09 -0400 Received: by mail-pj1-x1042.google.com with SMTP id k15so1323560pji.3; Thu, 03 Sep 2020 03:41:07 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id b18sm2137098pjq.3.2020.09.03.03.41.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 03 Sep 2020 03:41:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=E0+89gACSq0DbIpTAUJ5ClPjbEgWU1Xtql9kIfdqQFA=; b=TodLDyBq7AQM1agY4N8wJxyeZfI2zXbHlofyEaBnej4ePqETTDA7X16Vdd51CjOv/U mrTdRSNxiIL07iuriwJpH/0RKVPQyCFGIdrqwE3d/NJBTWuXdww6FSA2q3K6M2oPihej zAo5fA/pEyPXbMl579SFjigSc4d6UyuCvhICH2DmAAxH7Iil5uHUljM/wD2IPTVAQ5bI BnbPMEgMqNRtfLYbcSkG3WEphK9HAaccEkl79JJJmC9Uwe0rdH+xW86mSAcYDT5DOkYF istMn0Jpq8Hr+dI/XrSIcRzO2GDDyXhA4wr7txTMZviw5vQ33xTQdNdRJzWAfyU5mEe2 Hrjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=E0+89gACSq0DbIpTAUJ5ClPjbEgWU1Xtql9kIfdqQFA=; b=R4PbBFdkkahlyMW0/obCoaDnk/lYWp77imm9S/5rul+z2w5XMiWHmpLFiSNSJCnCRU RCOwKl2/JvVk5Zc0uzIzQ6I0CV7gHKUePPcxpbGKuaWKqg0+5XJC3Hl4i/B8shxNT5FM vBCxEyrQHtva/2lfA2Je5UEqHqNTPM5eZgrPQ+nwQMred6ymtDYeEbA8LzWAYteGOXyg QYrEFmAdjUDxS0bCrjB8/zkf5pFg9Vim1Xs3g34bn4YK2jd1LsLbcgAt+uSqeY9WDioC n38SSZjA5OIOnx3JrjEUo67SjUm7Mp6vdwQW6OzFhsmxlbFP0d5OJMYSDQMX861YpRE1 HHaA== X-Gm-Message-State: AOAM532XNdABv0JH7C0MnIYyt3A3dral5957gBP44ovZ/X1Lm+3Mygbo qPns432kQhYCLJ1G9wL4Y1g= X-Google-Smtp-Source: ABdhPJyhaBTAgmaRSCdj8PFJlo71b27Q+tm/w/IMkFpdm4fcn+8HYciACDSTgIWfcLO8q48j8R2PWA== X-Received: by 2002:a17:90b:30cd:: with SMTP id hi13mr2732157pjb.82.1599129666710; Thu, 03 Sep 2020 03:41:06 -0700 (PDT) From: Bin Meng To: Alistair Francis , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH 11/12] hw/riscv: Drop CONFIG_SIFIVE Date: Thu, 3 Sep 2020 18:40:22 +0800 Message-Id: <1599129623-68957-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> References: <1599129623-68957-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=bmeng.cn@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng The name SIFIVE is too vague to convey the required component of MSI_NONBROKEN. Let's drop the option, and select MSI_NONBROKEN in each machine instead. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/Kconfig | 14 +++++--------- 1 file changed, 5 insertions(+), 9 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 7d017bc..e152fdc 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -1,13 +1,9 @@ config IBEX bool =20 -config SIFIVE - bool - select MSI_NONBROKEN - config SIFIVE_E bool - select SIFIVE + select MSI_NONBROKEN select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_PLIC @@ -18,7 +14,7 @@ config SIFIVE_E config SIFIVE_U bool select CADENCE - select SIFIVE + select MSI_NONBROKEN select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_PDMA @@ -31,7 +27,7 @@ config SIFIVE_U config SPIKE bool select HTIF - select SIFIVE + select MSI_NONBROKEN select SIFIVE_CLINT select SIFIVE_PLIC =20 @@ -44,20 +40,20 @@ config RISCV_VIRT bool imply PCI_DEVICES imply TEST_DEVICES + select MSI_NONBROKEN select PCI select SERIAL select GOLDFISH_RTC select VIRTIO_MMIO select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 - select SIFIVE select SIFIVE_CLINT select SIFIVE_PLIC select SIFIVE_TEST =20 config MICROCHIP_PFSOC bool - select SIFIVE + select MSI_NONBROKEN select SIFIVE_CLINT select UNIMP select MCHP_PFSOC_MMUART --=20 2.7.4 From nobody Sun Nov 16 05:37:13 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1599129844; cv=none; d=zohomail.com; s=zohoarc; b=VRHiJSH25QXragWv3lRvPZaNeSm9aI6iBqFOMRckBmmzcsyZfv38z9w13kpNhl56wBdsMYQDvoeEJrWhU4vuMZRPCfEXtmI/JBnfhoVNI8Aaud8P0Iw23kFfKWgy/pafIZFfOddjFxNxvwK/epIQOzaPJFWQp9isvHJ2DxjlWqs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1599129844; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=BAoSl8WTSMSqpJyU/pVpg7WKQMPGwvLFY7+i9UUWwnw=; b=CBd/UIl7s5XYnNqhmmsTaY4wD6ompf9r9fyQfe9p3JG4Va3WWDOwbe92szYLttsCpf/LVoyqx7g6Ctbdy1BuDYUa9Aci4gT25dm72IciUWjzBHCU8rAtuYLybcUvbvRFKslqGN3kinE9cMQ56NXKRrL6fnDpVEkbrHZgSE+OPVA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1599129844607803.818672909883; Thu, 3 Sep 2020 03:44:04 -0700 (PDT) Received: from localhost ([::1]:52668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kDmip-00030a-OB for importer@patchew.org; Thu, 03 Sep 2020 06:44:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55364) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kDmg4-0006UI-K6; Thu, 03 Sep 2020 06:41:12 -0400 Received: from mail-pj1-x1043.google.com ([2607:f8b0:4864:20::1043]:52938) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kDmg2-0002Ij-N8; Thu, 03 Sep 2020 06:41:12 -0400 Received: by mail-pj1-x1043.google.com with SMTP id o16so1325376pjr.2; Thu, 03 Sep 2020 03:41:09 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the Kconfig file is in disorder. Let's sort the options. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/Kconfig | 58 ++++++++++++++++++++++++++++------------------------= ---- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index e152fdc..2df978f 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -1,36 +1,16 @@ config IBEX bool =20 -config SIFIVE_E - bool - select MSI_NONBROKEN - select SIFIVE_CLINT - select SIFIVE_GPIO - select SIFIVE_PLIC - select SIFIVE_UART - select SIFIVE_E_PRCI - select UNIMP - -config SIFIVE_U +config MICROCHIP_PFSOC bool - select CADENCE + select CADENCE_SDHCI + select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT - select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_PLIC - select SIFIVE_UART - select SIFIVE_U_OTP - select SIFIVE_U_PRCI select UNIMP =20 -config SPIKE - bool - select HTIF - select MSI_NONBROKEN - select SIFIVE_CLINT - select SIFIVE_PLIC - config OPENTITAN bool select IBEX @@ -40,23 +20,43 @@ config RISCV_VIRT bool imply PCI_DEVICES imply TEST_DEVICES + select GOLDFISH_RTC select MSI_NONBROKEN select PCI - select SERIAL - select GOLDFISH_RTC - select VIRTIO_MMIO select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 + select SERIAL select SIFIVE_CLINT select SIFIVE_PLIC select SIFIVE_TEST + select VIRTIO_MMIO =20 -config MICROCHIP_PFSOC +config SIFIVE_E bool select MSI_NONBROKEN select SIFIVE_CLINT + select SIFIVE_GPIO + select SIFIVE_PLIC + select SIFIVE_UART + select SIFIVE_E_PRCI select UNIMP - select MCHP_PFSOC_MMUART + +config SIFIVE_U + bool + select CADENCE + select MSI_NONBROKEN + select SIFIVE_CLINT + select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_PLIC - select CADENCE_SDHCI + select SIFIVE_UART + select SIFIVE_U_OTP + select SIFIVE_U_PRCI + select UNIMP + +config SPIKE + bool + select HTIF + select MSI_NONBROKEN + select SIFIVE_CLINT + select SIFIVE_PLIC --=20 2.7.4