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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=40.107.220.48; envelope-from=Babu.Moger@amd.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/01 11:57:28 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, FORGED_SPF_HELO=1, MSGID_FROM_MTA_HEADER=0.001, RCVD_ILLEGAL_IP=1.3, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: babu.moger@amd.com, qemu-devel@nongnu.org, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) Remove all the hardcoded values and replace with generalized fields. Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Reviewed-by: Igor Mammedov Reviewed-by: Pankaj Gupta --- target/i386/cpu.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ba4667b33c..b12addf323 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -395,11 +395,12 @@ static int cores_in_core_complex(int nr_cores) } =20 /* Encode cache info for CPUID[8000001D] */ -static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, + X86CPUTopoInfo *topo_info, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { - uint32_t l3_cores; + uint32_t l3_threads; assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -408,10 +409,10 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, CPUState *cs, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_cores =3D cores_in_core_complex(cs->nr_cores); - *eax |=3D ((l3_cores * cs->nr_threads) - 1) << 14; + l3_threads =3D topo_info->cores_per_die * topo_info->threads_per_c= ore; + *eax |=3D (l3_threads - 1) << 14; } else { - *eax |=3D ((cs->nr_threads - 1) << 14); + *eax |=3D ((topo_info->threads_per_core - 1) << 14); } =20 assert(cache->line_size > 0); @@ -5994,20 +5995,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, + &topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ *eax =3D *ebx =3D *ecx =3D *edx =3D 0; From nobody Fri May 17 06:43:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=amd.com) ARC-Seal: i=2; a=rsa-sha256; t=1598975912; cv=pass; d=zohomail.com; s=zohoarc; b=Y8zFC13FFHbRSpgT0DcIvHNErvlL0P4z1hEUkL/G4Jrl+YjMy+68cyyuzVHQtVZtsKfT08ddivhPemTOLewO3f/csqEWjmAR85c0VjKlvyAU+h7ARzHRhMkRxEkC7mcHsHEzAyd90LDWrrqc3NQEoaMV/2ZD1LxdTWsVTWoZul0= ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598975912; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=40.107.243.59; envelope-from=Babu.Moger@amd.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/09/01 11:57:34 X-ACL-Warn: Detected OS = Windows NT kernel [generic] [fuzzy] X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, FORGED_SPF_HELO=1, MSGID_FROM_MTA_HEADER=0.001, RCVD_ILLEGAL_IP=1.3, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_NONE=0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: babu.moger@amd.com, qemu-devel@nongnu.org, mst@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) apic_id contains all the information required to build CPUID_8000_001E. core_id and node_id is already part of apic_id generated by x86_topo_ids_from_apicid. Also remove the restriction on number bits on core_id and node_id. Remove all the hardcoded values and replace with generalized fields. Refer the Processor Programming Reference (PPR) documentation available from the bugzilla Link below. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov Acked-by: Michael S. Tsirkin Reviewed-by: Pankaj Gupta --- target/i386/cpu.c | 195 ++++++++++++-------------------------------------= ---- 1 file changed, 45 insertions(+), 150 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index b12addf323..ab2fcbd51c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -338,62 +338,6 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *l= 2, } } =20 -/* - * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E - * Please refer to the AMD64 Architecture Programmer=E2=80=99s Manual Volu= me 3. - * Define the constants to build the cpu topology. Right now, TOPOEXT - * feature is enabled only on EPYC. So, these constants are based on - * EPYC supported configurations. We may need to handle the cases if - * these values change in future. - */ -/* Maximum core complexes in a node */ -#define MAX_CCX 2 -/* Maximum cores in a core complex */ -#define MAX_CORES_IN_CCX 4 -/* Maximum cores in a node */ -#define MAX_CORES_IN_NODE 8 -/* Maximum nodes in a socket */ -#define MAX_NODES_PER_SOCKET 4 - -/* - * Figure out the number of nodes required to build this config. - * Max cores in a node is 8 - */ -static int nodes_in_socket(int nr_cores) -{ - int nodes; - - nodes =3D DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); - - /* Hardware does not support config with 3 nodes, return 4 in that case= */ - return (nodes =3D=3D 3) ? 4 : nodes; -} - -/* - * Decide the number of cores in a core complex with the given nr_cores us= ing - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible - * L3 cache is shared across all cores in a core complex. So, this will al= so - * tell us how many cores are sharing the L3 cache. - */ -static int cores_in_core_complex(int nr_cores) -{ - int nodes; - - /* Check if we can fit all the cores in one core complex */ - if (nr_cores <=3D MAX_CORES_IN_CCX) { - return nr_cores; - } - /* Get the number of nodes required to build this config */ - nodes =3D nodes_in_socket(nr_cores); - - /* - * Divide the cores accros all the core complexes - * Return rounded up value - */ - return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); -} - /* Encode cache info for CPUID[8000001D] */ static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, X86CPUTopoInfo *topo_info, @@ -432,107 +376,58 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo = *cache, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } =20 -/* Data structure to hold the configuration info for a given core index */ -struct core_topology { - /* core complex id of the current core index */ - int ccx_id; - /* - * Adjusted core index for this core in the topology - * This can be 0,1,2,3 with max 4 cores in a core complex - */ - int core_id; - /* Node id for this core index */ - int node_id; - /* Number of nodes in this config */ - int num_nodes; -}; - -/* - * Build the configuration closely match the EPYC hardware. Using the EPYC - * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_= NODE) - * right now. This could change in future. - * nr_cores : Total number of cores in the config - * core_id : Core index of the current CPU - * topo : Data structure to hold all the config info for this core ind= ex - */ -static void build_core_topology(int nr_cores, int core_id, - struct core_topology *topo) -{ - int nodes, cores_in_ccx; - - /* First get the number of nodes required */ - nodes =3D nodes_in_socket(nr_cores); - - cores_in_ccx =3D cores_in_core_complex(nr_cores); - - topo->node_id =3D core_id / (cores_in_ccx * MAX_CCX); - topo->ccx_id =3D (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; - topo->core_id =3D core_id % cores_in_ccx; - topo->num_nodes =3D nodes; -} - /* Encode cache info for CPUID[8000001E] */ -static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_topo_cpuid8000001e(X86CPU *cpu, X86CPUTopoInfo *topo_in= fo, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { - struct core_topology topo =3D {0}; - unsigned long nodes; - int shift; + X86CPUTopoIDs topo_ids; + + x86_topo_ids_from_apicid(cpu->apic_id, topo_info, &topo_ids); =20 - build_core_topology(cs->nr_cores, cpu->core_id, &topo); *eax =3D cpu->apic_id; + /* - * CPUID_Fn8000001E_EBX - * 31:16 Reserved - * 15:8 Threads per core (The number of threads per core is - * Threads per core + 1) - * 7:0 Core id (see bit decoding below) - * SMT: - * 4:3 node id - * 2 Core complex id - * 1:0 Core id - * Non SMT: - * 5:4 node id - * 3 Core complex id - * 1:0 Core id + * CPUID_Fn8000001E_EBX [Core Identifiers] (CoreId) + * Read-only. Reset: 0000_XXXXh. + * See Core::X86::Cpuid::ExtApicId. + * Core::X86::Cpuid::CoreId_lthree[1:0]_core[3:0]_thread[1:0]; + * Bits Description + * 31:16 Reserved. + * 15:8 ThreadsPerCore: threads per core. Read-only. Reset: XXh. + * The number of threads per core is ThreadsPerCore+1. + * 7:0 CoreId: core ID. Read-only. Reset: XXh. + * + * NOTE: CoreId is already part of apic_id. Just use it. We can + * use all the 8 bits to represent the core_id here. */ - if (cs->nr_threads - 1) { - *ebx =3D ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | - (topo.ccx_id << 2) | topo.core_id; - } else { - *ebx =3D (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; - } + *ebx =3D ((topo_info->threads_per_core - 1) << 8) | (topo_ids.core_id = & 0xFF); + /* - * CPUID_Fn8000001E_ECX - * 31:11 Reserved - * 10:8 Nodes per processor (Nodes per processor is number of nodes += 1) - * 7:0 Node id (see bit decoding below) - * 2 Socket id - * 1:0 Node id + * CPUID_Fn8000001E_ECX [Node Identifiers] (NodeId) + * Read-only. Reset: 0000_0XXXh. + * Core::X86::Cpuid::NodeId_lthree[1:0]_core[3:0]_thread[1:0]; + * Bits Description + * 31:11 Reserved. + * 10:8 NodesPerProcessor: Node per processor. Read-only. Reset: XXXb. + * ValidValues: + * Value Description + * 000b 1 node per processor. + * 001b 2 nodes per processor. + * 010b Reserved. + * 011b 4 nodes per processor. + * 111b-100b Reserved. + * 7:0 NodeId: Node ID. Read-only. Reset: XXh. + * + * NOTE: Hardware reserves 3 bits for number of nodes per processor. + * But users can create more nodes than the actual hardware can + * support. To genaralize we can use all the upper 8 bits for nodes. + * NodeId is combination of node and socket_id which is already decoded + * in apic_id. Just use it by shifting. */ - if (topo.num_nodes <=3D 4) { - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | - topo.node_id; - } else { - /* - * Node id fix up. Actual hardware supports up to 4 nodes. But with - * more than 32 cores, we may end up with more than 4 nodes. - * Node id is a combination of socket id and node id. Only require= ment - * here is that this number should be unique accross the system. - * Shift the socket id to accommodate more nodes. We dont expect b= oth - * socket id and node id to be big number at the same time. This i= s not - * an ideal config but we need to to support it. Max nodes we can = have - * is 32 (255/8) with 8 cores per node and 255 max cores. We only = need - * 5 bits for nodes. Find the left most set bit to represent the t= otal - * number of nodes. find_last_bit returns last set bit(0 based). L= eft - * shift(+1) the socket id to represent all the nodes. - */ - nodes =3D topo.num_nodes - 1; - shift =3D find_last_bit(&nodes, 8); - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift += 1)) | - topo.node_id; - } + *ecx =3D ((topo_info->dies_per_pkg - 1) << 8) | + ((cpu->apic_id >> apicid_die_offset(topo_info)) & 0xFF); + *edx =3D 0; } =20 @@ -6017,7 +5912,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x8000001E: assert(cpu->core_id <=3D 255); - encode_topo_cpuid8000001e(cs, cpu, + encode_topo_cpuid8000001e(cpu, &topo_info, eax, ebx, ecx, edx); break; case 0xC0000000: