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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.06 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=jDcYY0K/h58b0nGwvA6H9r7tjjvba9vWIRW+Z67cCA4=; b=oQ3z908AvEQRme7iG1uz1lKCs6Sy6/tj9h1zPvoFHix4qZodDGFhUIN/miFGXZbXbN 5HEO0CDyhoey7YK1VdGxf6HbCFPbKfsjoBZr43udfkDnp+juGEL+sMbP2+JmagyNP3UO 7U/IuBXgDNV7PjWl3XR/Jf8GjEvgGo8v7F4kV5ByU9MwH70xST4V4pUTCbxWHLFwF+DP NaIwwm3AaotxVtjj+JsSJnkwxRW7UfojKU+VLi85PDNaubicz8447kV0C38CKzkOs5Hp jC4w4fqAcYUIMyGSfT5hseFc1inuFHkOlAX/PU4szRACUXpuac3kQbJbjj8EP3dtgy7Q BwaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=jDcYY0K/h58b0nGwvA6H9r7tjjvba9vWIRW+Z67cCA4=; b=mKT6ACESUQhzZaSPLy2W+lKlOHjRQgIwwrb4M7gRt7Y8AXWW4jhlwQRTUFt5CzI3tt Hm0UhN9yxNDhA6TL7YdmK9dHYP8VEiJElTWmiF/63c/LHwhYB2PdomPMpuvw5iGYyDa3 4fvRpwijpDSFzPxsKqkQXp0JF4TFuifzsph5TONxTTU7R29XCKmAc4CchHJ7Mh64lRpx DH2RC9QsKF8Y5ELO3VapMziG+t0Ldgz0nVvWYcg/sDZcToYklL1aCa8i3U6stmCVyyEO 0s6vqrG7vD9h6t6iz+PCcEzCxlrEtT1GBi9rF9yy6vS3+uwzvZ3e3QTdQBwPu6rWgt6H HA0w== X-Gm-Message-State: AOAM533BW3A0ZMPGiRgKLFruUO64TjgQJyWIGh2Eoq9FZ0RYYQtnwcfq Er1SY2LSrd7OBecE3P45q5U= X-Google-Smtp-Source: ABdhPJzrvOqhJrioJvbe3LvHWSCigMKanQL3nS3od2FJAzHn8UeZuASgqGdcYQFxDJT6o5SwN77vYg== X-Received: by 2002:a05:6830:4001:: with SMTP id h1mr2323678ots.219.1598714290210; Sat, 29 Aug 2020 08:18:10 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 01/16] target/riscv: cpu: Add a new 'resetvec' property Date: Sat, 29 Aug 2020 23:17:25 +0800 Message-Id: <1598714261-8320-2-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Currently the reset vector address is hard-coded in a RISC-V CPU's instance_init() routine. In a real world we can have 2 exact same CPUs except for the reset vector address, which is pretty common in the RISC-V core IP licensing business. Normally reset vector address is a configurable parameter. Let's create a 64-bit property to store the reset vector address which covers both 32-bit and 64-bit CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) target/riscv/cpu.h | 1 + target/riscv/cpu.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 383808b..dc350f0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -291,6 +291,7 @@ typedef struct RISCVCPU { uint16_t elen; bool mmu; bool pmp; + uint64_t resetvec; } cfg; } RISCVCPU; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 228b9bd..8067a26 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -518,6 +518,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_UINT64("resetvec", RISCVCPU, cfg.resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; =20 --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1598714396; cv=none; d=zohomail.com; s=zohoarc; b=ITmFgAu64Q1luWINRnTo96Aapc2ykMSYylpZ6UQN8jL6GgB6ljVXFHLPXS5rUzhJwckjJusFT451r1zonnZBolj8xTls2CyL/KoB4zt7FWqcknJ6iaANMERz2lPfV4lfldQEARd88GkCIwuruk9dfVgh7wbP/PMxoEu695JRF3o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598714396; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=As6XYe9jhFVqGZbNvmQD6KrpN2QvPQQgwbIW8SC2EbU=; b=Ep17FuYzO1LqNauhUtV3jP9aUpeWLDlhdm0kDozbUyw3ZcOvMTqf9VshwkEnQPxTbG4dUH2kdxkPHYG1fc6O8QLdueFncMQdcoWbIYrcl7MMt42pz2wOJi6gwJrrLqYiLYugO36uc/FM/ovO9EpucPC7d2i7vUeaeAdcj9FrsRY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598714396875964.2097947435511; Sat, 29 Aug 2020 08:19:56 -0700 (PDT) Received: from localhost ([::1]:60810 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kC2e3-0002Da-Ny for importer@patchew.org; Sat, 29 Aug 2020 11:19:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44408) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kC2cS-0000OH-Ty; Sat, 29 Aug 2020 11:18:16 -0400 Received: from mail-oi1-x244.google.com ([2607:f8b0:4864:20::244]:45018) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kC2cR-0005AL-59; Sat, 29 Aug 2020 11:18:16 -0400 Received: by mail-oi1-x244.google.com with SMTP id 185so384291oie.11; Sat, 29 Aug 2020 08:18:14 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=As6XYe9jhFVqGZbNvmQD6KrpN2QvPQQgwbIW8SC2EbU=; b=A7XRqZey6DxNHKcgCNS6kCtfHuRakl89HYMf1DV55ozIrbpHoD1TMk+m1bzviWPfi3 SBiNr3DOPqb2MdPD31XvBu3mgoc7jt63Wj/LCiErMb3JBvHSKvah8lpQSil2q3dL3fey si7GMukJVhARyiDXKBD0tQgQF9xKTTAhYy7awl/9hWdsvLyawTMKsN34k/alLheIyNxc VO2KSxreNCCx7UzxGSB+eh7TMJ0rOSw4zAU13NM8wICpWRCcamx13ZquHTahHzeCpjHa PTy/WDWxAONXs8LSWmfelp7AExywUziY1pNvtDWDA7htpfi7b3UwMDOgoHeUTK4J2zzU q7Bw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=As6XYe9jhFVqGZbNvmQD6KrpN2QvPQQgwbIW8SC2EbU=; b=lc+Qv8Qfjv67NPzrVJg8XXtSAK2hFQQqKrM3l7DmJ7QHuriVhtW1yuHvJ820oRgk8M 7iZ2Z8CaTQBPZ9LHXTlxLDsfC1/7MIOT3pgmfqKyk5rTTGQ+9rFDzGLIqOAWqYAECaAP S7dt7Yh/J10i6Zrga1jeu4Z+vKS0/bQFfC7FWLAzZefbXkPSB6yyjhDfQ0LjxlGVja/P XNGkHLOL3vIiV1cQ8z4FLwpSaEyNbCEYHMaQ4RSGsPbN0P/kD13iCees7cZGBsBB0NRF zAZ1+2+PTzDGCQ4HnJK3MahadfuXKl52CLVhtuZnlT9ZayilLLyqC88krFti+kcwLueK K1Og== X-Gm-Message-State: AOAM533PVeEy1wezcEFoxdT2IAr4TZ4Ru/vg9uBx943MZXS8UKLCqaAP ETliuIP34DqHE/Ar4zCvL90= X-Google-Smtp-Source: ABdhPJxIKauQ5/S2k9YdkZdOceOZ5X40NyGUBhvUGmNEl2Jyw7ct+m26WVp62Kzf0Li+90I4Kxldfw== X-Received: by 2002:aca:ebc5:: with SMTP id j188mr2170418oih.129.1598714293624; Sat, 29 Aug 2020 08:18:13 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 02/16] hw/riscv: hart: Add a new 'resetvec' property Date: Sat, 29 Aug 2020 23:17:26 +0800 Message-Id: <1598714261-8320-3-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=bmeng.cn@gmail.com; helo=mail-oi1-x244.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng RISC-V machines do not instantiate RISC-V CPUs directly, instead they do that via the hart array. Add a new property for the reset vector address to allow the value to be passed to the CPU, before CPU is realized. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/riscv_hart.h | 1 + hw/riscv/riscv_hart.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index c75856f..77aa4bc 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -37,6 +37,7 @@ typedef struct RISCVHartArrayState { uint32_t num_harts; uint32_t hartid_base; char *cpu_type; + uint64_t resetvec; RISCVCPU *harts; } RISCVHartArrayState; =20 diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index f59fe52..613ea2a 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -31,6 +31,8 @@ static Property riscv_harts_props[] =3D { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), + DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, + DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -44,6 +46,7 @@ static bool riscv_hart_realize(RISCVHartArrayState *s, in= t idx, char *cpu_type, Error **errp) { object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); + qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); s->harts[idx].env.mhartid =3D s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1598714397; cv=none; d=zohomail.com; s=zohoarc; b=KjVWbcHvexqRP/Iou6EZwta7nPNXKraEh20FSijENuB6E4CWAi4ErT6LDJA+gLDvDJEE2ASUu2tL0YyGrDRj+dud0tta5Te8bgQgwsSYJbo2cFxipUVRL62eZUUH+ioHC9CdpBa4WOusONC0RObggfIphWQ2No7HgXE4ckA3QUY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598714397; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=zgCVaaWE4wk8cZqJM0imGhea+11Dl7ZU43jjVLpIW3Y=; b=eYllT1bl3340mE4YMT+tU2UpG+51M52XhON76DziUBSHqOR6pgfPN0Wx6eN9jfJz5U3jjQcvT1FCLU65Cv2B+s4CWCH6zAdR/IDHunYcuQntfzhG0jqZ3y2ruVIg09HOHgRzXgXqYdMTrjVGbTjy1oJnEKVNtyL5w5gaWqwWpEs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598714397844616.4752053139077; Sat, 29 Aug 2020 08:19:57 -0700 (PDT) Received: from localhost ([::1]:60992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kC2e5-0002Hs-1a for importer@patchew.org; Sat, 29 Aug 2020 11:19:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kC2cW-0000WL-HR; Sat, 29 Aug 2020 11:18:20 -0400 Received: from mail-ot1-x344.google.com ([2607:f8b0:4864:20::344]:33937) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kC2cU-0005Ao-Kn; Sat, 29 Aug 2020 11:18:20 -0400 Received: by mail-ot1-x344.google.com with SMTP id k20so1813118otr.1; Sat, 29 Aug 2020 08:18:17 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Now that we have the newly introduced 'resetvec' property in the RISC-V CPU and HART, instead of hard-coding the reset vector addr in the CPU's instance_init(), move that to riscv_cpu_realize() based on the configured property value from the RISC-V machines. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) hw/riscv/opentitan.c | 1 + hw/riscv/sifive_e.c | 1 + hw/riscv/sifive_u.c | 2 ++ target/riscv/cpu.c | 7 ++----- 4 files changed, 6 insertions(+), 5 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 23ba3b4..0531bd8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_s= oc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_a= bort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); =20 /* Boot ROM */ diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index ca55cc4..cd7560d 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -177,6 +177,7 @@ static void sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_a= bort); object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, TYPE_SIFIVE_GPIO); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a48046c..404d5e6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -611,6 +611,7 @@ static void sifive_u_soc_instance_init(Object *obj) qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); =20 object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUS= TER); qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); @@ -620,6 +621,7 @@ static void sifive_u_soc_instance_init(Object *obj) qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1= ); qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); =20 object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8067a26..bd41286 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -128,7 +128,6 @@ static void riscv_any_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_11_0); - set_resetvec(env, DEFAULT_RSTVEC); } =20 static void riscv_base_cpu_init(Object *obj) @@ -136,7 +135,6 @@ static void riscv_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, 0); - set_resetvec(env, DEFAULT_RSTVEC); } =20 static void rvxx_sifive_u_cpu_init(Object *obj) @@ -144,7 +142,6 @@ static void rvxx_sifive_u_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x1004); } =20 static void rvxx_sifive_e_cpu_init(Object *obj) @@ -152,7 +149,6 @@ static void rvxx_sifive_e_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RVXLEN | RVI | RVM | RVA | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x1004); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } =20 @@ -163,7 +159,6 @@ static void rv32_ibex_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; set_misa(env, RV32 | RVI | RVM | RVC | RVU); set_priv_version(env, PRIV_VERSION_1_10_0); - set_resetvec(env, 0x8090); qdev_prop_set_bit(DEVICE(obj), "mmu", false); } =20 @@ -373,6 +368,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) set_feature(env, RISCV_FEATURE_PMP); } =20 + set_resetvec(env, cpu->cfg.resetvec); + /* If misa isn't set (rv32 and rv64 machines) set it here */ if (!env->misa) { /* Do some ISA extension error checking */ --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.17 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ElBvCqHBiT2q8Csl+KnNCyF/5sox0P8YJrT3M8iL2Qk=; b=ahztOOgkmaqXFqVD0Czj6SoilmdTQRbepho/7Wwu7vBjkgNnqxw9UfzAKZAm3eyQJD PyfvYN4h75f5BycvxU+vA1NPICAlhhgE25wO70Oql44NOuQhOMnvyqi96yBZ1EIrPEQ1 lpkXG0opTXQwvr7nAPz+vOIb9hTp6Mrv+CObN6GV9Tzzl+XeAoXTz0ez9EsCXsOErZw5 AnnAvihgevGSZS0nBfTNQbUYJyp6AGDIT+LYMPMNtyss2c+5cBackGzXEV7tyWxUKJ42 GYm5FHd57vGFmvY4c1dtAD4JmwvMGagziMZWTEevaECNzBIv5Yta2M7eIxrKnMFkCVna IYQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ElBvCqHBiT2q8Csl+KnNCyF/5sox0P8YJrT3M8iL2Qk=; b=XKu0tiBvbn2wel2dUA/JdyUR/ILcv4Oa/9eRXfk6SeTU4A61Xlb/7vyjY/VpsvBggn +/55tXFcWsY6ca3z/uRurNBYjQEQgYfUVD5agM1ECDr3pmODOTbMzQyWMmJcnmQwdyyv rH1TPBYfL/H29MbDruQ9dsPvBwHaHE8IVzP7qfwey2YyyRNnVOzuK6mYWFgrnhogyd23 ueptdOnoneGmb+1ub2JePqDsSr11h2SqjXY5wWE83ePs/GriBs5b3abrgl7s75zYunet U1Wk9fgCDvW6lrJqmNZWGonZded/9ujOtehxmDUJEDZ7ky0Rw/yLz8DFB1V+rQGprqm3 R30Q== X-Gm-Message-State: AOAM5312jc35XsqomUDESh6P4aIqahXWc/0Ie3Fuj1vfaMkm/iKRRPI3 u1V3h6EGWq223KKybpONFmI= X-Google-Smtp-Source: ABdhPJzSgrLL7mhkVF1/VyLAeAq6sPWZ0z5jxG/6i3anLvpiorMYWut2tYniL8dlaVencPJ1ApJdIw== X-Received: by 2002:a05:6830:1c61:: with SMTP id s1mr220695otg.149.1598714300881; Sat, 29 Aug 2020 08:18:20 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 04/16] hw/riscv: Initial support for Microchip PolarFire SoC Icicle Kit board Date: Sat, 29 Aug 2020 23:17:28 +0800 Message-Id: <1598714261-8320-5-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is an initial support for Microchip PolarFire SoC Icicle Kit. The Icicle Kit board integrates a PolarFire SoC, with one SiFive's E51 plus four U54 cores and many on-chip peripherals and an FPGA. For more details about Microchip PolarFire Soc, please see: https://www.microsemi.com/product-directory/soc-fpgas/5498-polarfire-soc-fp= ga Unlike SiFive FU540, the RISC-V core resect vector is at 0x20220000. The following perepherals are created as an unimplemented device: - Bus Error Uint 0/1/2/3/4 - L2 cache controller - SYSREG - MPUCFG - IOSCBCFG More devices will be added later. The BIOS image used by this machine is hss.bin, aka Hart Software Services, which can be built from: https://github.com/polarfire-soc/hart-software-services To launch this machine: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit The memory is set to 1 GiB by default to match the hardware. A sanity check on ram size is performed in the machine init routine to prompt user to increase the RAM size to > 1 GiB when less than 1 GiB ram is detected. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) default-configs/riscv64-softmmu.mak | 1 + include/hw/riscv/microchip_pfsoc.h | 88 ++++++++++ hw/riscv/microchip_pfsoc.c | 312 ++++++++++++++++++++++++++++++++= ++++ MAINTAINERS | 7 + hw/riscv/Kconfig | 6 + hw/riscv/meson.build | 1 + 6 files changed, 415 insertions(+) create mode 100644 include/hw/riscv/microchip_pfsoc.h create mode 100644 hw/riscv/microchip_pfsoc.c diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-= softmmu.mak index aaf6d73..76b6195 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -10,3 +10,4 @@ CONFIG_SPIKE=3Dy CONFIG_SIFIVE_E=3Dy CONFIG_SIFIVE_U=3Dy CONFIG_RISCV_VIRT=3Dy +CONFIG_MICROCHIP_PFSOC=3Dy diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h new file mode 100644 index 0000000..1953ef1 --- /dev/null +++ b/include/hw/riscv/microchip_pfsoc.h @@ -0,0 +1,88 @@ +/* + * Microchip PolarFire SoC machine interface + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_MICROCHIP_PFSOC_H +#define HW_MICROCHIP_PFSOC_H + +typedef struct MicrochipPFSoCState { + /*< private >*/ + DeviceState parent_obj; + + /*< public >*/ + CPUClusterState e_cluster; + CPUClusterState u_cluster; + RISCVHartArrayState e_cpus; + RISCVHartArrayState u_cpus; + DeviceState *plic; +} MicrochipPFSoCState; + +#define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" +#define MICROCHIP_PFSOC(obj) \ + OBJECT_CHECK(MicrochipPFSoCState, (obj), TYPE_MICROCHIP_PFSOC) + +typedef struct MicrochipIcicleKitState { + /*< private >*/ + MachineState parent_obj; + + /*< public >*/ + MicrochipPFSoCState soc; +} MicrochipIcicleKitState; + +#define TYPE_MICROCHIP_ICICLE_KIT_MACHINE \ + MACHINE_TYPE_NAME("microchip-icicle-kit") +#define MICROCHIP_ICICLE_KIT_MACHINE(obj) \ + OBJECT_CHECK(MicrochipIcicleKitState, (obj), \ + TYPE_MICROCHIP_ICICLE_KIT_MACHINE) + +enum { + MICROCHIP_PFSOC_DEBUG, + MICROCHIP_PFSOC_E51_DTIM, + MICROCHIP_PFSOC_BUSERR_UNIT0, + MICROCHIP_PFSOC_BUSERR_UNIT1, + MICROCHIP_PFSOC_BUSERR_UNIT2, + MICROCHIP_PFSOC_BUSERR_UNIT3, + MICROCHIP_PFSOC_BUSERR_UNIT4, + MICROCHIP_PFSOC_CLINT, + MICROCHIP_PFSOC_L2CC, + MICROCHIP_PFSOC_L2LIM, + MICROCHIP_PFSOC_PLIC, + MICROCHIP_PFSOC_SYSREG, + MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_ENVM_CFG, + MICROCHIP_PFSOC_ENVM_DATA, + MICROCHIP_PFSOC_IOSCB_CFG, + MICROCHIP_PFSOC_DRAM, +}; + +#define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 +#define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 + +#define MICROCHIP_PFSOC_PLIC_HART_CONFIG "MS" +#define MICROCHIP_PFSOC_PLIC_NUM_SOURCES 185 +#define MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES 7 +#define MICROCHIP_PFSOC_PLIC_PRIORITY_BASE 0x04 +#define MICROCHIP_PFSOC_PLIC_PENDING_BASE 0x1000 +#define MICROCHIP_PFSOC_PLIC_ENABLE_BASE 0x2000 +#define MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE 0x80 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_BASE 0x200000 +#define MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE 0x1000 + +#endif /* HW_MICROCHIP_PFSOC_H */ diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c new file mode 100644 index 0000000..d946b2a --- /dev/null +++ b/hw/riscv/microchip_pfsoc.c @@ -0,0 +1,312 @@ +/* + * QEMU RISC-V Board Compatible with Microchip PolarFire SoC Icicle Kit + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * Provides a board compatible with the Microchip PolarFire SoC Icicle Kit + * + * 0) CLINT (Core Level Interruptor) + * 1) PLIC (Platform Level Interrupt Controller) + * 2) eNVM (Embedded Non-Volatile Memory) + * + * This board currently generates devicetree dynamically that indicates at= least + * two harts and up to five harts. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qemu/units.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "hw/boards.h" +#include "hw/irq.h" +#include "hw/loader.h" +#include "hw/sysbus.h" +#include "hw/cpu/cluster.h" +#include "target/riscv/cpu.h" +#include "hw/misc/unimp.h" +#include "hw/riscv/boot.h" +#include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_clint.h" +#include "hw/riscv/sifive_plic.h" +#include "hw/riscv/microchip_pfsoc.h" + +/* + * The BIOS image used by this machine is called Hart Software Services (H= SS). + * See https://github.com/polarfire-soc/hart-software-services + */ +#define BIOS_FILENAME "hss.bin" +#define RESET_VECTOR 0x20220000 + +static const struct MemmapEntry { + hwaddr base; + hwaddr size; +} microchip_pfsoc_memmap[] =3D { + [MICROCHIP_PFSOC_DEBUG] =3D { 0x0, 0x1000 }, + [MICROCHIP_PFSOC_E51_DTIM] =3D { 0x1000000, 0x2000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT0] =3D { 0x1700000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT1] =3D { 0x1701000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT2] =3D { 0x1702000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT3] =3D { 0x1703000, 0x1000 }, + [MICROCHIP_PFSOC_BUSERR_UNIT4] =3D { 0x1704000, 0x1000 }, + [MICROCHIP_PFSOC_CLINT] =3D { 0x2000000, 0x10000 }, + [MICROCHIP_PFSOC_L2CC] =3D { 0x2010000, 0x1000 }, + [MICROCHIP_PFSOC_L2LIM] =3D { 0x8000000, 0x2000000 }, + [MICROCHIP_PFSOC_PLIC] =3D { 0xc000000, 0x4000000 }, + [MICROCHIP_PFSOC_SYSREG] =3D { 0x20002000, 0x2000 }, + [MICROCHIP_PFSOC_MPUCFG] =3D { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_ENVM_CFG] =3D { 0x20200000, 0x1000 }, + [MICROCHIP_PFSOC_ENVM_DATA] =3D { 0x20220000, 0x20000 }, + [MICROCHIP_PFSOC_IOSCB_CFG] =3D { 0x37080000, 0x1000 }, + [MICROCHIP_PFSOC_DRAM] =3D { 0x80000000, 0x0 }, +}; + +static void microchip_pfsoc_soc_instance_init(Object *obj) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + MicrochipPFSoCState *s =3D MICROCHIP_PFSOC(obj); + + object_initialize_child(obj, "e-cluster", &s->e_cluster, TYPE_CPU_CLUS= TER); + qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + + object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", &s->e_cpus, + TYPE_RISCV_HART_ARRAY); + qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); + qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_E51); + qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", RESET_VECTOR); + + object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUS= TER); + qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); + + object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", &s->u_cpus, + TYPE_RISCV_HART_ARRAY); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1= ); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); + qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", + TYPE_RISCV_CPU_SIFIVE_U54); + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); +} + +static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) +{ + MachineState *ms =3D MACHINE(qdev_get_machine()); + MicrochipPFSoCState *s =3D MICROCHIP_PFSOC(dev); + const struct MemmapEntry *memmap =3D microchip_pfsoc_memmap; + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *e51_dtim_mem =3D g_new(MemoryRegion, 1); + MemoryRegion *l2lim_mem =3D g_new(MemoryRegion, 1); + MemoryRegion *envm_data =3D g_new(MemoryRegion, 1); + char *plic_hart_config; + size_t plic_hart_config_len; + int i; + + sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); + sysbus_realize(SYS_BUS_DEVICE(&s->u_cpus), &error_abort); + /* + * The cluster must be realized after the RISC-V hart array container, + * as the container's CPU object is only created on realize, and the + * CPU must exist and have been parented into the cluster before the + * cluster is realized. + */ + qdev_realize(DEVICE(&s->e_cluster), NULL, &error_abort); + qdev_realize(DEVICE(&s->u_cluster), NULL, &error_abort); + + /* E51 DTIM */ + memory_region_init_ram(e51_dtim_mem, NULL, "microchip.pfsoc.e51_dtim_m= em", + memmap[MICROCHIP_PFSOC_E51_DTIM].size, &error_f= atal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_E51_DTIM].base, + e51_dtim_mem); + + /* Bus Error Units */ + create_unimplemented_device("microchip.pfsoc.buserr_unit0_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT0].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit1_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT1].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit2_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT2].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit3_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT3].size); + create_unimplemented_device("microchip.pfsoc.buserr_unit4_mem", + memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].base, + memmap[MICROCHIP_PFSOC_BUSERR_UNIT4].size); + + /* CLINT */ + sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, + memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + + /* L2 cache controller */ + create_unimplemented_device("microchip.pfsoc.l2cc", + memmap[MICROCHIP_PFSOC_L2CC].base, memmap[MICROCHIP_PFSOC_L2CC].si= ze); + + /* + * Add L2-LIM at reset size. + * This should be reduced in size as the L2 Cache Controller WayEnable + * register is incremented. Unfortunately I don't see a nice (or any) = way + * to handle reducing or blocking out the L2 LIM while still allowing = it + * be re returned to all enabled after a reset. For the time being, ju= st + * leave it enabled all the time. This won't break anything, but will = be + * too generous to misbehaving guests. + */ + memory_region_init_ram(l2lim_mem, NULL, "microchip.pfsoc.l2lim", + memmap[MICROCHIP_PFSOC_L2LIM].size, &error_fata= l); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_L2LIM].base, + l2lim_mem); + + /* create PLIC hart topology configuration string */ + plic_hart_config_len =3D (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG) + 1= ) * + ms->smp.cpus; + plic_hart_config =3D g_malloc0(plic_hart_config_len); + for (i =3D 0; i < ms->smp.cpus; i++) { + if (i !=3D 0) { + strncat(plic_hart_config, "," MICROCHIP_PFSOC_PLIC_HART_CONFIG, + plic_hart_config_len); + } else { + strncat(plic_hart_config, "M", plic_hart_config_len); + } + plic_hart_config_len -=3D (strlen(MICROCHIP_PFSOC_PLIC_HART_CONFIG= ) + 1); + } + + /* PLIC */ + s->plic =3D sifive_plic_create(memmap[MICROCHIP_PFSOC_PLIC].base, + plic_hart_config, 0, + MICROCHIP_PFSOC_PLIC_NUM_SOURCES, + MICROCHIP_PFSOC_PLIC_NUM_PRIORITIES, + MICROCHIP_PFSOC_PLIC_PRIORITY_BASE, + MICROCHIP_PFSOC_PLIC_PENDING_BASE, + MICROCHIP_PFSOC_PLIC_ENABLE_BASE, + MICROCHIP_PFSOC_PLIC_ENABLE_STRIDE, + MICROCHIP_PFSOC_PLIC_CONTEXT_BASE, + MICROCHIP_PFSOC_PLIC_CONTEXT_STRIDE, + memmap[MICROCHIP_PFSOC_PLIC].size); + g_free(plic_hart_config); + + /* SYSREG */ + create_unimplemented_device("microchip.pfsoc.sysreg", + memmap[MICROCHIP_PFSOC_SYSREG].base, + memmap[MICROCHIP_PFSOC_SYSREG].size); + + /* MPUCFG */ + create_unimplemented_device("microchip.pfsoc.mpucfg", + memmap[MICROCHIP_PFSOC_MPUCFG].base, + memmap[MICROCHIP_PFSOC_MPUCFG].size); + + /* eNVM */ + memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.d= ata", + memmap[MICROCHIP_PFSOC_ENVM_DATA].size, + &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_ENVM_DATA].base, + envm_data); + + /* IOSCBCFG */ + create_unimplemented_device("microchip.pfsoc.ioscb.cfg", + memmap[MICROCHIP_PFSOC_IOSCB_CFG].base, + memmap[MICROCHIP_PFSOC_IOSCB_CFG].size); +} + +static void microchip_pfsoc_soc_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(oc); + + dc->realize =3D microchip_pfsoc_soc_realize; + /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ + dc->user_creatable =3D false; +} + +static const TypeInfo microchip_pfsoc_soc_type_info =3D { + .name =3D TYPE_MICROCHIP_PFSOC, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(MicrochipPFSoCState), + .instance_init =3D microchip_pfsoc_soc_instance_init, + .class_init =3D microchip_pfsoc_soc_class_init, +}; + +static void microchip_pfsoc_soc_register_types(void) +{ + type_register_static(µchip_pfsoc_soc_type_info); +} + +type_init(microchip_pfsoc_soc_register_types) + +static void microchip_icicle_kit_machine_init(MachineState *machine) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const struct MemmapEntry *memmap =3D microchip_pfsoc_memmap; + MicrochipIcicleKitState *s =3D MICROCHIP_ICICLE_KIT_MACHINE(machine); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + + /* Sanity check on RAM size */ + if (machine->ram_size < mc->default_ram_size) { + char *sz =3D size_to_str(mc->default_ram_size); + error_report("Invalid RAM size, should be bigger than %s", sz); + g_free(sz); + exit(EXIT_FAILURE); + } + + /* Initialize SoC */ + object_initialize_child(OBJECT(machine), "soc", &s->soc, + TYPE_MICROCHIP_PFSOC); + qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + + /* Register RAM */ + memory_region_init_ram(main_mem, NULL, "microchip.icicle.kit.ram", + machine->ram_size, &error_fatal); + memory_region_add_subregion(system_memory, + memmap[MICROCHIP_PFSOC_DRAM].base, main_me= m); + + /* Load the firmware */ + riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NUL= L); +} + +static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void = *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "Microchip PolarFire SoC Icicle Kit"; + mc->init =3D microchip_icicle_kit_machine_init; + mc->max_cpus =3D MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + + MICROCHIP_PFSOC_COMPUTE_CPU_COUNT; + mc->min_cpus =3D MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus =3D mc->min_cpus; + mc->default_ram_size =3D 1 * GiB; +} + +static const TypeInfo microchip_icicle_kit_machine_typeinfo =3D { + .name =3D MACHINE_TYPE_NAME("microchip-icicle-kit"), + .parent =3D TYPE_MACHINE, + .class_init =3D microchip_icicle_kit_machine_class_init, + .instance_size =3D sizeof(MicrochipIcicleKitState), +}; + +static void microchip_icicle_kit_machine_init_register_types(void) +{ + type_register_static(µchip_icicle_kit_machine_typeinfo); +} + +type_init(microchip_icicle_kit_machine_init_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 5a22c8b..5359b39 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1315,6 +1315,13 @@ F: include/hw/riscv/opentitan.h F: include/hw/char/ibex_uart.h F: include/hw/intc/ibex_plic.h =20 +Microchip PolarFire SoC Icicle Kit +M: Bin Meng +L: qemu-riscv@nongnu.org +S: Supported +F: hw/riscv/microchip_pfsoc.c +F: include/hw/riscv/microchip_pfsoc.h + RX Machines ----------- rx-gdbsim diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 28947ef..3292fae 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -48,3 +48,9 @@ config RISCV_VIRT select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 select SIFIVE + +config MICROCHIP_PFSOC + bool + select HART + select SIFIVE + select UNIMP diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 25af9db..cf1aa99 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -16,5 +16,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sif= ive_u_otp.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) +riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfs= oc.c')) =20 hw_arch +=3D {'riscv': riscv_ss} --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.21 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kq3y5HQV/PUolrKKsQRxge2Z7DyIbib/n6eqgklz5W4=; b=JJaZki/yGpvY6gtZSDN59QPbWcXL+oau3VHDQIXbPlKk1EZbJFqaFkYGc5gHaT6h+G x4lKb0rUdq7sB1BX2jp2KBAti/ZkmlLohOUcPebYbeHeQXqdd1DsNhc26mnZUASKDum6 meQuqab/Z+gvLXVgxvtAIgFxLVeeAdGhaktyVkwJ3e2YjeXp6zpWrjXoI+OESNLzyh/Z 2lvLrSQkWDHgm9RL6HRVSD1gVT15XKmelPUn88cxpXC2PXkZcFsLuZ2umJLIK9U3jLQz YUHSvI74l6NjZ40LmSpeW0DalVlwkOKpukcmzC+Rk5eOuVe262j/pT6vMIkRGNyf9CGQ vvXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kq3y5HQV/PUolrKKsQRxge2Z7DyIbib/n6eqgklz5W4=; b=o/raWolFQgOOMBh8a3bySQfZeS6589FcyWQ6QWx9c+yX5/+G3Nt+fjWoxrG/K2WCnD hTuj/8ud6eEe75YWHayiSUOFp9UcMiWHY3SYLYFABIJQy3Ou+MaKWRJjcoBX5SKg6xh7 /tUXxOjP1uc8AdRzsilNkjGAA2Gr56W3aEjTd63oXQlD8cBdqPER9lUiWMaF5jL+Do5I O4OUSD+G9NXkY3WME4OdDRZePnwMdRVkfVYwjBBt5Z8kBD8X3mNiwdLgNGifn43CSq3+ 55yTW/L1DdB1eBUjOa1IQQao74iir62kpBMvATyIWiMAxSlm2ItjWCT/+57193cMizV5 Syag== X-Gm-Message-State: AOAM5322yP/ElBxRvTHyW98q+3gfrmDB9RSEYnFmzqCfCZI8MYdolfhK GyDIiStEWBcx5WF6DapRsYc= X-Google-Smtp-Source: ABdhPJyzw33dm6KbhNBY+auEE5qqcuPJAQugp6/2m75x70kj5gkknVsOi1wv5+lnywyntYKjfQmHzw== X-Received: by 2002:a4a:a60a:: with SMTP id e10mr2602288oom.25.1598714304464; Sat, 29 Aug 2020 08:18:24 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 05/16] hw/char: Add Microchip PolarFire SoC MMUART emulation Date: Sat, 29 Aug 2020 23:17:29 +0800 Message-Id: <1598714261-8320-6-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c41; envelope-from=bmeng.cn@gmail.com; helo=mail-oo1-xc41.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Microchip PolarFire SoC MMUART is ns16550 compatible, with some additional registers. Create a simple MMUART model built on top of the existing ns16550 model. Signed-off-by: Bin Meng --- Changes in v2: - change to update hw/char/meson.build - add impl.min_access_size and impl.max_access_size as part of MemoryRegionOps and remove the allignment check include/hw/char/mchp_pfsoc_mmuart.h | 61 ++++++++++++++++++++++++++ hw/char/mchp_pfsoc_mmuart.c | 86 +++++++++++++++++++++++++++++++++= ++++ MAINTAINERS | 2 + hw/char/Kconfig | 3 ++ hw/char/meson.build | 1 + 5 files changed, 153 insertions(+) create mode 100644 include/hw/char/mchp_pfsoc_mmuart.h create mode 100644 hw/char/mchp_pfsoc_mmuart.c diff --git a/include/hw/char/mchp_pfsoc_mmuart.h b/include/hw/char/mchp_pfs= oc_mmuart.h new file mode 100644 index 0000000..f619902 --- /dev/null +++ b/include/hw/char/mchp_pfsoc_mmuart.h @@ -0,0 +1,61 @@ +/* + * Microchip PolarFire SoC MMUART emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_MCHP_PFSOC_MMUART_H +#define HW_MCHP_PFSOC_MMUART_H + +#include "hw/char/serial.h" + +#define MCHP_PFSOC_MMUART_REG_SIZE 52 + +typedef struct MchpPfSoCMMUartState { + MemoryRegion iomem; + hwaddr base; + qemu_irq irq; + + SerialMM *serial; + + uint32_t reg[MCHP_PFSOC_MMUART_REG_SIZE / sizeof(uint32_t)]; +} MchpPfSoCMMUartState; + +/** + * mchp_pfsoc_mmuart_create - Create a Microchip PolarFire SoC MMUART + * + * This is a helper routine for board to create a MMUART device that is + * compatible with Microchip PolarFire SoC. + * + * @sysmem: system memory region to map + * @base: base address of the MMUART registers + * @irq: IRQ number of the MMUART device + * @chr: character device to associate to + * + * @return: a pointer to the device specific control structure + */ +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, qemu_irq irq, Chardev *chr); + +#endif /* HW_MCHP_PFSOC_MMUART_H */ diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c new file mode 100644 index 0000000..8a002b0 --- /dev/null +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -0,0 +1,86 @@ +/* + * Microchip PolarFire SoC MMUART emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "chardev/char.h" +#include "exec/address-spaces.h" +#include "hw/char/mchp_pfsoc_mmuart.h" + +static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned= size) +{ + MchpPfSoCMMUartState *s =3D opaque; + + if (addr >=3D MCHP_PFSOC_MMUART_REG_SIZE) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=3D0x%" HWADDR_PRIx = "\n", + __func__, addr); + return 0; + } + + return s->reg[addr / sizeof(uint32_t)]; +} + +static void mchp_pfsoc_mmuart_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + MchpPfSoCMMUartState *s =3D opaque; + uint32_t val32 =3D (uint32_t)value; + + if (addr >=3D MCHP_PFSOC_MMUART_REG_SIZE) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=3D0x%" HWADDR_= PRIx + " v=3D0x%x\n", __func__, addr, val32); + return; + } + + s->reg[addr / sizeof(uint32_t)] =3D val32; +} + +static const MemoryRegionOps mchp_pfsoc_mmuart_ops =3D { + .read =3D mchp_pfsoc_mmuart_read, + .write =3D mchp_pfsoc_mmuart_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +MchpPfSoCMMUartState *mchp_pfsoc_mmuart_create(MemoryRegion *sysmem, + hwaddr base, qemu_irq irq, Chardev *chr) +{ + MchpPfSoCMMUartState *s; + + s =3D g_new0(MchpPfSoCMMUartState, 1); + + memory_region_init_io(&s->iomem, NULL, &mchp_pfsoc_mmuart_ops, s, + "mchp.pfsoc.mmuart", 0x1000); + + s->base =3D base; + s->irq =3D irq; + + s->serial =3D serial_mm_init(sysmem, base, 2, irq, 399193, chr, + DEVICE_LITTLE_ENDIAN); + + memory_region_add_subregion(sysmem, base + 0x20, &s->iomem); + + return s; +} diff --git a/MAINTAINERS b/MAINTAINERS index 5359b39..4002d51 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1320,7 +1320,9 @@ M: Bin Meng L: qemu-riscv@nongnu.org S: Supported F: hw/riscv/microchip_pfsoc.c +F: hw/char/mchp_pfsoc_mmuart.c F: include/hw/riscv/microchip_pfsoc.h +F: include/hw/char/mchp_pfsoc_mmuart.h =20 RX Machines ----------- diff --git a/hw/char/Kconfig b/hw/char/Kconfig index b7e0e4d..1d64555 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -52,3 +52,6 @@ config RENESAS_SCI =20 config AVR_USART bool + +config MCHP_PFSOC_MMUART + bool diff --git a/hw/char/meson.build b/hw/char/meson.build index e888215..ae27932 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -32,6 +32,7 @@ softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2= 835_aux.c')) softmmu_ss.add(when: 'CONFIG_RENESAS_SCI', if_true: files('renesas_sci.c')) softmmu_ss.add(when: 'CONFIG_SH4', if_true: files('sh_serial.c')) softmmu_ss.add(when: 'CONFIG_STM32F2XX_USART', if_true: files('stm32f2xx_u= sart.c')) +softmmu_ss.add(when: 'CONFIG_MCHP_PFSOC_MMUART', if_true: files('mchp_pfso= c_mmuart.c')) =20 specific_ss.add(when: 'CONFIG_TERMINAL3270', if_true: files('terminal3270.= c')) specific_ss.add(when: 'CONFIG_VIRTIO', if_true: files('virtio-serial-bus.c= ')) --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vnuiw/muM6soC9Fx9pcU+x5ClmS6jV/SRavwXbyBRhw=; b=UzgJpFBFNqZnSKJUNFgIaICdoCajFp+ARa4obk/XPYyIULfWLzpbhXfW/a6NtIiX/p Kg9Q24x890PjKgNnf6Xl0OKTC366noMCkmvQFOV9CEYwAa99jdIOQDM1XdB7ocYMuew4 nKL6B77hEEsT0Px0N604hnt2LY7APy6xJUOqX6LIrDFStGgEJD6flUyGgwQkW0EHQrnm hmCIxmh1AbGA9cEuGTOMPrGHkbrto6770u+rizeg2CvZYlG67c8RbNV7ja9ZykoFOOex FD5DWUELVxM0DphiHq2skGoYLBVfhJ/hYCMpQuGLY6h0YoG64mA4N7G4V81TSnRrz3B7 KQKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vnuiw/muM6soC9Fx9pcU+x5ClmS6jV/SRavwXbyBRhw=; b=HFxf67eJ2hZPERB9OEHUTBc1alxY0JwG2pJQOBVEjLn+OmruKMzc1CFUihK6T69v3F nveVCFG+RLnGzcKq816FlzMlRcDdYiS2xwn5G1hDmERcSCHBV2MsNRdXN3/9RfZCacxc lQe7uXNHCXJJexZ3rEvuWS8Xtic9Ax6Sizbeet9OeJEcQg0hw95y4xnOk714pBVZV1Dd me6r7Ir9JmeeAGCNKyuG3DuDp0/y5veYY7IIyAQS72vpSC94asPueFMkHPUcgEJ+eGmE Wi84kykJInmaPkQtDzTYxcfiZBlou/Zjh7oK+GIG9pg3P0q72geastsUKJ6oCYb42baT hTCw== X-Gm-Message-State: AOAM533e3LhpF4kXQnxtt3Wqn9gKHV4ckUVeYdHOvtMmt//H1OVZn9ea zrV8ik7be2lAfXDmxlFzy8Q= X-Google-Smtp-Source: ABdhPJwZd60aTisNiWwhi6A+8J9r3bN8dCd/7NEAGaxYuk29PAaaVTwasu4T5yx3sIUiqRQHXAa18A== X-Received: by 2002:a05:6808:3cb:: with SMTP id o11mr2221449oie.75.1598714308037; Sat, 29 Aug 2020 08:18:28 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 06/16] hw/riscv: microchip_pfsoc: Connect 5 MMUARTs Date: Sat, 29 Aug 2020 23:17:30 +0800 Message-Id: <1598714261-8320-7-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=bmeng.cn@gmail.com; helo=mail-oi1-x241.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Microchip PolarFire SoC has 5 MMUARTs, and the Icicle Kit board wires 4 of them out. Let's connect all 5 MMUARTs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/microchip_pfsoc.h | 20 ++++++++++++++++++++ hw/riscv/microchip_pfsoc.c | 30 ++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 1 + 3 files changed, 51 insertions(+) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index 1953ef1..a5efa1d 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -22,6 +22,8 @@ #ifndef HW_MICROCHIP_PFSOC_H #define HW_MICROCHIP_PFSOC_H =20 +#include "hw/char/mchp_pfsoc_mmuart.h" + typedef struct MicrochipPFSoCState { /*< private >*/ DeviceState parent_obj; @@ -32,6 +34,11 @@ typedef struct MicrochipPFSoCState { RISCVHartArrayState e_cpus; RISCVHartArrayState u_cpus; DeviceState *plic; + MchpPfSoCMMUartState *serial0; + MchpPfSoCMMUartState *serial1; + MchpPfSoCMMUartState *serial2; + MchpPfSoCMMUartState *serial3; + MchpPfSoCMMUartState *serial4; } MicrochipPFSoCState; =20 #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" @@ -64,14 +71,27 @@ enum { MICROCHIP_PFSOC_L2CC, MICROCHIP_PFSOC_L2LIM, MICROCHIP_PFSOC_PLIC, + MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_MMUART1, + MICROCHIP_PFSOC_MMUART2, + MICROCHIP_PFSOC_MMUART3, + MICROCHIP_PFSOC_MMUART4, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, MICROCHIP_PFSOC_DRAM, }; =20 +enum { + MICROCHIP_PFSOC_MMUART0_IRQ =3D 90, + MICROCHIP_PFSOC_MMUART1_IRQ =3D 91, + MICROCHIP_PFSOC_MMUART2_IRQ =3D 92, + MICROCHIP_PFSOC_MMUART3_IRQ =3D 93, + MICROCHIP_PFSOC_MMUART4_IRQ =3D 94, +}; + #define MICROCHIP_PFSOC_MANAGEMENT_CPU_COUNT 1 #define MICROCHIP_PFSOC_COMPUTE_CPU_COUNT 4 =20 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index d946b2a..cee959a 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -11,6 +11,7 @@ * 0) CLINT (Core Level Interruptor) * 1) PLIC (Platform Level Interrupt Controller) * 2) eNVM (Embedded Non-Volatile Memory) + * 3) MMUARTs (Multi-Mode UART) * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -38,6 +39,7 @@ #include "hw/irq.h" #include "hw/loader.h" #include "hw/sysbus.h" +#include "chardev/char.h" #include "hw/cpu/cluster.h" #include "target/riscv/cpu.h" #include "hw/misc/unimp.h" @@ -46,6 +48,7 @@ #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/microchip_pfsoc.h" +#include "sysemu/sysemu.h" =20 /* * The BIOS image used by this machine is called Hart Software Services (H= SS). @@ -69,8 +72,13 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_L2CC] =3D { 0x2010000, 0x1000 }, [MICROCHIP_PFSOC_L2LIM] =3D { 0x8000000, 0x2000000 }, [MICROCHIP_PFSOC_PLIC] =3D { 0xc000000, 0x4000000 }, + [MICROCHIP_PFSOC_MMUART0] =3D { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] =3D { 0x20002000, 0x2000 }, [MICROCHIP_PFSOC_MPUCFG] =3D { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART1] =3D { 0x20100000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART2] =3D { 0x20102000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART3] =3D { 0x20104000, 0x1000 }, + [MICROCHIP_PFSOC_MMUART4] =3D { 0x20106000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] =3D { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] =3D { 0x20220000, 0x20000 }, [MICROCHIP_PFSOC_IOSCB_CFG] =3D { 0x37080000, 0x1000 }, @@ -215,6 +223,28 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); =20 + /* MMUARTs */ + s->serial0 =3D mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART0].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART0_IRQ), + serial_hd(0)); + s->serial1 =3D mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART1].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART1_IRQ), + serial_hd(1)); + s->serial2 =3D mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART2].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART2_IRQ), + serial_hd(2)); + s->serial3 =3D mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART3].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART3_IRQ), + serial_hd(3)); + s->serial4 =3D mchp_pfsoc_mmuart_create(system_memory, + memmap[MICROCHIP_PFSOC_MMUART4].base, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), + serial_hd(4)); + /* eNVM */ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.d= ata", memmap[MICROCHIP_PFSOC_ENVM_DATA].size, diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 3292fae..ceb7c16 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -54,3 +54,4 @@ config MICROCHIP_PFSOC select HART select SIFIVE select UNIMP + select MCHP_PFSOC_MMUART --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.28 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KNRT1knn0em3YoOiUyxD5OWMEzQ4yKKyk9M5F8dfP2A=; b=DKGy4yyIn0oTKmZgimtv3xRrSogOKP72xFrZJocXI7oxWIkomHy9IpFe7NPNFifnPC e7DbWSe7LqxHFGccdi9S/M2gOr+iwY9Tk7TY+DGWrdfTal70FqSob1gZKbHkQpUBmC9n VTkxAIuks9XgpEtDS6CON4oUQ33qMp9dkgEplHwEy7C8AO/ir+4iIu6X44PLBLROiPfY dqQRj6si4y9g4mEQKbnu8s+/L0NTl2CMfk0CTyQIEWLdS3tGxNOfdCeMkOriuwurRt59 6oxfuWryb7Kca/IEmWXsfGVx+NbztrInUKlIT2eBgj2HQlwJxbWfJDSpuRgRj2krZ57Z IkMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KNRT1knn0em3YoOiUyxD5OWMEzQ4yKKyk9M5F8dfP2A=; b=QoLuxPixZFFGS2RmiR+W4129MyZ/GbGkKGHgHaDgwcECmul/op2y6DNHfDUU58Woa/ bBGTuibtYsI+Xin4zvoKDMEoQZUGneyOzm1X0HrJdjGjVl7aFelH6pibQaDx1QFElU1c hK5BX3hoEzwF4hljwU8Dgtf84lOYKlHljnR3jpXW84AoMuwUCuRLnOCaGhI3WDY63Jzy 145hZBVEIhz+Ft9KuQBrvCsiuPqYc1JiUgte/thdTeKnm4wxSsyAxZqzx/DED14Jz7Xg 57H7Gqe6yZ6LoBZJfoVz62JUXzfkj95H7JG5cTKd2sCQ2sBruaV6VZtXGhoG/5jB2QMW +/2w== X-Gm-Message-State: AOAM5300tc5gISexHMsECmbb+98v6mAZVC25nG0ZQXSTyIGcbO8mGf4w TOISKQHVGoX63USuqUfBbwA= X-Google-Smtp-Source: ABdhPJzZJdh+QiiAicUL0WVDchAtofgq4A83soSrUM3Ut56qe0aWYPOud1yqgliWENzvr0pxmcu+7Q== X-Received: by 2002:aca:1904:: with SMTP id l4mr2240405oii.67.1598714311773; Sat, 29 Aug 2020 08:18:31 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 07/16] hw/sd: Add Cadence SDHCI emulation Date: Sat, 29 Aug 2020 23:17:31 +0800 Message-Id: <1598714261-8320-8-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=bmeng.cn@gmail.com; helo=mail-oi1-x243.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Bin Meng , qemu-arm@nongnu.org, Alistair Francis , Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Bin Meng Cadence SD/SDIO/eMMC Host Controller (SD4HC) is an SDHCI compatible controller. The SDHCI compatible registers start from offset 0x200, which are called Slot Register Set (SRS) in its datasheet. This creates a Cadence SDHCI model built on top of the existing generic SDHCI model. Cadence specific Host Register Set (HRS) is implemented to make guest software happy. Signed-off-by: Bin Meng Acked-by: Philippe Mathieu-Daud=C3=A9 --- Changes in v2: - change to update hw/sd/meson.build - change the name to "generic-sdhci" when calling object_initialize_child() - add a container MR to simplify out-of-bounds access checks include/hw/sd/cadence_sdhci.h | 47 ++++++++++ hw/sd/cadence_sdhci.c | 193 ++++++++++++++++++++++++++++++++++++++= ++++ hw/sd/Kconfig | 4 + hw/sd/meson.build | 1 + 4 files changed, 245 insertions(+) create mode 100644 include/hw/sd/cadence_sdhci.h create mode 100644 hw/sd/cadence_sdhci.c diff --git a/include/hw/sd/cadence_sdhci.h b/include/hw/sd/cadence_sdhci.h new file mode 100644 index 0000000..cd8288b --- /dev/null +++ b/include/hw/sd/cadence_sdhci.h @@ -0,0 +1,47 @@ +/* + * Cadence SDHCI emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef CADENCE_SDHCI_H +#define CADENCE_SDHCI_H + +#include "hw/sd/sdhci.h" + +#define CADENCE_SDHCI_REG_SIZE 0x100 +#define CADENCE_SDHCI_NUM_REGS (CADENCE_SDHCI_REG_SIZE / sizeof(uint32_t)) + +typedef struct CadenceSDHCIState { + SysBusDevice parent; + + MemoryRegion container; + MemoryRegion iomem; + BusState *bus; + + uint32_t regs[CADENCE_SDHCI_NUM_REGS]; + + SDHCIState sdhci; +} CadenceSDHCIState; + +#define TYPE_CADENCE_SDHCI "cadence.sdhci" +#define CADENCE_SDHCI(obj) OBJECT_CHECK(CadenceSDHCIState, (obj), \ + TYPE_CADENCE_SDHCI) + +#endif /* CADENCE_SDHCI_H */ diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c new file mode 100644 index 0000000..0b371c8 --- /dev/null +++ b/hw/sd/cadence_sdhci.c @@ -0,0 +1,193 @@ +/* + * Cadence SDHCI emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "hw/irq.h" +#include "hw/sd/cadence_sdhci.h" +#include "sdhci-internal.h" + +/* HRS - Host Register Set (specific to Cadence) */ + +#define CADENCE_SDHCI_HRS00 0x00 /* general information */ +#define CADENCE_SDHCI_HRS00_SWR BIT(0) +#define CADENCE_SDHCI_HRS00_POR_VAL 0x00010000 + +#define CADENCE_SDHCI_HRS04 0x10 /* PHY access port */ +#define CADENCE_SDHCI_HRS04_WR BIT(24) +#define CADENCE_SDHCI_HRS04_RD BIT(25) +#define CADENCE_SDHCI_HRS04_ACK BIT(26) + +#define CADENCE_SDHCI_HRS06 0x18 /* eMMC control */ +#define CADENCE_SDHCI_HRS06_TUNE_UP BIT(15) + +/* SRS - Slot Register Set (SDHCI-compatible) */ + +#define CADENCE_SDHCI_SRS_BASE 0x200 + +#define TO_REG(addr) ((addr) / sizeof(uint32_t)) + +static void cadence_sdhci_instance_init(Object *obj) +{ + CadenceSDHCIState *s =3D CADENCE_SDHCI(obj); + + object_initialize_child(OBJECT(s), "generic-sdhci", + &s->sdhci, TYPE_SYSBUS_SDHCI); +} + +static void cadence_sdhci_reset(DeviceState *dev) +{ + CadenceSDHCIState *s =3D CADENCE_SDHCI(dev); + + memset(s->regs, 0, CADENCE_SDHCI_REG_SIZE); + s->regs[TO_REG(CADENCE_SDHCI_HRS00)] =3D CADENCE_SDHCI_HRS00_POR_VAL; + + device_cold_reset(DEVICE(&s->sdhci)); +} + +static uint64_t cadence_sdhci_read(void *opaque, hwaddr addr, unsigned int= size) +{ + CadenceSDHCIState *s =3D opaque; + uint32_t val; + + val =3D s->regs[TO_REG(addr)]; + + return (uint64_t)val; +} + +static void cadence_sdhci_write(void *opaque, hwaddr addr, uint64_t val, + unsigned int size) +{ + CadenceSDHCIState *s =3D opaque; + uint32_t val32 =3D (uint32_t)val; + + switch (addr) { + case CADENCE_SDHCI_HRS00: + /* + * The only writable bit is SWR (software reset) and it automatica= lly + * clears to zero, so essentially this register remains unchanged. + */ + if (val32 & CADENCE_SDHCI_HRS00_SWR) { + cadence_sdhci_reset(DEVICE(s)); + } + + break; + case CADENCE_SDHCI_HRS04: + /* + * Only emulate the ACK bit behavior when read or write transaction + * are requested. + */ + if (val32 & (CADENCE_SDHCI_HRS04_WR | CADENCE_SDHCI_HRS04_RD)) { + val32 |=3D CADENCE_SDHCI_HRS04_ACK; + } else { + val32 &=3D ~CADENCE_SDHCI_HRS04_ACK; + } + + s->regs[TO_REG(addr)] =3D val32; + break; + case CADENCE_SDHCI_HRS06: + if (val32 & CADENCE_SDHCI_HRS06_TUNE_UP) { + val32 &=3D ~CADENCE_SDHCI_HRS06_TUNE_UP; + } + + s->regs[TO_REG(addr)] =3D val32; + break; + default: + s->regs[TO_REG(addr)] =3D val32; + break; + } +} + +static const MemoryRegionOps cadence_sdhci_ops =3D { + .read =3D cadence_sdhci_read, + .write =3D cadence_sdhci_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + } +}; + +static void cadence_sdhci_realize(DeviceState *dev, Error **errp) +{ + CadenceSDHCIState *s =3D CADENCE_SDHCI(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + SysBusDevice *sbd_sdhci =3D SYS_BUS_DEVICE(&s->sdhci); + + memory_region_init(&s->container, OBJECT(s), + "cadence.sdhci-container", 0x1000); + sysbus_init_mmio(sbd, &s->container); + + memory_region_init_io(&s->iomem, OBJECT(s), &cadence_sdhci_ops, + s, TYPE_CADENCE_SDHCI, CADENCE_SDHCI_REG_SIZE); + memory_region_add_subregion(&s->container, 0, &s->iomem); + + sysbus_realize(sbd_sdhci, errp); + memory_region_add_subregion(&s->container, CADENCE_SDHCI_SRS_BASE, + sysbus_mmio_get_region(sbd_sdhci, 0)); + + /* propagate irq and "sd-bus" from generic-sdhci */ + sysbus_pass_irq(sbd, sbd_sdhci); + s->bus =3D qdev_get_child_bus(DEVICE(sbd_sdhci), "sd-bus"); +} + +static const VMStateDescription vmstate_cadence_sdhci =3D { + .name =3D TYPE_CADENCE_SDHCI, + .version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, CadenceSDHCIState, CADENCE_SDHCI_NUM_RE= GS), + VMSTATE_END_OF_LIST(), + }, +}; + +static void cadence_sdhci_class_init(ObjectClass *classp, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(classp); + + dc->desc =3D "Cadence SD/SDIO/eMMC Host Controller (SD4HC)"; + dc->realize =3D cadence_sdhci_realize; + dc->reset =3D cadence_sdhci_reset; + dc->vmsd =3D &vmstate_cadence_sdhci; +} + +static TypeInfo cadence_sdhci_info =3D { + .name =3D TYPE_CADENCE_SDHCI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(CadenceSDHCIState), + .instance_init =3D cadence_sdhci_instance_init, + .class_init =3D cadence_sdhci_class_init, +}; + +static void cadence_sdhci_register_types(void) +{ + type_register_static(&cadence_sdhci_info); +} + +type_init(cadence_sdhci_register_types) diff --git a/hw/sd/Kconfig b/hw/sd/Kconfig index c5e1e55..633b9af 100644 --- a/hw/sd/Kconfig +++ b/hw/sd/Kconfig @@ -19,3 +19,7 @@ config SDHCI_PCI default y if PCI_DEVICES depends on PCI select SDHCI + +config CADENCE_SDHCI + bool + select SDHCI diff --git a/hw/sd/meson.build b/hw/sd/meson.build index b43e59b..9c29691 100644 --- a/hw/sd/meson.build +++ b/hw/sd/meson.build @@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa= 2xx_mmci.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_sdhost.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files('aspeed_sdhci.c')) softmmu_ss.add(when: 'CONFIG_ALLWINNER_H3', if_true: files('allwinner-sdho= st.c')) +softmmu_ss.add(when: 'CONFIG_CADENCE_SDHCI', if_true: files('cadence_sdhci= .c')) --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.32 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=cOdozXckDxNQxCzGLFO11M9mKQ/b8CPjfYZvlO3AVEI=; b=Zdf4qXzYLX5+lCoHQURL6+g+n6uwOm8EJPjkyfSAPlnLxpn8BU63iiJkbHpbCYXLhJ pfJryXp8fO4r5Vd/ExeQx4FUkj52F09nXURnBoOv++mzh+ItKZN2gJ/9QycuW/4curL3 0Obv6gp6Qlxr1cDXaTx4Fy4Lm5Pr+gH2Spram54Y9kuRUjsccLgvJ/ez7RsvUDkK4PFP CIEL6OBC3eXhhNsNhuWSDw5icj3o8TOth69L9zUDAtdzwPIurZDs9qqwlHWFtkz7LMi8 itSkLiy5ngStrAMYh0fAgKea8s/+a6ceHXFyKDdVmOzwlWASE5htMMGinpNhpXIT6PrW nQhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=cOdozXckDxNQxCzGLFO11M9mKQ/b8CPjfYZvlO3AVEI=; b=Kqe6ULFOduANe5vdRrKxEWfZJch87vVIlH73L8n9ehRaVPtj7hLxO5DJVl92j3swRS PWUcxhFkDS82vSmcgH4/aSo1LMybypeIXd231CQLUmeDM+ZAox0+omaVPOhmVZjKEj/I 0dBqhiKgwZZ6jTA5gHxuDnKPdMSNmukLBx6ANfgljQ8rnG2aQk5R0fzX03Nhq5/TR9fi QrHsLEK5Ce9rEJ2WK66nW3vASnOL/IBrpJfodbPA5oAK/WP88Go6HEQ55CNd1mk3DEEy qaHngiSASYOYI8mlIPnp7YXtQw6VwT7GqCq1nEl3nlGc6O33wBGVMMWEFMhlRR0ZPIkJ cKVw== X-Gm-Message-State: AOAM530SM77pvKQTqtyz2GlUSSxveLh+Jy164PbdFrrip3v6IfsBtrWf SavmReglj6BWuZJxPAY+N3o= X-Google-Smtp-Source: ABdhPJy+PB4+AP4v7rCq7mWVr12mo27EAK+rbD2T/NMFxVhhYr8qZAAvVzA1Nm7YN4Ry7fKdKMAJtA== X-Received: by 2002:a9d:7186:: with SMTP id o6mr550721otj.76.1598714315910; Sat, 29 Aug 2020 08:18:35 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 08/16] hw/riscv: microchip_pfsoc: Connect a Cadence SDHCI controller and an SD card Date: Sat, 29 Aug 2020 23:17:32 +0800 Message-Id: <1598714261-8320-9-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Microchip PolarFire SoC integrates one Cadence SDHCI controller. On the Icicle Kit board, one eMMC chip and an external SD card connect to this controller depending on different configuration. As QEMU does not support eMMC yet, we just emulate the SD card configuration. To test this, the Hart Software Services (HSS) should choose the SD card configuration: $ cp boards/icicle-kit-es/def_config.sdcard .config $ make BOARD=3Dicicle-kit-es The SD card image can be built from the Yocto BSP at: https://github.com/polarfire-soc/meta-polarfire-soc-yocto-bsp Note the generated SD card image should be resized before use: $ qemu-img resize /path/to/sdcard.img 4G Launch QEMU with the following command: $ qemu-system-riscv64 -nographic -M microchip-icicle-kit -sd sdcard.img Signed-off-by: Bin Meng --- Changes in v2: - do not initialize TYPE_SYSBUS_SDHCI in the SoC instance_init(), instead move that to the cadence_sdhci model - do not access generic-sdhci's state directly, instead move that to the cadence_sdhci model include/hw/riscv/microchip_pfsoc.h | 4 ++++ hw/riscv/microchip_pfsoc.c | 23 +++++++++++++++++++++++ hw/riscv/Kconfig | 1 + 3 files changed, 28 insertions(+) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index a5efa1d..d810ee8 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -23,6 +23,7 @@ #define HW_MICROCHIP_PFSOC_H =20 #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/sd/cadence_sdhci.h" =20 typedef struct MicrochipPFSoCState { /*< private >*/ @@ -39,6 +40,7 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial2; MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; + CadenceSDHCIState sdhci; } MicrochipPFSoCState; =20 #define TYPE_MICROCHIP_PFSOC "microchip.pfsoc" @@ -74,6 +76,7 @@ enum { MICROCHIP_PFSOC_MMUART0, MICROCHIP_PFSOC_SYSREG, MICROCHIP_PFSOC_MPUCFG, + MICROCHIP_PFSOC_EMMC_SD, MICROCHIP_PFSOC_MMUART1, MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, @@ -85,6 +88,7 @@ enum { }; =20 enum { + MICROCHIP_PFSOC_EMMC_SD_IRQ =3D 88, MICROCHIP_PFSOC_MMUART0_IRQ =3D 90, MICROCHIP_PFSOC_MMUART1_IRQ =3D 91, MICROCHIP_PFSOC_MMUART2_IRQ =3D 92, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index cee959a..0b2e9ca 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -12,6 +12,7 @@ * 1) PLIC (Platform Level Interrupt Controller) * 2) eNVM (Embedded Non-Volatile Memory) * 3) MMUARTs (Multi-Mode UART) + * 4) Cadence eMMC/SDHC controller and an SD card connected to it * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -75,6 +76,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART0] =3D { 0x20000000, 0x1000 }, [MICROCHIP_PFSOC_SYSREG] =3D { 0x20002000, 0x2000 }, [MICROCHIP_PFSOC_MPUCFG] =3D { 0x20005000, 0x1000 }, + [MICROCHIP_PFSOC_EMMC_SD] =3D { 0x20008000, 0x1000 }, [MICROCHIP_PFSOC_MMUART1] =3D { 0x20100000, 0x1000 }, [MICROCHIP_PFSOC_MMUART2] =3D { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] =3D { 0x20104000, 0x1000 }, @@ -111,6 +113,9 @@ static void microchip_pfsoc_soc_instance_init(Object *o= bj) qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", TYPE_RISCV_CPU_SIFIVE_U54); qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); + + object_initialize_child(obj, "sd-controller", &s->sdhci, + TYPE_CADENCE_SDHCI); } =20 static void microchip_pfsoc_soc_realize(DeviceState *dev, Error **errp) @@ -223,6 +228,13 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) memmap[MICROCHIP_PFSOC_MPUCFG].base, memmap[MICROCHIP_PFSOC_MPUCFG].size); =20 + /* SDHCI */ + sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->sdhci), 0, + memmap[MICROCHIP_PFSOC_EMMC_SD].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_EMMC_SD_IRQ)); + /* MMUARTs */ s->serial0 =3D mchp_pfsoc_mmuart_create(system_memory, memmap[MICROCHIP_PFSOC_MMUART0].base, @@ -290,6 +302,7 @@ static void microchip_icicle_kit_machine_init(MachineSt= ate *machine) MicrochipIcicleKitState *s =3D MICROCHIP_ICICLE_KIT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *main_mem =3D g_new(MemoryRegion, 1); + DriveInfo *dinfo =3D drive_get_next(IF_SD); =20 /* Sanity check on RAM size */ if (machine->ram_size < mc->default_ram_size) { @@ -312,6 +325,16 @@ static void microchip_icicle_kit_machine_init(MachineS= tate *machine) =20 /* Load the firmware */ riscv_find_and_load_firmware(machine, BIOS_FILENAME, RESET_VECTOR, NUL= L); + + /* Attach an SD card */ + if (dinfo) { + CadenceSDHCIState *sdhci =3D &(s->soc.sdhci); + DeviceState *card =3D qdev_new(TYPE_SD_CARD); + + qdev_prop_set_drive_err(card, "drive", blk_by_legacy_dinfo(dinfo), + &error_fatal); + qdev_realize_and_unref(card, sdhci->bus, &error_fatal); + } } =20 static void microchip_icicle_kit_machine_class_init(ObjectClass *oc, void = *data) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index ceb7c16..7412db9 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -55,3 +55,4 @@ config MICROCHIP_PFSOC select SIFIVE select UNIMP select MCHP_PFSOC_MMUART + select CADENCE_SDHCI --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Bin Meng , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Microchip PolarFire SoC integrates a DMA engine that supports: * Independent concurrent DMA transfers using 4 DMA channels * Generation of interrupts on various conditions during execution which is actually an IP reused from the SiFive FU540 chip. This creates a model to support both polling and interrupt modes. Signed-off-by: Bin Meng --- Changes in v2: - change to update hw/dma/meson.build - rename the file names to sifive_pdma.[c|h] - update irq number to 8 per the SiFive FU540 manual - fix the register offset for channel 1/2/3 in the read/write ops include/hw/dma/sifive_pdma.h | 57 ++++++++ hw/dma/sifive_pdma.c | 313 +++++++++++++++++++++++++++++++++++++++= ++++ hw/dma/Kconfig | 3 + hw/dma/meson.build | 1 + 4 files changed, 374 insertions(+) create mode 100644 include/hw/dma/sifive_pdma.h create mode 100644 hw/dma/sifive_pdma.c diff --git a/include/hw/dma/sifive_pdma.h b/include/hw/dma/sifive_pdma.h new file mode 100644 index 0000000..fb09383 --- /dev/null +++ b/include/hw/dma/sifive_pdma.h @@ -0,0 +1,57 @@ +/* + * SiFive Platform DMA emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef SIFIVE_PDMA_H +#define SIFIVE_PDMA_H + +struct sifive_pdma_chan { + uint32_t control; + uint32_t next_config; + uint64_t next_bytes; + uint64_t next_dst; + uint64_t next_src; + uint32_t exec_config; + uint64_t exec_bytes; + uint64_t exec_dst; + uint64_t exec_src; + int state; +}; + +#define SIFIVE_PDMA_CHANS 4 +#define SIFIVE_PDMA_IRQS (SIFIVE_PDMA_CHANS * 2) +#define SIFIVE_PDMA_REG_SIZE 0x100000 +#define SIFIVE_PDMA_CHAN_NO(reg) ((reg & (SIFIVE_PDMA_REG_SIZE - 1)) >>= 12) + +typedef struct SiFivePDMAState { + SysBusDevice parent; + MemoryRegion iomem; + qemu_irq irq[SIFIVE_PDMA_IRQS]; + + struct sifive_pdma_chan chan[SIFIVE_PDMA_CHANS]; +} SiFivePDMAState; + +#define TYPE_SIFIVE_PDMA "sifive.pdma" + +#define MCHP_PFSOC_DMA(obj) \ + OBJECT_CHECK(SiFivePDMAState, (obj), TYPE_SIFIVE_PDMA) + +#endif /* SIFIVE_PDMA_H */ diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c new file mode 100644 index 0000000..365bad9 --- /dev/null +++ b/hw/dma/sifive_pdma.c @@ -0,0 +1,313 @@ +/* + * SiFive Platform DMA emulation + * + * Copyright (c) 2020 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 or + * (at your option) version 3 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "hw/hw.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "sysemu/dma.h" +#include "hw/dma/sifive_pdma.h" + +#define DMA_CONTROL 0x000 +#define CONTROL_CLAIM BIT(0) +#define CONTROL_RUN BIT(1) +#define CONTROL_DONE_IE BIT(14) +#define CONTROL_ERR_IE BIT(15) +#define CONTROL_DONE BIT(30) +#define CONTROL_ERR BIT(31) + +#define DMA_NEXT_CONFIG 0x004 +#define CONFIG_REPEAT BIT(2) +#define CONFIG_ORDER BIT(3) +#define CONFIG_WRSZ_SHIFT 24 +#define CONFIG_RDSZ_SHIFT 28 +#define CONFIG_SZ_MASK 0xf + +#define DMA_NEXT_BYTES 0x008 +#define DMA_NEXT_DST 0x010 +#define DMA_NEXT_SRC 0x018 +#define DMA_EXEC_CONFIG 0x104 +#define DMA_EXEC_BYTES 0x108 +#define DMA_EXEC_DST 0x110 +#define DMA_EXEC_SRC 0x118 + +enum dma_chan_state { + DMA_CHAN_STATE_IDLE, + DMA_CHAN_STATE_STARTED, + DMA_CHAN_STATE_ERROR, + DMA_CHAN_STATE_DONE +}; + +static void sifive_pdma_run(SiFivePDMAState *s, int ch) +{ + uint64_t bytes =3D s->chan[ch].next_bytes; + uint64_t dst =3D s->chan[ch].next_dst; + uint64_t src =3D s->chan[ch].next_src; + uint32_t config =3D s->chan[ch].next_config; + int wsize, rsize, size; + uint8_t buf[64]; + int n; + + /* do nothing if bytes to transfer is zero */ + if (!bytes) { + goto error; + } + + /* + * The manual does not describe how the hardware behaviors when + * config.wsize and config.rsize are given different values. + * A common case is memory to memory DMA, and in this case they + * are normally the same. Abort if this expectation fails. + */ + wsize =3D (config >> CONFIG_WRSZ_SHIFT) & CONFIG_SZ_MASK; + rsize =3D (config >> CONFIG_RDSZ_SHIFT) & CONFIG_SZ_MASK; + if (wsize !=3D rsize) { + goto error; + } + + /* + * Calculate the transaction size + * + * size field is base 2 logarithm of DMA transaction size, + * but there is an upper limit of 64 bytes per transaction. + */ + size =3D wsize; + if (size > 6) { + size =3D 6; + } + size =3D 1 << size; + + /* the bytes to transfer should be multiple of transaction size */ + if (bytes % size) { + goto error; + } + + /* indicate a DMA transfer is started */ + s->chan[ch].state =3D DMA_CHAN_STATE_STARTED; + s->chan[ch].control &=3D ~CONTROL_DONE; + s->chan[ch].control &=3D ~CONTROL_ERR; + + /* load the next_ registers into their exec_ counterparts */ + s->chan[ch].exec_config =3D config; + s->chan[ch].exec_bytes =3D bytes; + s->chan[ch].exec_dst =3D dst; + s->chan[ch].exec_src =3D src; + + for (n =3D 0; n < bytes / size; n++) { + cpu_physical_memory_read(s->chan[ch].exec_src, buf, size); + cpu_physical_memory_write(s->chan[ch].exec_dst, buf, size); + s->chan[ch].exec_src +=3D size; + s->chan[ch].exec_dst +=3D size; + s->chan[ch].exec_bytes -=3D size; + } + + /* indicate a DMA transfer is done */ + s->chan[ch].state =3D DMA_CHAN_STATE_DONE; + s->chan[ch].control &=3D ~CONTROL_RUN; + s->chan[ch].control |=3D CONTROL_DONE; + + /* reload exec_ registers if repeat is required */ + if (s->chan[ch].next_config & CONFIG_REPEAT) { + s->chan[ch].exec_bytes =3D bytes; + s->chan[ch].exec_dst =3D dst; + s->chan[ch].exec_src =3D src; + } + + return; + +error: + s->chan[ch].state =3D DMA_CHAN_STATE_ERROR; + s->chan[ch].control |=3D CONTROL_ERR; + return; +} + +static inline void sifive_pdma_update_irq(SiFivePDMAState *s, int ch) +{ + bool done_ie, err_ie; + + done_ie =3D !!(s->chan[ch].control & CONTROL_DONE_IE); + err_ie =3D !!(s->chan[ch].control & CONTROL_ERR_IE); + + if (done_ie && (s->chan[ch].control & CONTROL_DONE)) { + qemu_irq_raise(s->irq[ch * 2]); + } else { + qemu_irq_lower(s->irq[ch * 2]); + } + + if (err_ie && (s->chan[ch].control & CONTROL_ERR)) { + qemu_irq_raise(s->irq[ch * 2 + 1]); + } else { + qemu_irq_lower(s->irq[ch * 2 + 1]); + } + + s->chan[ch].state =3D DMA_CHAN_STATE_IDLE; +} + +static uint64_t sifive_pdma_read(void *opaque, hwaddr offset, unsigned siz= e) +{ + SiFivePDMAState *s =3D opaque; + int ch =3D SIFIVE_PDMA_CHAN_NO(offset); + uint64_t val =3D 0; + + if (ch >=3D SIFIVE_PDMA_CHANS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", + __func__, ch); + return 0; + } + + offset &=3D 0xfff; + switch (offset) { + case DMA_CONTROL: + val =3D s->chan[ch].control; + break; + case DMA_NEXT_CONFIG: + val =3D s->chan[ch].next_config; + break; + case DMA_NEXT_BYTES: + val =3D s->chan[ch].next_bytes; + break; + case DMA_NEXT_DST: + val =3D s->chan[ch].next_dst; + break; + case DMA_NEXT_SRC: + val =3D s->chan[ch].next_src; + break; + case DMA_EXEC_CONFIG: + val =3D s->chan[ch].exec_config; + break; + case DMA_EXEC_BYTES: + val =3D s->chan[ch].exec_bytes; + break; + case DMA_EXEC_DST: + val =3D s->chan[ch].exec_dst; + break; + case DMA_EXEC_SRC: + val =3D s->chan[ch].exec_src; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); + break; + } + + return val; +} + +static void sifive_pdma_write(void *opaque, hwaddr offset, + uint64_t value, unsigned size) +{ + SiFivePDMAState *s =3D opaque; + int ch =3D SIFIVE_PDMA_CHAN_NO(offset); + + if (ch >=3D SIFIVE_PDMA_CHANS) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid channel no %d\n", + __func__, ch); + return; + } + + offset &=3D 0xfff; + switch (offset) { + case DMA_CONTROL: + s->chan[ch].control =3D value; + + if (value & CONTROL_RUN) { + sifive_pdma_run(s, ch); + } + + sifive_pdma_update_irq(s, ch); + break; + case DMA_NEXT_CONFIG: + s->chan[ch].next_config =3D value; + break; + case DMA_NEXT_BYTES: + s->chan[ch].next_bytes =3D value; + break; + case DMA_NEXT_DST: + s->chan[ch].next_dst =3D value; + break; + case DMA_NEXT_SRC: + s->chan[ch].next_src =3D value; + break; + case DMA_EXEC_CONFIG: + case DMA_EXEC_BYTES: + case DMA_EXEC_DST: + case DMA_EXEC_SRC: + /* these are read-only registers */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\= n", + __func__, offset); + break; + } +} + +static const MemoryRegionOps sifive_pdma_ops =3D { + .read =3D sifive_pdma_read, + .write =3D sifive_pdma_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + /* there are 32-bit and 64-bit wide registers */ + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, + } +}; + +static void sifive_pdma_realize(DeviceState *dev, Error **errp) +{ + SiFivePDMAState *s =3D MCHP_PFSOC_DMA(dev); + int i; + + memory_region_init_io(&s->iomem, OBJECT(dev), &sifive_pdma_ops, s, + TYPE_SIFIVE_PDMA, SIFIVE_PDMA_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + + for (i =3D 0; i < SIFIVE_PDMA_IRQS; i++) { + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); + } +} + +static void sifive_pdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->desc =3D "SiFive Platform DMA controller"; + dc->realize =3D sifive_pdma_realize; +} + +static const TypeInfo sifive_pdma_info =3D { + .name =3D TYPE_SIFIVE_PDMA, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(SiFivePDMAState), + .class_init =3D sifive_pdma_class_init, +}; + +static void sifive_pdma_register_types(void) +{ + type_register_static(&sifive_pdma_info); +} + +type_init(sifive_pdma_register_types) diff --git a/hw/dma/Kconfig b/hw/dma/Kconfig index 5c61b67..d67492d 100644 --- a/hw/dma/Kconfig +++ b/hw/dma/Kconfig @@ -20,3 +20,6 @@ config ZYNQ_DEVCFG =20 config STP2000 bool + +config SIFIVE_PDMA + bool diff --git a/hw/dma/meson.build b/hw/dma/meson.build index ff5bb37..b991d76 100644 --- a/hw/dma/meson.build +++ b/hw/dma/meson.build @@ -13,3 +13,4 @@ softmmu_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: f= iles('xlnx-zdma.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_dma.c', 'soc_dma.= c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx_dma.c')) softmmu_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_dma.c')) +softmmu_ss.add(when: 'CONFIG_SIFIVE_PDMA', if_true: files('sifive_pdma.c')) --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.39 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ffO5CG6O0bdtGu4nC+qXhrBBPdnKSoatcxODngYecGI=; b=eTkc3P/tuDqmBKIj5rle32kXIbMOTS+WcVNICJ5ZMITRGoj4/852/NUkJaOakQV3SE TFAgigIGkjr4YcFtJ7EWjmgRd8jyc505QSiJc4mBPSdoHfzbGrf9lHdvRBtc1zY/xG8g LGYEE1kWPRDOx3S7ygm5pdKA18CfQVHilQJoUl0XUmubBRwk/SLZqPjvzXnYCpIDrTS5 VcjgggVqlisSGUYyALJLQIyUDvvIi+H8QfQ+yv7QRI3E0R2Gf30I8t1jkD5l9h1IanWC NsxZG793dYPdPcvggOVksZYwAiIdMjWgHG0L8HcOQShjLuNTgmKKWmYGWsGRpIfLH5/d oa+g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ffO5CG6O0bdtGu4nC+qXhrBBPdnKSoatcxODngYecGI=; b=gPxcz0L0+UZoCVJn51hOWUeRBBKs93JBv4NlvRAkHupbMXbnw6QvmqTWEF/gHUP928 RBpNivfwqr8qvzEIqhIfq5ZyukDhGpdtTauOE1tTpEOANPnpkD1feVqmGx5Irbud3tH1 pjOOY1ovGkf+fqIrnGu0PiA7+tNQsq+e36aSTCKT5d6kYYkJVlydrIkeAVhsWk8XGxC+ n2OGsDZla+0AQQA6cnWaC0/7gEOH4nN0lQCPEOCRvyyKf5o79+mbCyygEe1CyAE5e+Tq iTIGTBQsGXUnwc7Xuam3d2lyh1JquJdSi0f5OrnjXv2NZ6nEr/S84FLbuxS+xmT2g6Yq ItIw== X-Gm-Message-State: AOAM530gIOuKckzAcPaCJN3138nSjORLsMSB4rDST486aoBfq2pNBWtB 7RUrZ/74F4hAbXWCVrabH3E= X-Google-Smtp-Source: ABdhPJwAf5Q8/n+WJy9/GfsgMskSh2Wu2G4J8XutUcmvBTjeu49udYsJcrQBO249L4FF3apXd4jPIw== X-Received: by 2002:aca:48cc:: with SMTP id v195mr2282643oia.57.1598714323317; Sat, 29 Aug 2020 08:18:43 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 10/16] hw/riscv: microchip_pfsoc: Connect a DMA controller Date: Sat, 29 Aug 2020 23:17:34 +0800 Message-Id: <1598714261-8320-11-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::243; envelope-from=bmeng.cn@gmail.com; helo=mail-oi1-x243.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng On the Icicle Kit board, the HSS firmware utilizes the on-chip DMA controller to move the 2nd stage bootloader in the system memory. Let's connect a DMA controller to Microchip PolarFire SoC. Signed-off-by: Bin Meng --- Changes in v2: - connect 8 IRQs to the PLIC include/hw/riscv/microchip_pfsoc.h | 11 +++++++++++ hw/riscv/microchip_pfsoc.c | 15 +++++++++++++++ hw/riscv/Kconfig | 1 + 3 files changed, 27 insertions(+) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index d810ee8..63e7860 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -23,6 +23,7 @@ #define HW_MICROCHIP_PFSOC_H =20 #include "hw/char/mchp_pfsoc_mmuart.h" +#include "hw/dma/sifive_pdma.h" #include "hw/sd/cadence_sdhci.h" =20 typedef struct MicrochipPFSoCState { @@ -40,6 +41,7 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial2; MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; + SiFivePDMAState dma; CadenceSDHCIState sdhci; } MicrochipPFSoCState; =20 @@ -71,6 +73,7 @@ enum { MICROCHIP_PFSOC_BUSERR_UNIT4, MICROCHIP_PFSOC_CLINT, MICROCHIP_PFSOC_L2CC, + MICROCHIP_PFSOC_DMA, MICROCHIP_PFSOC_L2LIM, MICROCHIP_PFSOC_PLIC, MICROCHIP_PFSOC_MMUART0, @@ -88,6 +91,14 @@ enum { }; =20 enum { + MICROCHIP_PFSOC_DMA_IRQ0 =3D 5, + MICROCHIP_PFSOC_DMA_IRQ1 =3D 6, + MICROCHIP_PFSOC_DMA_IRQ2 =3D 7, + MICROCHIP_PFSOC_DMA_IRQ3 =3D 8, + MICROCHIP_PFSOC_DMA_IRQ4 =3D 9, + MICROCHIP_PFSOC_DMA_IRQ5 =3D 10, + MICROCHIP_PFSOC_DMA_IRQ6 =3D 11, + MICROCHIP_PFSOC_DMA_IRQ7 =3D 12, MICROCHIP_PFSOC_EMMC_SD_IRQ =3D 88, MICROCHIP_PFSOC_MMUART0_IRQ =3D 90, MICROCHIP_PFSOC_MMUART1_IRQ =3D 91, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 0b2e9ca..d8ec973 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -13,6 +13,7 @@ * 2) eNVM (Embedded Non-Volatile Memory) * 3) MMUARTs (Multi-Mode UART) * 4) Cadence eMMC/SDHC controller and an SD card connected to it + * 5) SiFive Platform DMA (Direct Memory Access Controller) * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -71,6 +72,7 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_BUSERR_UNIT4] =3D { 0x1704000, 0x1000 }, [MICROCHIP_PFSOC_CLINT] =3D { 0x2000000, 0x10000 }, [MICROCHIP_PFSOC_L2CC] =3D { 0x2010000, 0x1000 }, + [MICROCHIP_PFSOC_DMA] =3D { 0x3000000, 0x100000 }, [MICROCHIP_PFSOC_L2LIM] =3D { 0x8000000, 0x2000000 }, [MICROCHIP_PFSOC_PLIC] =3D { 0xc000000, 0x4000000 }, [MICROCHIP_PFSOC_MMUART0] =3D { 0x20000000, 0x1000 }, @@ -114,6 +116,9 @@ static void microchip_pfsoc_soc_instance_init(Object *o= bj) TYPE_RISCV_CPU_SIFIVE_U54); qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", RESET_VECTOR); =20 + object_initialize_child(obj, "dma-controller", &s->dma, + TYPE_SIFIVE_PDMA); + object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); } @@ -218,6 +223,16 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) memmap[MICROCHIP_PFSOC_PLIC].size); g_free(plic_hart_config); =20 + /* DMA */ + sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, + memmap[MICROCHIP_PFSOC_DMA].base); + for (i =3D 0; i < SIFIVE_PDMA_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, + qdev_get_gpio_in(DEVICE(s->plic), + MICROCHIP_PFSOC_DMA_IRQ0 + i)); + } + /* SYSREG */ create_unimplemented_device("microchip.pfsoc.sysreg", memmap[MICROCHIP_PFSOC_SYSREG].base, diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 7412db9..9032cb0 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -55,4 +55,5 @@ config MICROCHIP_PFSOC select SIFIVE select UNIMP select MCHP_PFSOC_MMUART + select SIFIVE_PDMA select CADENCE_SDHCI --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.43 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=XSd6UA9oGJXgO/Kcn28mrye1Vbs4EU3WILT/MQkdqmw=; b=iRPM103u4ZZKHaEFmDRJvt+VAJIsRj9fNeEZGzCBpYoBz+d4HF+5AThuaNOf2Jcfqn EzkCbCUjw8Kb+XEWJ0j3+xF2jnYUlxMQpxzh2hFy9nBOehtFxWSmzRfjaXP72aijCxdl FcStNKlHNkOHkJ9F+OOeGodMY+rF/wwGXV9G12tdPRHstKXx2fnYSlOq1xDWIxpx3Ilf c137FI9SFXqX7LWBiPdoRBiu1LRx3ecKZRGXpFdfZVh2nim0GijCzXBCKKgs3KGUzVaG y1OjyeRrUF5SplLXGCL8B5+wFZDBM6qSj6dkeFlfVCBNeuQ5koUWhcUAXztBMI46bGIe ZFhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=XSd6UA9oGJXgO/Kcn28mrye1Vbs4EU3WILT/MQkdqmw=; b=qyRnVqbNhYdhumThil8DTtQI+52SgCzgeVT0aXDN5BlaX6ScUp5exGGDM1bVxN0j4z lKsHmc9OM+uh4nfefmtF3w9MV0wbTnaL0azoJvKcvNkGEHsdp3Fm0ELSb5LhI8lAvCTP 3Sga9bsDfNNmxtwxYAI6r7WEBdhom1ezMGRRxWbcM/lnp9Ipk8JKC3h+LMzzObp9kFxz GLc+dXHMSVxCmO+WU53sA7TOlsVGFRixs+scvaygPNraYDP73TcTJsWIcZ6ITpYRKBff tdJ8EZj9RnZ90/gyrUo/zUW+gp9iTaMbMCn+gp/U8NCYiJKz6zimp16EWLyOOPNG2VYV DUqw== X-Gm-Message-State: AOAM5333Oou7/KtZUiaPJ31tEBS8CgI92XYGYfnBg+unMKmw5ixCYXEF 41rn3M1iYozjbqM41HgFaeg= X-Google-Smtp-Source: ABdhPJxFJ5+5X/585nlnrqDj/BnFVtTsIdfFQCiS8zzjPqZbTrAVx+1rS/bx/xkMeNHZQVtZobCTJA== X-Received: by 2002:a9d:4b01:: with SMTP id q1mr2311635otf.15.1598714327353; Sat, 29 Aug 2020 08:18:47 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 11/16] hw/net: cadence_gem: Add a new 'phy-addr' property Date: Sat, 29 Aug 2020 23:17:35 +0800 Message-Id: <1598714261-8320-12-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , Jason Wang , Bin Meng , qemu-arm@nongnu.org, "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the PHY address of the PHY connected to GEM is hard-coded to either 23 (BOARD_PHY_ADDRESS) or 0. This might not be the case for all boards. Add a new 'phy-addr' property so that board can specify the PHY address for each GEM instance. Signed-off-by: Bin Meng --- Changes in v2: - change "phy-addr" default value to BOARD_PHY_ADDRESS include/hw/net/cadence_gem.h | 2 ++ hw/net/cadence_gem.c | 5 +++-- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/include/hw/net/cadence_gem.h b/include/hw/net/cadence_gem.h index 54e646f..01c6189 100644 --- a/include/hw/net/cadence_gem.h +++ b/include/hw/net/cadence_gem.h @@ -73,6 +73,8 @@ typedef struct CadenceGEMState { /* Mask of register bits which are write 1 to clear */ uint32_t regs_w1c[CADENCE_GEM_MAXREG]; =20 + /* PHY address */ + uint8_t phy_addr; /* PHY registers backing store */ uint16_t phy_regs[32]; =20 diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index a93b5c0..d80096b 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset,= unsigned size) uint32_t phy_addr, reg_num; =20 phy_addr =3D (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR= _SHFT; - if (phy_addr =3D=3D BOARD_PHY_ADDRESS || phy_addr =3D=3D 0) { + if (phy_addr =3D=3D s->phy_addr || phy_addr =3D=3D 0) { reg_num =3D (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_RE= G_SHIFT; retval &=3D 0xFFFF0000; retval |=3D gem_phy_read(s, reg_num); @@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, ui= nt64_t val, uint32_t phy_addr, reg_num; =20 phy_addr =3D (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SH= FT; - if (phy_addr =3D=3D BOARD_PHY_ADDRESS || phy_addr =3D=3D 0) { + if (phy_addr =3D=3D s->phy_addr || phy_addr =3D=3D 0) { reg_num =3D (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_S= HIFT; gem_phy_write(s, reg_num, val); } @@ -1682,6 +1682,7 @@ static Property gem_properties[] =3D { DEFINE_NIC_PROPERTIES(CadenceGEMState, conf), DEFINE_PROP_UINT32("revision", CadenceGEMState, revision, GEM_MODID_VALUE), + DEFINE_PROP_UINT8("phy-addr", CadenceGEMState, phy_addr, BOARD_PHY_ADD= RESS), DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState, num_priority_queues, 1), DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState, --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1598714604; cv=none; d=zohomail.com; s=zohoarc; b=DQv18xq7yd0Ssany3HdPsLePRpE4l+szF+oiblUnCvbkKympUTJ+gttQP3UPXbtv5FWedmgO1wCXlqtZov6/cYSi4YQb0Y/g16iyv86I7DJi10ghhwu+l9FM1CI2gaA93k/rgsbtioqVyG+1sI+9uaQXRcISqZzYXpPLNRkwVCc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598714604; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=Ij4Fa5djbJIx/Myvpw/aDERYC9Ay8jdmYeDXjuiJA28=; b=buDj8KVeCvF0OooqUFRbaoZSyRgU0eJrL6h6VoEpR+nU56A/DiAR229gV9DVl6u/kZJ+dwCh6YbR40bPpINB816fBqIuMFpI+OLLgnGx8c7G9uArYux3U6ufiESCZQ7S8od3LJoSSDYEhziXEHife2HrXz6q+/yJ4Fuslda2p6k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598714604930668.0821603749993; Sat, 29 Aug 2020 08:23:24 -0700 (PDT) Received: from localhost ([::1]:50478 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kC2hQ-000123-5q for importer@patchew.org; Sat, 29 Aug 2020 11:23:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kC2d5-0001Hd-SM; Sat, 29 Aug 2020 11:18:56 -0400 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:32862) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kC2d4-0005EL-4A; Sat, 29 Aug 2020 11:18:55 -0400 Received: by mail-ot1-x342.google.com with SMTP id t7so1819697otp.0; Sat, 29 Aug 2020 08:18:51 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ij4Fa5djbJIx/Myvpw/aDERYC9Ay8jdmYeDXjuiJA28=; b=C7Ig8tyD6UItRRKFw1lbBgqf+wXkj4pVryyVnqyQDXiW+VCxNEygzFU62lJHABEIjA b20s7hzjRNYdthDWuMbq5lngPt/xbuT/73gBEk5LaTI7lniYkHwy1dMH1sFZbfMqyLWP BbIxnemECfu1WRHs4xzauPKQ9880rjT/GQoRAOJbQuf5a9rlagKbUr9gv59/aj80CTgf dcIZLuJoiMaB90XtjwunGUXmcZwPG2UkOBC5KD8qQquPZdmHZAZzVleFRN0KFIyQoSl/ mp1NOwAmsMFcRlNKJYbUM3XJtDTc+8a87a1g1uJwjVpZo3rZK/mTdpLnCKM1fjh4I4WG lN4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ij4Fa5djbJIx/Myvpw/aDERYC9Ay8jdmYeDXjuiJA28=; b=EvdNyqriH1+h/Z2c1zJFG3AapjtCFtbc1buCEFYjoAfnRW39G45fK2PZcRY6llktP0 661HzajfEPnBuPnosWzeDE03PiP4+MugAzG1C0KpJvn9FKCTABZjfcyN5T9Z6UM8P/KJ G/2q2nZL8RgYCWJ9Y553e0DUFQK0qMQk7gaCJ/umSYOBLQOeI/w29fQMLEHO5wiAOlNh X9Ym8k7jYp3/lrff1xamaJ1DwoEXv+VqmYjJztoHYd4xTQmCNfg6BVZzKDBYjaM6DBZ8 hJbZgYPQgsb6BxLJ4yzMWKYf8Y7NEyXGFOb9pwc7kaCb1iVwfQszMsOcCsANlq6evKdF zQFQ== X-Gm-Message-State: AOAM532VEqLQSBJRPWW9cyJ1fb1L9PdAGVAY60Eza4tANkViC472uKOo 8kUi4TNkel347xiQ/7ZrUc/dirxt528= X-Google-Smtp-Source: ABdhPJxO7JnGywZSleA7Og55l7T4KD9D1TclrG891Fd45zIu/+mIdxbM38iI626tvV1/2JOtnxJ7Mw== X-Received: by 2002:a9d:734a:: with SMTP id l10mr2346965otk.240.1598714331283; Sat, 29 Aug 2020 08:18:51 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 12/16] hw/arm: xlnx: Set all boards' GEM 'phy-addr' property value to 23 Date: Sat, 29 Aug 2020 23:17:36 +0800 Message-Id: <1598714261-8320-13-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , Jason Wang , Bin Meng , qemu-arm@nongnu.org, "Edgar E. Iglesias" Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng When cadence_gem model was created for Xilinx boards, the PHY address was hard-coded to 23 in the GEM model. Now that we have introduced a property we can use that to tell GEM model what our PHY address is. Change all boards' GEM 'phy-addr' property value to 23, and set the PHY address default value to 0 in the GEM model. Signed-off-by: Bin Meng --- (no changes since v1) hw/arm/xilinx_zynq.c | 1 + hw/arm/xlnx-versal.c | 1 + hw/arm/xlnx-zynqmp.c | 1 + hw/net/cadence_gem.c | 6 +++--- 4 files changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 969ef07..9ffcc56 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -119,6 +119,7 @@ static void gem_init(NICInfo *nd, uint32_t base, qemu_i= rq irq) qemu_check_nic_model(nd, TYPE_CADENCE_GEM); qdev_set_nic_properties(dev, nd); } + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); s =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); sysbus_mmio_map(s, 0, base); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index e3aa4bd..12ba6c4 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -165,6 +165,7 @@ static void versal_create_gems(Versal *s, qemu_irq *pic) qemu_check_nic_model(nd, "cadence_gem"); qdev_set_nic_properties(dev, nd); } + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); object_property_set_int(OBJECT(dev), "num-priority-queues", 2, &error_abort); object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index c435b9d..a85ef4b 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -460,6 +460,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) } object_property_set_int(OBJECT(&s->gem[i]), "revision", GEM_REVISI= ON, &error_abort); + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); object_property_set_int(OBJECT(&s->gem[i]), "num-priority-queues",= 2, &error_abort); if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem[i]), errp)) { diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index d80096b..7a53469 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -250,7 +250,7 @@ #define GEM_PHYMNTNC_REG_SHIFT 18 =20 /* Marvell PHY definitions */ -#define BOARD_PHY_ADDRESS 23 /* PHY address we will emulate a device at= */ +#define BOARD_PHY_ADDRESS 0 /* PHY address we will emulate a device at = */ =20 #define PHY_REG_CONTROL 0 #define PHY_REG_STATUS 1 @@ -1446,7 +1446,7 @@ static uint64_t gem_read(void *opaque, hwaddr offset,= unsigned size) uint32_t phy_addr, reg_num; =20 phy_addr =3D (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR= _SHFT; - if (phy_addr =3D=3D s->phy_addr || phy_addr =3D=3D 0) { + if (phy_addr =3D=3D s->phy_addr) { reg_num =3D (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_RE= G_SHIFT; retval &=3D 0xFFFF0000; retval |=3D gem_phy_read(s, reg_num); @@ -1569,7 +1569,7 @@ static void gem_write(void *opaque, hwaddr offset, ui= nt64_t val, uint32_t phy_addr, reg_num; =20 phy_addr =3D (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SH= FT; - if (phy_addr =3D=3D s->phy_addr || phy_addr =3D=3D 0) { + if (phy_addr =3D=3D s->phy_addr) { reg_num =3D (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_S= HIFT; gem_phy_write(s, reg_num, val); } --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.51 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7R2QHjsRNu1SOw4Rj8O1LUx16kxOsEkbJPfU0SAk6Zs=; b=nc8sIGfZSHaIGKP+cLm23YJBisnqMrA9L/rqfR6UEwUInIpJxDBBa7JGLX1v7mJSnd 1OaKYxd7MYG9/2LS+hznYIPgN2/zM51bG1oAdsYjEDuLYepcFN5iw7fLit2JI3Tc3vHi CQ/K7KPXkNyIbCJ+tN0wQH+Uok7uVK/7MQgbXFbU+CSDYmxSz/cD7800r6RS18F8LmaI bj+klCax23HvffSD3Hq25vTOT6lOEXXqs4SQRf+d25yYe+SUG88ELU+8LUdinwXc8u5l 2Ph5N/YG4umYkDkQ+oULZJyFTV07ZUkT/ZBxacQJgERU3G+mmoGWrccuXgNo2kgOSuRn dF5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7R2QHjsRNu1SOw4Rj8O1LUx16kxOsEkbJPfU0SAk6Zs=; b=UqxcYEwB3NTfag1j2JJisES6ZdwQ2oiH+9+kPSWOqNiaYAq6GN26vW31QY+KOalyU9 veq8XCBbLVEMZPBDT2sr6p4LVaF9qH1uoG5G2ENe+6Ki/b/MA6BTRMa2CvXdBUluwFuv 47wPsvlepjkJobLh4cKKzpNFvbTpXfIsLZwXPmRMP5eTOmzBLAD/FNd25dheps/4Qcqf JgisB0foIFOLgyV+mtcbuEEIlW4Xd/OoqXEWT5XyZfqSDEicRpTDtxbxw4RzwvlPdInc j5ZorORPC1QL1hjPjYHPwItztR5PfpnExh3C6UaY5YgP6Jy5GAGDn3rzfyjKB+dQhFS6 eSNg== X-Gm-Message-State: AOAM530A4FxhCOTjjTJaxISSLIWK/YXxPFSvy/k81ikygMVlM5ek8QFo fDRFAeFZnKp868UADKVoR5o= X-Google-Smtp-Source: ABdhPJy2M+T0Sj6Nxm1uEeX6o0IKwYngHc7muFE8DQmMHSihB1A2d1tsDpr0Otq/hH2UZhI8mdCV2Q== X-Received: by 2002:a05:6830:314c:: with SMTP id c12mr2314528ots.133.1598714334896; Sat, 29 Aug 2020 08:18:54 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 13/16] hw/riscv: microchip_pfsoc: Connect 2 Cadence GEMs Date: Sat, 29 Aug 2020 23:17:37 +0800 Message-Id: <1598714261-8320-14-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::341; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x341.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Microchip PolarFire SoC integrates 2 Candence GEMs to provide IEEE 802.3 standard-compliant 10/100/1000 Mbps ethernet interface. On the Icicle Kit board, GEM0 connects to a PHY at address 8 while GEM1 connects to a PHY at address 9. The 2nd stage bootloader (U-Boot) is using GEM1 by default, so we must specify 2 '-nic' options from the command line in order to get a working ethernet. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/microchip_pfsoc.h | 7 +++++++ hw/riscv/microchip_pfsoc.c | 39 ++++++++++++++++++++++++++++++++++= ++++ 2 files changed, 46 insertions(+) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index 63e7860..6d20853 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -24,6 +24,7 @@ =20 #include "hw/char/mchp_pfsoc_mmuart.h" #include "hw/dma/sifive_pdma.h" +#include "hw/net/cadence_gem.h" #include "hw/sd/cadence_sdhci.h" =20 typedef struct MicrochipPFSoCState { @@ -42,6 +43,8 @@ typedef struct MicrochipPFSoCState { MchpPfSoCMMUartState *serial3; MchpPfSoCMMUartState *serial4; SiFivePDMAState dma; + CadenceGEMState gem0; + CadenceGEMState gem1; CadenceSDHCIState sdhci; } MicrochipPFSoCState; =20 @@ -84,6 +87,8 @@ enum { MICROCHIP_PFSOC_MMUART2, MICROCHIP_PFSOC_MMUART3, MICROCHIP_PFSOC_MMUART4, + MICROCHIP_PFSOC_GEM0, + MICROCHIP_PFSOC_GEM1, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, @@ -99,6 +104,8 @@ enum { MICROCHIP_PFSOC_DMA_IRQ5 =3D 10, MICROCHIP_PFSOC_DMA_IRQ6 =3D 11, MICROCHIP_PFSOC_DMA_IRQ7 =3D 12, + MICROCHIP_PFSOC_GEM0_IRQ =3D 64, + MICROCHIP_PFSOC_GEM1_IRQ =3D 70, MICROCHIP_PFSOC_EMMC_SD_IRQ =3D 88, MICROCHIP_PFSOC_MMUART0_IRQ =3D 90, MICROCHIP_PFSOC_MMUART1_IRQ =3D 91, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index d8ec973..7f25609 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -14,6 +14,7 @@ * 3) MMUARTs (Multi-Mode UART) * 4) Cadence eMMC/SDHC controller and an SD card connected to it * 5) SiFive Platform DMA (Direct Memory Access Controller) + * 6) GEM (Gigabit Ethernet MAC Controller) * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -59,6 +60,9 @@ #define BIOS_FILENAME "hss.bin" #define RESET_VECTOR 0x20220000 =20 +/* GEM version */ +#define GEM_REVISION 0x0107010c + static const struct MemmapEntry { hwaddr base; hwaddr size; @@ -83,6 +87,8 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART2] =3D { 0x20102000, 0x1000 }, [MICROCHIP_PFSOC_MMUART3] =3D { 0x20104000, 0x1000 }, [MICROCHIP_PFSOC_MMUART4] =3D { 0x20106000, 0x1000 }, + [MICROCHIP_PFSOC_GEM0] =3D { 0x20110000, 0x2000 }, + [MICROCHIP_PFSOC_GEM1] =3D { 0x20112000, 0x2000 }, [MICROCHIP_PFSOC_ENVM_CFG] =3D { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] =3D { 0x20220000, 0x20000 }, [MICROCHIP_PFSOC_IOSCB_CFG] =3D { 0x37080000, 0x1000 }, @@ -119,6 +125,9 @@ static void microchip_pfsoc_soc_instance_init(Object *o= bj) object_initialize_child(obj, "dma-controller", &s->dma, TYPE_SIFIVE_PDMA); =20 + object_initialize_child(obj, "gem0", &s->gem0, TYPE_CADENCE_GEM); + object_initialize_child(obj, "gem1", &s->gem1, TYPE_CADENCE_GEM); + object_initialize_child(obj, "sd-controller", &s->sdhci, TYPE_CADENCE_SDHCI); } @@ -134,6 +143,7 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) MemoryRegion *envm_data =3D g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; + NICInfo *nd; int i; =20 sysbus_realize(SYS_BUS_DEVICE(&s->e_cpus), &error_abort); @@ -272,6 +282,35 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_MMUART4_IRQ), serial_hd(4)); =20 + /* GEMs */ + + nd =3D &nd_table[0]; + if (nd->used) { + qemu_check_nic_model(nd, TYPE_CADENCE_GEM); + qdev_set_nic_properties(DEVICE(&s->gem0), nd); + } + nd =3D &nd_table[1]; + if (nd->used) { + qemu_check_nic_model(nd, TYPE_CADENCE_GEM); + qdev_set_nic_properties(DEVICE(&s->gem1), nd); + } + + object_property_set_int(OBJECT(&s->gem0), "revision", GEM_REVISION, er= rp); + object_property_set_int(OBJECT(&s->gem0), "phy-addr", 8, errp); + sysbus_realize(SYS_BUS_DEVICE(&s->gem0), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem0), 0, + memmap[MICROCHIP_PFSOC_GEM0].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem0), 0, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM0_IRQ)); + + object_property_set_int(OBJECT(&s->gem1), "revision", GEM_REVISION, er= rp); + object_property_set_int(OBJECT(&s->gem1), "phy-addr", 9, errp); + sysbus_realize(SYS_BUS_DEVICE(&s->gem1), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem1), 0, + memmap[MICROCHIP_PFSOC_GEM1].base); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, + qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); + /* eNVM */ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.d= ata", memmap[MICROCHIP_PFSOC_ENVM_DATA].size, --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1598714691; cv=none; d=zohomail.com; s=zohoarc; b=VvD55O/lbFFeU3tKlWU0ssxFR05Vf7wkL6wUscy0UEd1qAeWeZl9xJhqLaH2Tub+wjx4FTy/StdiFLubWXbsedd3mLwb22UJ3lmhvB2TUpqpWFNxYvHuqx9zUhuwPU629hL1kaeHsJ9wN/wQ0mPoZJ/o/gQ/WcZBf0aYrBO51GA= ARC-Message-Signature: i=1; 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[147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.55 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=vguI5U0bhxwSlVEjuemI3fZ5Fw5Lf5dy0E2vha1rC8E=; b=iuuDT7epacLK9ZYu/D25eeFlZw4rqt7AXQBYuKEcI3TLvH0HnfwkvEo5/ofsEuX+Lf CAeDfgTHcZ2S2B3WsD5yB5vbii6OK4p2uL/NHiewCGmGNAvedW3srqqtn7tUER4Vxj/o KVX7A3flPOoFx70n4pcpPHMrPw/ONuYzpXWPKyzzrlmVIObi7b7yY8dUfDTOQNKaEuSB V04/n1dp8EDOx75v5RE37L66/a3qkNSDB4fjd7Y6gG0X0uO1/G6dnq6Pw4QvzMV+VumD KGmoAu1qx3g1exJRMqgKfe2Mn8XzuITeuJXa5MtVrHEDlc/6ISCaaBDowXZMiQ4kGmmZ 2Byw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=vguI5U0bhxwSlVEjuemI3fZ5Fw5Lf5dy0E2vha1rC8E=; b=uHZjXsILkRYZL24/nTOkieJ/NZKmed2rk1YdSMaIAvwJum2A6NQUnnrZE38uYoYuZv QJLb5lzM9lrEw53rV/uyvnojtEQkorU6xS/SU3N9xKcAxb6bqfCfLvx97dNKVQPBLQ70 9cRJFarRFxjRBnEGq77XNJ8CquVVV6wMhPVzB0O/UtgcDWX/6P768vQ9p4jw99dn56e3 jnPIOZel8NGAWyn+liN1lyqK8KT65w9L5ZtdVcyDdcTBXtzbrT5FCosAO1pYoJVzBXEj CILd+gJnUZa5CzYRUcEOPBB0Y8oThKwmMSUfKH8rBvH2pmMgEFKhWs9Nx5n1C94SuOkk 60Fg== X-Gm-Message-State: AOAM533CYi2PGbaG91ZzuoaZeatz4ohwpNf6KUdnXfOL6zJ5Q1uegjrZ lJ2QIwJ2XUgm7jpNRwvDTdg= X-Google-Smtp-Source: ABdhPJyd5G4NFygo/nDdwr/Snnz3Bb5I55RfvelEgwfTFNWxyl1Kb/bY17bwDvlyf/bEgJ4juUbFfw== X-Received: by 2002:aca:53c4:: with SMTP id h187mr2209520oib.126.1598714338791; Sat, 29 Aug 2020 08:18:58 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 14/16] hw/riscv: microchip_pfsoc: Hook GPIO controllers Date: Sat, 29 Aug 2020 23:17:38 +0800 Message-Id: <1598714261-8320-15-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::241; envelope-from=bmeng.cn@gmail.com; helo=mail-oi1-x241.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Microchip PolarFire SoC integrates 3 GPIOs controllers. It seems enough to create unimplemented devices to cover their register spaces at this point. With this commit, QEMU can boot to U-Boot (2nd stage bootloader) all the way to the Linux shell login prompt, with a modified HSS (1st stage bootloader). For detailed instructions on how to create images for the Icicle Kit board, please check QEMU RISC-V WiKi page at: https://wiki.qemu.org/Documentation/Platforms/RISCV Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/microchip_pfsoc.h | 3 +++ hw/riscv/microchip_pfsoc.c | 14 ++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/include/hw/riscv/microchip_pfsoc.h b/include/hw/riscv/microchi= p_pfsoc.h index 6d20853..8bfc7e1 100644 --- a/include/hw/riscv/microchip_pfsoc.h +++ b/include/hw/riscv/microchip_pfsoc.h @@ -89,6 +89,9 @@ enum { MICROCHIP_PFSOC_MMUART4, MICROCHIP_PFSOC_GEM0, MICROCHIP_PFSOC_GEM1, + MICROCHIP_PFSOC_GPIO0, + MICROCHIP_PFSOC_GPIO1, + MICROCHIP_PFSOC_GPIO2, MICROCHIP_PFSOC_ENVM_CFG, MICROCHIP_PFSOC_ENVM_DATA, MICROCHIP_PFSOC_IOSCB_CFG, diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 7f25609..11ebdd1 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -89,6 +89,9 @@ static const struct MemmapEntry { [MICROCHIP_PFSOC_MMUART4] =3D { 0x20106000, 0x1000 }, [MICROCHIP_PFSOC_GEM0] =3D { 0x20110000, 0x2000 }, [MICROCHIP_PFSOC_GEM1] =3D { 0x20112000, 0x2000 }, + [MICROCHIP_PFSOC_GPIO0] =3D { 0x20120000, 0x1000 }, + [MICROCHIP_PFSOC_GPIO1] =3D { 0x20121000, 0x1000 }, + [MICROCHIP_PFSOC_GPIO2] =3D { 0x20122000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_CFG] =3D { 0x20200000, 0x1000 }, [MICROCHIP_PFSOC_ENVM_DATA] =3D { 0x20220000, 0x20000 }, [MICROCHIP_PFSOC_IOSCB_CFG] =3D { 0x37080000, 0x1000 }, @@ -311,6 +314,17 @@ static void microchip_pfsoc_soc_realize(DeviceState *d= ev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem1), 0, qdev_get_gpio_in(DEVICE(s->plic), MICROCHIP_PFSOC_GEM1_IRQ)); =20 + /* GPIOs */ + create_unimplemented_device("microchip.pfsoc.gpio0", + memmap[MICROCHIP_PFSOC_GPIO0].base, + memmap[MICROCHIP_PFSOC_GPIO0].size); + create_unimplemented_device("microchip.pfsoc.gpio1", + memmap[MICROCHIP_PFSOC_GPIO1].base, + memmap[MICROCHIP_PFSOC_GPIO1].size); + create_unimplemented_device("microchip.pfsoc.gpio2", + memmap[MICROCHIP_PFSOC_GPIO2].base, + memmap[MICROCHIP_PFSOC_GPIO2].size); + /* eNVM */ memory_region_init_rom(envm_data, OBJECT(dev), "microchip.pfsoc.envm.d= ata", memmap[MICROCHIP_PFSOC_ENVM_DATA].size, --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1598714712; cv=none; d=zohomail.com; s=zohoarc; b=PkexYP3jl5GSUUEhMSs5IuBMo510NRXBB/5tC90oMm2ALt66uUrGJgUsXTZA+LCqCvvJEGUn/4KxpoKg7cIC3KTXdiGI4H7B1hhQ4wUXgJGcWjd4klJ0DJWKLPUraSmwWC7Yz9TOwgUZKOJzihaP0L4mIcoMBYGRp+p+U+x1qrY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1598714712; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=624U7P8Anlw1P84aa7K8bjFHRKvTacCVw6UcCLOjDio=; b=KheJw6wK2IbpZOvhuZPszDDnB4qHkEh6W7hVdueVgHqx4TCjqAbr3xH22myfmS/GN6PO92FACSnB4tGFEpV9yB+UeRZWrPslsf0eePji5PMV2/pXjfD9+8KKuBv2gvZxwLAfRXmriwt8C2/0jMIjm9FDq45Vy1rJQTAN9MQexDs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1598714712385987.4193924228101; Sat, 29 Aug 2020 08:25:12 -0700 (PDT) Received: from localhost ([::1]:57454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1kC2j8-0003s3-Ud for importer@patchew.org; Sat, 29 Aug 2020 11:25:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44722) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1kC2dG-0001UK-3U; Sat, 29 Aug 2020 11:19:06 -0400 Received: from mail-ot1-x342.google.com ([2607:f8b0:4864:20::342]:41332) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1kC2dD-0005GG-Pz; Sat, 29 Aug 2020 11:19:05 -0400 Received: by mail-ot1-x342.google.com with SMTP id a65so1773913otc.8; Sat, 29 Aug 2020 08:19:03 -0700 (PDT) Received: from pek-vx-bsp2.wrs.com (unknown-146-144.windriver.com. [147.11.146.144]) by smtp.gmail.com with ESMTPSA id f50sm58181otf.47.2020.08.29.08.18.59 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 29 Aug 2020 08:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=624U7P8Anlw1P84aa7K8bjFHRKvTacCVw6UcCLOjDio=; b=sxSBSII+d5ZTBs/rvc8Ac0Vefv4Lu8t2xHWoG8dElZQwQewoR9D6YD1TwVteM9MsiM B5MV2NVBWRLlNu9bqwM+EQHeeZt4OsieqxGKL5HRfx6MTf+anZRaMkjCV5gvuQJdAOoD jHpi4x+V5tteZvwpofTG7WJF+TJ/CuPP4XOvMgM6p/tPJSp0DpD/xa56mnxl7gyTdk/p Weft92mysYpc/gAAULvAXDUt/ViHYf4gWxfewN4cV5It7NDc5mfcANqx8Z76bqotyVVT DepFBLIHFaGzW+W9452VmF3I9KomxrWbVxOf7u3rvfdYsB7gBXoTH3iKx9MZ8cmAYbdm KLow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=624U7P8Anlw1P84aa7K8bjFHRKvTacCVw6UcCLOjDio=; b=TPUymYUyS8KGkeD5pjehY2+72ZIg3VGOTGeKXsyCor2Yz8RvSYLwVtJb05KSNkIMig h4gkV67qpMfAe93kU8uAMfv706F9Kbci+hH9NJ5iJTsd+EFekbWavvJ6o11otGmneZrl GoOMQVsqW7TgiSPMCzF67qBYfT+kTMIyYalBolnoQlQEh8v+UYf9sLUQw/mIQjOBb0G7 nTL0LCSRf7UPZJbSTCQIk0jLOZwmPkGAEm2YdeSqKPcDQjNRbxjWV1aaWAEd5Jt2dVfj /Z4W/uC4Btvp8skguc1yJimOvu51Akh9VIETmO5VAwojogpxJVn8bfSQK4iPywwecKvA u06w== X-Gm-Message-State: AOAM531nAxK8d9WF50qE2DV8sQUnUAHg2yisHPfaSG4qPerCki+kAsCw TgbTY45RO95+k5JMVg+wANQnkib8CrM= X-Google-Smtp-Source: ABdhPJwZW42XYNnGbdHjQRMLHqW18IBkIM4H+HP2ijnK//beAkTF7IhoiMambAy86W/6P/vujKRZGQ== X-Received: by 2002:a9d:6e8b:: with SMTP id a11mr2428802otr.363.1598714342374; Sat, 29 Aug 2020 08:19:02 -0700 (PDT) From: Bin Meng To: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v2 15/16] hw/riscv: clint: Avoid using hard-coded timebase frequency Date: Sat, 29 Aug 2020 23:17:39 +0800 Message-Id: <1598714261-8320-16-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> References: <1598714261-8320-1-git-send-email-bmeng.cn@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::342; envelope-from=bmeng.cn@gmail.com; helo=mail-ot1-x342.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the CLINT timestamp is using a hard-coded timebase frequency value SIFIVE_CLINT_TIMEBASE_FREQ. This might not be true for all boards. Add a new 'timebase-freq' property to the CLINT device, and update various functions to accept this as a parameter. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- (no changes since v1) include/hw/riscv/sifive_clint.h | 4 +++- target/riscv/cpu.h | 6 ++++-- hw/riscv/microchip_pfsoc.c | 6 +++++- hw/riscv/sifive_clint.c | 26 +++++++++++++++----------- hw/riscv/sifive_e.c | 3 ++- hw/riscv/sifive_u.c | 3 ++- hw/riscv/spike.c | 3 ++- hw/riscv/virt.c | 3 ++- target/riscv/cpu_helper.c | 4 +++- target/riscv/csr.c | 4 ++-- 10 files changed, 40 insertions(+), 22 deletions(-) diff --git a/include/hw/riscv/sifive_clint.h b/include/hw/riscv/sifive_clin= t.h index 9f5fb3d..a30be0f 100644 --- a/include/hw/riscv/sifive_clint.h +++ b/include/hw/riscv/sifive_clint.h @@ -39,11 +39,13 @@ typedef struct SiFiveCLINTState { uint32_t timecmp_base; uint32_t time_base; uint32_t aperture_size; + uint32_t timebase_freq; } SiFiveCLINTState; =20 DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, - uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime); + uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, + bool provide_rdtime); =20 enum { SIFIVE_SIP_BASE =3D 0x0, diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dc350f0..a003d83 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -219,7 +219,8 @@ struct CPURISCVState { pmp_table_t pmp_state; =20 /* machine specific rdtime callback */ - uint64_t (*rdtime_fn)(void); + uint64_t (*rdtime_fn)(uint32_t); + uint32_t rdtime_fn_arg; =20 /* True if in debugger mode. */ bool debugger; @@ -349,7 +350,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts); uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)); +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), + uint32_t arg); #endif void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv); =20 diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 11ebdd1..da6bd29 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -60,6 +60,9 @@ #define BIOS_FILENAME "hss.bin" #define RESET_VECTOR 0x20220000 =20 +/* CLINT timebase frequency */ +#define CLINT_TIMEBASE_FREQ 1000000 + /* GEM version */ #define GEM_REVISION 0x0107010c =20 @@ -187,7 +190,8 @@ static void microchip_pfsoc_soc_realize(DeviceState *de= v, Error **errp) /* CLINT */ sifive_clint_create(memmap[MICROCHIP_PFSOC_CLINT].base, memmap[MICROCHIP_PFSOC_CLINT].size, 0, ms->smp.cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + CLINT_TIMEBASE_FREQ, false); =20 /* L2 cache controller */ create_unimplemented_device("microchip.pfsoc.l2cc", diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 15e13d5..fa1ddf2 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -29,22 +29,23 @@ #include "hw/riscv/sifive_clint.h" #include "qemu/timer.h" =20 -static uint64_t cpu_riscv_read_rtc(void) +static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - SIFIVE_CLINT_TIMEBASE_FREQ, NANOSECONDS_PER_SECOND); + timebase_freq, NANOSECONDS_PER_SECOND); } =20 /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <=3D current timer value. */ -static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value) +static void sifive_clint_write_timecmp(RISCVCPU *cpu, uint64_t value, + uint32_t timebase_freq) { uint64_t next; uint64_t diff; =20 - uint64_t rtc_r =3D cpu_riscv_read_rtc(); + uint64_t rtc_r =3D cpu_riscv_read_rtc(timebase_freq); =20 cpu->env.timecmp =3D value; if (cpu->env.timecmp <=3D rtc_r) { @@ -59,7 +60,7 @@ static void sifive_clint_write_timecmp(RISCVCPU *cpu, uin= t64_t value) diff =3D cpu->env.timecmp - rtc_r; /* back to ns (note args switched in muldiv64) */ next =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - muldiv64(diff, NANOSECONDS_PER_SECOND, SIFIVE_CLINT_TIMEBASE_FREQ); + muldiv64(diff, NANOSECONDS_PER_SECOND, timebase_freq); timer_mod(cpu->env.timer, next); } =20 @@ -112,10 +113,10 @@ static uint64_t sifive_clint_read(void *opaque, hwadd= r addr, unsigned size) } } else if (addr =3D=3D clint->time_base) { /* time_lo */ - return cpu_riscv_read_rtc() & 0xFFFFFFFF; + return cpu_riscv_read_rtc(clint->timebase_freq) & 0xFFFFFFFF; } else if (addr =3D=3D clint->time_base + 4) { /* time_hi */ - return (cpu_riscv_read_rtc() >> 32) & 0xFFFFFFFF; + return (cpu_riscv_read_rtc(clint->timebase_freq) >> 32) & 0xFFFFFF= FF; } =20 error_report("clint: invalid read: %08x", (uint32_t)addr); @@ -153,13 +154,13 @@ static void sifive_clint_write(void *opaque, hwaddr a= ddr, uint64_t value, /* timecmp_lo */ uint64_t timecmp_hi =3D env->timecmp >> 32; sifive_clint_write_timecmp(RISCV_CPU(cpu), - timecmp_hi << 32 | (value & 0xFFFFFFFF)); + timecmp_hi << 32 | (value & 0xFFFFFFFF), clint->timebase_f= req); return; } else if ((addr & 0x7) =3D=3D 4) { /* timecmp_hi */ uint64_t timecmp_lo =3D env->timecmp; sifive_clint_write_timecmp(RISCV_CPU(cpu), - value << 32 | (timecmp_lo & 0xFFFFFFFF)); + value << 32 | (timecmp_lo & 0xFFFFFFFF), clint->timebase_f= req); } else { error_report("clint: invalid timecmp write: %08x", (uint32_t)a= ddr); } @@ -194,6 +195,7 @@ static Property sifive_clint_properties[] =3D { DEFINE_PROP_UINT32("timecmp-base", SiFiveCLINTState, timecmp_base, 0), DEFINE_PROP_UINT32("time-base", SiFiveCLINTState, time_base, 0), DEFINE_PROP_UINT32("aperture-size", SiFiveCLINTState, aperture_size, 0= ), + DEFINE_PROP_UINT32("timebase-freq", SiFiveCLINTState, timebase_freq, 0= ), DEFINE_PROP_END_OF_LIST(), }; =20 @@ -232,7 +234,8 @@ type_init(sifive_clint_register_types) */ DeviceState *sifive_clint_create(hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t sip_base, - uint32_t timecmp_base, uint32_t time_base, bool provide_rdtime) + uint32_t timecmp_base, uint32_t time_base, uint32_t timebase_freq, + bool provide_rdtime) { int i; for (i =3D 0; i < num_harts; i++) { @@ -242,7 +245,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr si= ze, continue; } if (provide_rdtime) { - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc); + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq= ); } env->timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &sifive_clint_timer_cb, cpu); @@ -256,6 +259,7 @@ DeviceState *sifive_clint_create(hwaddr addr, hwaddr si= ze, qdev_prop_set_uint32(dev, "timecmp-base", timecmp_base); qdev_prop_set_uint32(dev, "time-base", time_base); qdev_prop_set_uint32(dev, "aperture-size", size); + qdev_prop_set_uint32(dev, "timebase-freq", timebase_freq); sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); return dev; diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index cd7560d..36ccfb2 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -213,7 +213,8 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) memmap[SIFIVE_E_PLIC].size); sifive_clint_create(memmap[SIFIVE_E_CLINT].base, memmap[SIFIVE_E_CLINT].size, 0, ms->smp.cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, false); create_unimplemented_device("riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 404d5e6..2bc3992 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -706,7 +706,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ= )); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, 0, ms->smp.cpus, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, false); =20 if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) { return; diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 56f5fe7..b54a396 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -242,7 +242,8 @@ static void spike_board_init(MachineState *machine) sifive_clint_create( memmap[SPIKE_CLINT].base + i * memmap[SPIKE_CLINT].size, memmap[SPIKE_CLINT].size, base_hartid, hart_count, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, false); } =20 /* register system main memory (actual RAM) */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6fca513..c67a910 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -541,7 +541,8 @@ static void virt_machine_init(MachineState *machine) sifive_clint_create( memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, memmap[VIRT_CLINT].size, base_hartid, hart_count, - SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, true); + SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, + SIFIVE_CLINT_TIMEBASE_FREQ, true); =20 /* Per-socket PLIC hart topology configuration string */ plic_hart_config_len =3D diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index dc7ae3e..b0b91d4 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -276,9 +276,11 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t = mask, uint32_t value) return old; } =20 -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void)) +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), + uint32_t arg) { env->rdtime_fn =3D fn; + env->rdtime_fn_arg =3D arg; } =20 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 200001d..26ae347 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -351,7 +351,7 @@ static int read_time(CPURISCVState *env, int csrno, tar= get_ulong *val) return -RISCV_EXCP_ILLEGAL_INST; } =20 - *val =3D env->rdtime_fn() + delta; + *val =3D env->rdtime_fn(env->rdtime_fn_arg) + delta; return 0; } =20 @@ -364,7 +364,7 @@ static int read_timeh(CPURISCVState *env, int csrno, ta= rget_ulong *val) return -RISCV_EXCP_ILLEGAL_INST; } =20 - *val =3D (env->rdtime_fn() + delta) >> 32; + *val =3D (env->rdtime_fn(env->rdtime_fn_arg) + delta) >> 32; return 0; } #endif --=20 2.7.4 From nobody Sat May 18 15:38:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1598714520; cv=none; d=zohomail.com; s=zohoarc; b=hbAuvfn42jl0+rpCz/yFtUx29m++fQ6A1B6rAO+z9BT9BmU5cCYmOCISxKUfRtU1UDzrMOvZS+3fFjZVkfEBI5vnZcOqvUgSTVV/CpV60KNglw4FOuHUi/+pEmABOaU2KIZpxxbexbxM4GlDWeQWTakHF6hBwfOcnWckt8/pGFc= ARC-Message-Signature: i=1; a=rsa-sha256; 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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bastian Koppelmann , Bin Meng , Palmer Dabbelt , Sagar Karandikar Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng SiFive FU540 SoC integrates a platform DMA controller with 4 DMA channels. This connects the exsiting SiFive PDMA model to the SoC, and adds its device tree data as well. Signed-off-by: Bin Meng --- (no changes since v1) include/hw/riscv/sifive_u.h | 11 +++++++++++ hw/riscv/sifive_u.c | 30 ++++++++++++++++++++++++++++++ hw/riscv/Kconfig | 1 + 3 files changed, 42 insertions(+) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index d3c0c00..793000a 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -19,6 +19,7 @@ #ifndef HW_SIFIVE_U_H #define HW_SIFIVE_U_H =20 +#include "hw/dma/sifive_pdma.h" #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_cpu.h" @@ -43,6 +44,7 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SIFIVEGPIOState gpio; SiFiveUOTPState otp; + SiFivePDMAState dma; CadenceGEMState gem; =20 uint32_t serial; @@ -72,6 +74,7 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_L2CC, + SIFIVE_U_PDMA, SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, @@ -108,6 +111,14 @@ enum { SIFIVE_U_GPIO_IRQ13 =3D 20, SIFIVE_U_GPIO_IRQ14 =3D 21, SIFIVE_U_GPIO_IRQ15 =3D 22, + SIFIVE_U_PDMA_IRQ0 =3D 23, + SIFIVE_U_PDMA_IRQ1 =3D 24, + SIFIVE_U_PDMA_IRQ2 =3D 25, + SIFIVE_U_PDMA_IRQ3 =3D 26, + SIFIVE_U_PDMA_IRQ4 =3D 27, + SIFIVE_U_PDMA_IRQ5 =3D 28, + SIFIVE_U_PDMA_IRQ6 =3D 29, + SIFIVE_U_PDMA_IRQ7 =3D 30, SIFIVE_U_GEM_IRQ =3D 0x35 }; =20 diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 2bc3992..7997537 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -14,6 +14,7 @@ * 4) GPIO (General Purpose Input/Output Controller) * 5) OTP (One-Time Programmable) memory with stored serial number * 6) GEM (Gigabit Ethernet Controller) and management block + * 7) DMA (Direct Memory Access Controller) * * This board currently generates devicetree dynamically that indicates at= least * two harts and up to five harts. @@ -73,6 +74,7 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] =3D { 0x1000, 0xf000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, [SIFIVE_U_L2CC] =3D { 0x2010000, 0x1000 }, + [SIFIVE_U_PDMA] =3D { 0x3000000, 0x100000 }, [SIFIVE_U_L2LIM] =3D { 0x8000000, 0x2000000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, @@ -303,6 +305,22 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); g_free(nodename); =20 + nodename =3D g_strdup_printf("/soc/dma@%lx", + (long)memmap[SIFIVE_U_PDMA].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "#dma-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", + SIFIVE_U_PDMA_IRQ0, SIFIVE_U_PDMA_IRQ1, SIFIVE_U_PDMA_IRQ2, + SIFIVE_U_PDMA_IRQ3, SIFIVE_U_PDMA_IRQ4, SIFIVE_U_PDMA_IRQ5, + SIFIVE_U_PDMA_IRQ6, SIFIVE_U_PDMA_IRQ7); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_PDMA].base, + 0x0, memmap[SIFIVE_U_PDMA].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-pdma"); + g_free(nodename); + nodename =3D g_strdup_printf("/soc/cache-controller@%lx", (long)memmap[SIFIVE_U_L2CC].base); qemu_fdt_add_subnode(fdt, nodename); @@ -627,6 +645,7 @@ static void sifive_u_soc_instance_init(Object *obj) object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); object_initialize_child(obj, "gem", &s->gem, TYPE_CADENCE_GEM); object_initialize_child(obj, "gpio", &s->gpio, TYPE_SIFIVE_GPIO); + object_initialize_child(obj, "pdma", &s->dma, TYPE_SIFIVE_PDMA); } =20 static void sifive_u_soc_realize(DeviceState *dev, Error **errp) @@ -730,6 +749,17 @@ static void sifive_u_soc_realize(DeviceState *dev, Err= or **errp) SIFIVE_U_GPIO_IRQ0 + i)); } =20 + /* PDMA */ + sysbus_realize(SYS_BUS_DEVICE(&s->dma), errp); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->dma), 0, memmap[SIFIVE_U_PDMA].base= ); + + /* Connect PDMA interrupts to the PLIC */ + for (i =3D 0; i < SIFIVE_PDMA_IRQS; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dma), i, + qdev_get_gpio_in(DEVICE(s->plic), + SIFIVE_U_PDMA_IRQ0 + i)); + } + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) { return; diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 9032cb0..e53ab1e 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -22,6 +22,7 @@ config SIFIVE_U select CADENCE select HART select SIFIVE + select SIFIVE_PDMA select UNIMP =20 config SPIKE --=20 2.7.4