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charset="utf-8" The names of some of the svm_x86_ops functions do not have a corresponding 'svm_' prefix. Generate the names using a macro so that the names are conformant. Fixing the naming will help in better readability and maintenance of the code. Suggested-by: Vitaly Kuznetsov Suggested-by: Paolo Bonzini Signed-off-by: Sean Christopherson Signed-off-by: Krish Sadhukhan --- arch/x86/kvm/svm/avic.c | 4 +- arch/x86/kvm/svm/nested.c | 2 +- arch/x86/kvm/svm/sev.c | 6 +- arch/x86/kvm/svm/svm.c | 218 +++++++++++++++++++++++-------------------= ---- arch/x86/kvm/svm/svm.h | 8 +- 5 files changed, 120 insertions(+), 118 deletions(-) diff --git a/arch/x86/kvm/svm/avic.c b/arch/x86/kvm/svm/avic.c index e80daa9..619391e 100644 --- a/arch/x86/kvm/svm/avic.c +++ b/arch/x86/kvm/svm/avic.c @@ -579,7 +579,7 @@ int avic_init_vcpu(struct vcpu_svm *svm) return ret; } =20 -void avic_post_state_restore(struct kvm_vcpu *vcpu) +void svm_avic_post_state_restore(struct kvm_vcpu *vcpu) { if (avic_handle_apic_id_update(vcpu) !=3D 0) return; @@ -660,7 +660,7 @@ void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu) * we need to check and update the AVIC logical APIC ID table * accordingly before re-activating. */ - avic_post_state_restore(vcpu); + svm_avic_post_state_restore(vcpu); vmcb->control.int_ctl |=3D AVIC_ENABLE_MASK; } else { vmcb->control.int_ctl &=3D ~AVIC_ENABLE_MASK; diff --git a/arch/x86/kvm/svm/nested.c b/arch/x86/kvm/svm/nested.c index 6bceafb..3be6256 100644 --- a/arch/x86/kvm/svm/nested.c +++ b/arch/x86/kvm/svm/nested.c @@ -348,7 +348,7 @@ static void nested_prepare_vmcb_control(struct vcpu_svm= *svm) /* Guest paging mode is active - reset mmu */ kvm_mmu_reset_context(&svm->vcpu); =20 - svm_flush_tlb(&svm->vcpu); + svm_tlb_flush(&svm->vcpu); =20 svm->vmcb->control.tsc_offset =3D svm->vcpu.arch.tsc_offset =3D svm->vcpu.arch.l1_tsc_offset + svm->nested.ctl.tsc_offset; diff --git a/arch/x86/kvm/svm/sev.c b/arch/x86/kvm/svm/sev.c index 5573a97..1ca9f60 100644 --- a/arch/x86/kvm/svm/sev.c +++ b/arch/x86/kvm/svm/sev.c @@ -969,7 +969,7 @@ int svm_mem_enc_op(struct kvm *kvm, void __user *argp) return r; } =20 -int svm_register_enc_region(struct kvm *kvm, +int svm_mem_enc_register_region(struct kvm *kvm, struct kvm_enc_region *range) { struct kvm_sev_info *sev =3D &to_kvm_svm(kvm)->sev_info; @@ -1038,8 +1038,8 @@ static void __unregister_enc_region_locked(struct kvm= *kvm, kfree(region); } =20 -int svm_unregister_enc_region(struct kvm *kvm, - struct kvm_enc_region *range) +int svm_mem_enc_unregister_region(struct kvm *kvm, + struct kvm_enc_region *range) { struct enc_region *region; int ret; diff --git a/arch/x86/kvm/svm/svm.c b/arch/x86/kvm/svm/svm.c index 24755eb..d63181e 100644 --- a/arch/x86/kvm/svm/svm.c +++ b/arch/x86/kvm/svm/svm.c @@ -254,7 +254,7 @@ static inline void invlpga(unsigned long addr, u32 asid) asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr)); } =20 -static int get_npt_level(struct kvm_vcpu *vcpu) +static int svm_get_tdp_level(struct kvm_vcpu *vcpu) { #ifdef CONFIG_X86_64 return PT64_ROOT_4LEVEL; @@ -312,7 +312,7 @@ static void svm_set_interrupt_shadow(struct kvm_vcpu *v= cpu, int mask) =20 } =20 -static int skip_emulated_instruction(struct kvm_vcpu *vcpu) +static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -351,7 +351,7 @@ static void svm_queue_exception(struct kvm_vcpu *vcpu) * raises a fault that is not intercepted. Still better than * failing in all cases. */ - (void)skip_emulated_instruction(&svm->vcpu); + (void)svm_skip_emulated_instruction(&svm->vcpu); rip =3D kvm_rip_read(&svm->vcpu); svm->int3_rip =3D rip + svm->vmcb->save.cs.base; svm->int3_injected =3D rip - old_rip; @@ -1153,7 +1153,7 @@ static void svm_vcpu_reset(struct kvm_vcpu *vcpu, boo= l init_event) avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE); } =20 -static int svm_create_vcpu(struct kvm_vcpu *vcpu) +static int svm_vcpu_create(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm; struct page *page; @@ -1232,7 +1232,7 @@ static void svm_clear_current_vmcb(struct vmcb *vmcb) cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL); } =20 -static void svm_free_vcpu(struct kvm_vcpu *vcpu) +static void svm_vcpu_free(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -1585,7 +1585,7 @@ int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long = cr4) return 1; =20 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE)) - svm_flush_tlb(vcpu); + svm_tlb_flush(vcpu); =20 vcpu->arch.cr4 =3D cr4; if (!npt_enabled) @@ -1627,7 +1627,7 @@ static void svm_set_segment(struct kvm_vcpu *vcpu, mark_dirty(svm->vmcb, VMCB_SEG); } =20 -static void update_bp_intercept(struct kvm_vcpu *vcpu) +static void svm_update_bp_intercept(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -2143,7 +2143,7 @@ static int task_switch_interception(struct vcpu_svm *= svm) int_type =3D=3D SVM_EXITINTINFO_TYPE_SOFT || (int_type =3D=3D SVM_EXITINTINFO_TYPE_EXEPT && (int_vec =3D=3D OF_VECTOR || int_vec =3D=3D BP_VECTOR))) { - if (!skip_emulated_instruction(&svm->vcpu)) + if (!svm_skip_emulated_instruction(&svm->vcpu)) return 0; } =20 @@ -2909,7 +2909,7 @@ static void svm_get_exit_info(struct kvm_vcpu *vcpu, = u64 *info1, u64 *info2) *info2 =3D control->exit_info_2; } =20 -static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath) +static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath) { struct vcpu_svm *svm =3D to_svm(vcpu); struct kvm_run *kvm_run =3D vcpu->run; @@ -3023,7 +3023,7 @@ static void svm_inject_nmi(struct kvm_vcpu *vcpu) ++vcpu->stat.nmi_injections; } =20 -static void svm_set_irq(struct kvm_vcpu *vcpu) +static void svm_inject_irq(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -3036,7 +3036,7 @@ static void svm_set_irq(struct kvm_vcpu *vcpu) SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR; } =20 -static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr) +static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int i= rr) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -3145,7 +3145,7 @@ static int svm_interrupt_allowed(struct kvm_vcpu *vcp= u, bool for_injection) return !svm_interrupt_blocked(vcpu); } =20 -static void enable_irq_window(struct kvm_vcpu *vcpu) +static void svm_enable_irq_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -3169,7 +3169,7 @@ static void enable_irq_window(struct kvm_vcpu *vcpu) } } =20 -static void enable_nmi_window(struct kvm_vcpu *vcpu) +static void svm_enable_nmi_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -3202,7 +3202,7 @@ static int svm_set_identity_map_addr(struct kvm *kvm,= u64 ident_addr) return 0; } =20 -void svm_flush_tlb(struct kvm_vcpu *vcpu) +void svm_tlb_flush(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -3219,7 +3219,7 @@ void svm_flush_tlb(struct kvm_vcpu *vcpu) svm->asid_generation--; } =20 -static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva) +static void svm_tlb_flush_gva(struct kvm_vcpu *vcpu, gva_t gva) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -3857,7 +3857,7 @@ static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, c= onst char *smstate) return 0; } =20 -static void enable_smi_window(struct kvm_vcpu *vcpu) +static void svm_enable_smi_window(struct kvm_vcpu *vcpu) { struct vcpu_svm *svm =3D to_svm(vcpu); =20 @@ -3968,124 +3968,126 @@ static int svm_vm_init(struct kvm *kvm) return 0; } =20 +#define KVM_X86_OP(name) .name =3D svm_##name + static struct kvm_x86_ops svm_x86_ops __initdata =3D { - .hardware_teardown =3D svm_hardware_teardown, - .hardware_enable =3D svm_hardware_enable, - .hardware_disable =3D svm_hardware_disable, - .cpu_has_accelerated_tpr =3D svm_cpu_has_accelerated_tpr, - .has_emulated_msr =3D svm_has_emulated_msr, + KVM_X86_OP(hardware_teardown), + KVM_X86_OP(hardware_enable), + KVM_X86_OP(hardware_disable), + KVM_X86_OP(cpu_has_accelerated_tpr), + KVM_X86_OP(has_emulated_msr), =20 - .vcpu_create =3D svm_create_vcpu, - .vcpu_free =3D svm_free_vcpu, - .vcpu_reset =3D svm_vcpu_reset, + KVM_X86_OP(vcpu_create), + KVM_X86_OP(vcpu_free), + KVM_X86_OP(vcpu_reset), =20 .vm_size =3D sizeof(struct kvm_svm), - .vm_init =3D svm_vm_init, - .vm_destroy =3D svm_vm_destroy, - - .prepare_guest_switch =3D svm_prepare_guest_switch, - .vcpu_load =3D svm_vcpu_load, - .vcpu_put =3D svm_vcpu_put, - .vcpu_blocking =3D svm_vcpu_blocking, - .vcpu_unblocking =3D svm_vcpu_unblocking, - - .update_bp_intercept =3D update_bp_intercept, - .get_msr_feature =3D svm_get_msr_feature, - .get_msr =3D svm_get_msr, - .set_msr =3D svm_set_msr, - .get_segment_base =3D svm_get_segment_base, - .get_segment =3D svm_get_segment, - .set_segment =3D svm_set_segment, - .get_cpl =3D svm_get_cpl, + KVM_X86_OP(vm_init), + KVM_X86_OP(vm_destroy), + + KVM_X86_OP(prepare_guest_switch), + KVM_X86_OP(vcpu_load), + KVM_X86_OP(vcpu_put), + KVM_X86_OP(vcpu_blocking), + KVM_X86_OP(vcpu_unblocking), + + KVM_X86_OP(update_bp_intercept), + KVM_X86_OP(get_msr_feature), + KVM_X86_OP(get_msr), + KVM_X86_OP(set_msr), + KVM_X86_OP(get_segment_base), + KVM_X86_OP(get_segment), + KVM_X86_OP(set_segment), + KVM_X86_OP(get_cpl), .get_cs_db_l_bits =3D kvm_get_cs_db_l_bits, - .set_cr0 =3D svm_set_cr0, - .set_cr4 =3D svm_set_cr4, - .set_efer =3D svm_set_efer, - .get_idt =3D svm_get_idt, - .set_idt =3D svm_set_idt, - .get_gdt =3D svm_get_gdt, - .set_gdt =3D svm_set_gdt, - .set_dr7 =3D svm_set_dr7, - .sync_dirty_debug_regs =3D svm_sync_dirty_debug_regs, - .cache_reg =3D svm_cache_reg, - .get_rflags =3D svm_get_rflags, - .set_rflags =3D svm_set_rflags, - - .tlb_flush_all =3D svm_flush_tlb, - .tlb_flush_current =3D svm_flush_tlb, - .tlb_flush_gva =3D svm_flush_tlb_gva, - .tlb_flush_guest =3D svm_flush_tlb, - - .vcpu_run =3D svm_vcpu_run, - .handle_exit =3D handle_exit, - .skip_emulated_instruction =3D skip_emulated_instruction, + KVM_X86_OP(set_cr0), + KVM_X86_OP(set_cr4), + KVM_X86_OP(set_efer), + KVM_X86_OP(get_idt), + KVM_X86_OP(set_idt), + KVM_X86_OP(get_gdt), + KVM_X86_OP(set_gdt), + KVM_X86_OP(set_dr7), + KVM_X86_OP(sync_dirty_debug_regs), + KVM_X86_OP(cache_reg), + KVM_X86_OP(get_rflags), + KVM_X86_OP(set_rflags), + + .tlb_flush_all =3D svm_tlb_flush, + .tlb_flush_current =3D svm_tlb_flush, + KVM_X86_OP(tlb_flush_gva), + .tlb_flush_guest =3D svm_tlb_flush, + + KVM_X86_OP(vcpu_run), + KVM_X86_OP(handle_exit), + KVM_X86_OP(skip_emulated_instruction), .update_emulated_instruction =3D NULL, - .set_interrupt_shadow =3D svm_set_interrupt_shadow, - .get_interrupt_shadow =3D svm_get_interrupt_shadow, - .patch_hypercall =3D svm_patch_hypercall, - .inject_irq =3D svm_set_irq, - .inject_nmi =3D svm_inject_nmi, - .queue_exception =3D svm_queue_exception, - .cancel_injection =3D svm_cancel_injection, - .interrupt_allowed =3D svm_interrupt_allowed, - .nmi_allowed =3D svm_nmi_allowed, - .get_nmi_mask =3D svm_get_nmi_mask, - .set_nmi_mask =3D svm_set_nmi_mask, - .enable_nmi_window =3D enable_nmi_window, - .enable_irq_window =3D enable_irq_window, - .update_cr8_intercept =3D update_cr8_intercept, - .set_virtual_apic_mode =3D svm_set_virtual_apic_mode, - .refresh_apicv_exec_ctrl =3D svm_refresh_apicv_exec_ctrl, - .check_apicv_inhibit_reasons =3D svm_check_apicv_inhibit_reasons, - .pre_update_apicv_exec_ctrl =3D svm_pre_update_apicv_exec_ctrl, - .load_eoi_exitmap =3D svm_load_eoi_exitmap, - .hwapic_irr_update =3D svm_hwapic_irr_update, - .hwapic_isr_update =3D svm_hwapic_isr_update, + KVM_X86_OP(set_interrupt_shadow), + KVM_X86_OP(get_interrupt_shadow), + KVM_X86_OP(patch_hypercall), + KVM_X86_OP(inject_irq), + KVM_X86_OP(inject_nmi), + KVM_X86_OP(queue_exception), + KVM_X86_OP(cancel_injection), + KVM_X86_OP(interrupt_allowed), + KVM_X86_OP(nmi_allowed), + KVM_X86_OP(get_nmi_mask), + KVM_X86_OP(set_nmi_mask), + KVM_X86_OP(enable_nmi_window), + KVM_X86_OP(enable_irq_window), + KVM_X86_OP(update_cr8_intercept), + KVM_X86_OP(set_virtual_apic_mode), + KVM_X86_OP(refresh_apicv_exec_ctrl), + KVM_X86_OP(check_apicv_inhibit_reasons), + KVM_X86_OP(pre_update_apicv_exec_ctrl), + KVM_X86_OP(load_eoi_exitmap), + KVM_X86_OP(hwapic_irr_update), + KVM_X86_OP(hwapic_isr_update), .sync_pir_to_irr =3D kvm_lapic_find_highest_irr, - .apicv_post_state_restore =3D avic_post_state_restore, + .apicv_post_state_restore =3D svm_avic_post_state_restore, =20 - .set_tss_addr =3D svm_set_tss_addr, - .set_identity_map_addr =3D svm_set_identity_map_addr, - .get_tdp_level =3D get_npt_level, - .get_mt_mask =3D svm_get_mt_mask, + KVM_X86_OP(set_tss_addr), + KVM_X86_OP(set_identity_map_addr), + KVM_X86_OP(get_tdp_level), + KVM_X86_OP(get_mt_mask), =20 - .get_exit_info =3D svm_get_exit_info, + KVM_X86_OP(get_exit_info), =20 - .cpuid_update =3D svm_cpuid_update, + KVM_X86_OP(cpuid_update), =20 - .has_wbinvd_exit =3D svm_has_wbinvd_exit, + KVM_X86_OP(has_wbinvd_exit), =20 - .write_l1_tsc_offset =3D svm_write_l1_tsc_offset, + KVM_X86_OP(write_l1_tsc_offset), =20 - .load_mmu_pgd =3D svm_load_mmu_pgd, + KVM_X86_OP(load_mmu_pgd), =20 - .check_intercept =3D svm_check_intercept, - .handle_exit_irqoff =3D svm_handle_exit_irqoff, + KVM_X86_OP(check_intercept), + KVM_X86_OP(handle_exit_irqoff), =20 .request_immediate_exit =3D __kvm_request_immediate_exit, =20 - .sched_in =3D svm_sched_in, + KVM_X86_OP(sched_in), =20 .pmu_ops =3D &amd_pmu_ops, .nested_ops =3D &svm_nested_ops, =20 .deliver_posted_interrupt =3D svm_deliver_avic_intr, - .dy_apicv_has_pending_interrupt =3D svm_dy_apicv_has_pending_interrupt, - .update_pi_irte =3D svm_update_pi_irte, - .setup_mce =3D svm_setup_mce, + KVM_X86_OP(dy_apicv_has_pending_interrupt), + KVM_X86_OP(update_pi_irte), + KVM_X86_OP(setup_mce), =20 - .smi_allowed =3D svm_smi_allowed, - .pre_enter_smm =3D svm_pre_enter_smm, - .pre_leave_smm =3D svm_pre_leave_smm, - .enable_smi_window =3D enable_smi_window, + KVM_X86_OP(smi_allowed), + KVM_X86_OP(pre_enter_smm), + KVM_X86_OP(pre_leave_smm), + KVM_X86_OP(enable_smi_window), =20 - .mem_enc_op =3D svm_mem_enc_op, - .mem_enc_register_region =3D svm_register_enc_region, - .mem_enc_unregister_region =3D svm_unregister_enc_region, + KVM_X86_OP(mem_enc_op), + KVM_X86_OP(mem_enc_register_region), + KVM_X86_OP(mem_enc_unregister_region), =20 - .need_emulation_on_page_fault =3D svm_need_emulation_on_page_fault, + KVM_X86_OP(need_emulation_on_page_fault), =20 - .apic_init_signal_blocked =3D svm_apic_init_signal_blocked, + KVM_X86_OP(apic_init_signal_blocked), }; =20 static struct kvm_x86_init_ops svm_init_ops __initdata =3D { diff --git a/arch/x86/kvm/svm/svm.h b/arch/x86/kvm/svm/svm.h index 6ac4c00..e2d5029 100644 --- a/arch/x86/kvm/svm/svm.h +++ b/arch/x86/kvm/svm/svm.h @@ -352,7 +352,7 @@ static inline bool gif_set(struct vcpu_svm *svm) void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer); void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0); int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4); -void svm_flush_tlb(struct kvm_vcpu *vcpu); +void svm_tlb_flush(struct kvm_vcpu *vcpu); void disable_nmi_singlestep(struct vcpu_svm *svm); bool svm_smi_blocked(struct kvm_vcpu *vcpu); bool svm_nmi_blocked(struct kvm_vcpu *vcpu); @@ -444,7 +444,7 @@ static inline bool avic_vcpu_is_running(struct kvm_vcpu= *vcpu) int avic_init_vcpu(struct vcpu_svm *svm); void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu); void avic_vcpu_put(struct kvm_vcpu *vcpu); -void avic_post_state_restore(struct kvm_vcpu *vcpu); +void svm_avic_post_state_restore(struct kvm_vcpu *vcpu); void svm_set_virtual_apic_mode(struct kvm_vcpu *vcpu); void svm_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu); bool svm_check_apicv_inhibit_reasons(ulong bit); @@ -481,9 +481,9 @@ static inline bool svm_sev_enabled(void) =20 void sev_vm_destroy(struct kvm *kvm); int svm_mem_enc_op(struct kvm *kvm, void __user *argp); -int svm_register_enc_region(struct kvm *kvm, +int svm_mem_enc_register_region(struct kvm *kvm, struct kvm_enc_region *range); -int svm_unregister_enc_region(struct kvm *kvm, +int svm_mem_enc_unregister_region(struct kvm *kvm, struct kvm_enc_region *range); void pre_sev_run(struct vcpu_svm *svm, int cpu); int __init sev_hardware_setup(void); --=20 1.8.3.1