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[147.11.224.80]) by smtp.gmail.com with ESMTPSA id m140sm15592562pfd.195.2020.07.19.23.50.31 (version=TLS1 cipher=AES128-SHA bits=128/128); Sun, 19 Jul 2020 23:50:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=Od730M3ahusjI/M47BKltZBPGr/5VHQrawcyQ5Cis6g=; b=A/oH57DQV7unOM5hfxQ0V9uYyOBdZjlqxs48f9sKXu45C7Wv4uU+ocolcArU3hQwx6 088HN8bRgZS4DrcUFiPoutA0xocCdzlDAghUG4g55F7nGxuuFZMIEvmH2eJ95YQklqPK /+HaU4fPx06h2YP0Nd5k+nM3uyt7bJQXv3mHtoUkE8DBxQzztD2AmUbTnofbTgm3djRL lFkUv4+AWKUHprmOtxbeoEomKL96SR2jXrz46S4ETMyRuh1DFDpbNETpiRMEI/g5I/yx sOEUimcyUnZ9NdkyJSxoh2sv/K7auUGS5Zy3NcsComPLAR4Y3O61gDoZoLBEzdY8Vl2n 3OMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=Od730M3ahusjI/M47BKltZBPGr/5VHQrawcyQ5Cis6g=; b=OVQ9sNHUzsA6Q2qGIqVB5KJiB48+nfrWbimoWto2AenBJ3mwbJ7efarLG/cRBv3DoF 4qwctALkbWZ7rV/ZIqoaV4/Ue1FeHFty/C6YQJqbKiY605qn0U8Do8erXYcUOe8zpCOJ b0jYy1lEesr4uyWa3JyqygXR1fs3mcmaU1WsZxQXygNmTKDC21I0VDfpsUfErwTNFoHH FuN8E46bUMMNyIlghQCquemDUqlr9F9koy8q3Cpr15i7CI8pJzH2JgxejGQx+bzwivrD OL93zIwQ8vOe3tiBzmQesvo4uT6nkeWfmI3xEC8ysMQp0ieqI0cGXQKxmi4glmyXgApN xoEA== X-Gm-Message-State: AOAM533BMNZA8WuwxknvP+GCE3S6Oiyh7XDYrEH2E9MH825KMNiG19RT j+/TQTSO3O/wtoFS2zeWe2c= X-Google-Smtp-Source: ABdhPJyxShjW3d5cSVoDa6jUtm0gvmECk//ZMMCSWcrtKypAox/pJ5PKr/gjYS4R8oEa5cF8jIOkYg== X-Received: by 2002:a62:3582:: with SMTP id c124mr18395534pfa.288.1595227832776; Sun, 19 Jul 2020 23:50:32 -0700 (PDT) From: Bin Meng To: Alistair Francis , Bastian Koppelmann , Palmer Dabbelt , Sagar Karandikar , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH] hw/riscv: sifive_u: Add a dummy L2 cache controller device Date: Sun, 19 Jul 2020 23:49:08 -0700 Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com> X-Mailer: git-send-email 1.7.1 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::443; envelope-from=bmeng.cn@gmail.com; helo=mail-pf1-x443.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng It is enough to simply map the SiFive FU540 L2 cache controller into the MMIO space using create_unimplemented_device(), with an FDT fragment generated, to make the latest upstream U-Boot happy. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_u.c | 22 ++++++++++++++++++++++ include/hw/riscv/sifive_u.h | 4 ++++ 2 files changed, 26 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6487d5e..f771cb0 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -72,6 +72,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEBUG] =3D { 0x0, 0x100 }, [SIFIVE_U_MROM] =3D { 0x1000, 0xf000 }, [SIFIVE_U_CLINT] =3D { 0x2000000, 0x10000 }, + [SIFIVE_U_L2CC] =3D { 0x2010000, 0x1000 }, [SIFIVE_U_L2LIM] =3D { 0x8000000, 0x2000000 }, [SIFIVE_U_PLIC] =3D { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] =3D { 0x10000000, 0x1000 }, @@ -302,6 +303,24 @@ static void create_fdt(SiFiveUState *s, const struct M= emmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "gpio-restart"); g_free(nodename); =20 + nodename =3D g_strdup_printf("/soc/cache-controller@%lx", + (long)memmap[SIFIVE_U_L2CC].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_L2CC].base, + 0x0, memmap[SIFIVE_U_L2CC].size); + qemu_fdt_setprop_cells(fdt, nodename, "interrupts", + SIFIVE_U_L2CC_IRQ0, SIFIVE_U_L2CC_IRQ1, SIFIVE_U_L2CC_IRQ2); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop(fdt, nodename, "cache-unified", NULL, 0); + qemu_fdt_setprop_cell(fdt, nodename, "cache-size", 2097152); + qemu_fdt_setprop_cell(fdt, nodename, "cache-sets", 1024); + qemu_fdt_setprop_cell(fdt, nodename, "cache-level", 2); + qemu_fdt_setprop_cell(fdt, nodename, "cache-block-size", 64); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-ccache"); + g_free(nodename); + phy_phandle =3D phandle++; nodename =3D g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); @@ -732,6 +751,9 @@ static void sifive_u_soc_realize(DeviceState *dev, Erro= r **errp) =20 create_unimplemented_device("riscv.sifive.u.dmc", memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size); + + create_unimplemented_device("riscv.sifive.u.l2cc", + memmap[SIFIVE_U_L2CC].base, memmap[SIFIVE_U_L2CC].size); } =20 static Property sifive_u_soc_props[] =3D { diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index aba4d01..d3c0c00 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -71,6 +71,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2CC, SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, @@ -86,6 +87,9 @@ enum { }; =20 enum { + SIFIVE_U_L2CC_IRQ0 =3D 1, + SIFIVE_U_L2CC_IRQ1 =3D 2, + SIFIVE_U_L2CC_IRQ2 =3D 3, SIFIVE_U_UART0_IRQ =3D 4, SIFIVE_U_UART1_IRQ =3D 5, SIFIVE_U_GPIO_IRQ0 =3D 7, --=20 2.7.4