From nobody Mon Feb 9 09:53:07 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1593862661; cv=none; d=zohomail.com; s=zohoarc; b=A4seH1ypGPWpSvcIXs0ilwP6xGofixG6sWkIivr9N+1kJ0DJgjQrIeJ4umeARiRR51TxkHanRFIXufQQe4M3xdza6TCs6XF4h9fvJkd1eaU/VprsQ6K9Wkz1nPc+5aHEQdRoQymOwJmmAcxYldcar1OOKqIS93ycXKK2dsxujMY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1593862661; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=SJqNY369I6oq/zAJGeSYzz0Nwpf5aZ0PLLUHC36YDwo=; b=ceG/bVg0Wglh3kN7tSzGqdgWLnG9f2j7gI9Isci7LDQ/PgdjiXhSo0Rqb149lgm7EigugJXvZCeQX1cicsFikJjD5iTim51dPUS71deNea0+rFFkR0zgb+6I9/zurlXM5ZPGmjhagi8gbUIFOERpJBSmLSQXBigl+XNL+O5crt4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1593862661695574.737742885121; Sat, 4 Jul 2020 04:37:41 -0700 (PDT) Received: from localhost ([::1]:49380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jrgUG-00062v-Er for importer@patchew.org; Sat, 04 Jul 2020 07:37:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:52688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrgO6-0001ef-Iz for qemu-devel@nongnu.org; Sat, 04 Jul 2020 07:31:18 -0400 Received: from mga05.intel.com ([192.55.52.43]:24796) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jrgO3-0004KB-Gf for qemu-devel@nongnu.org; Sat, 04 Jul 2020 07:31:18 -0400 Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Jul 2020 04:30:25 -0700 Received: from jacob-builder.jf.intel.com ([10.7.199.155]) by fmsmga007.fm.intel.com with ESMTP; 04 Jul 2020 04:30:24 -0700 IronPort-SDR: G9tOqUAmnnm9SVrvue7lDZRNfXKVkzXSW1/0tDCjlpsQVJya3oJbbrb6qgIFcm9YrhSyEzAUfj gClhd396TxoA== X-IronPort-AV: E=McAfee;i="6000,8403,9671"; a="232105536" X-IronPort-AV: E=Sophos;i="5.75,311,1589266800"; d="scan'208";a="232105536" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: 1CzQiAvKzcWNiI3KEiWW85GeqPuYhG1tbntFI84kRt7wfoHMBzrtnOV/Vl0B4Lv+6s9qZ7iUUe zShnUkUaIMyg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,311,1589266800"; d="scan'208";a="266146834" From: Liu Yi L To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Subject: [RFC v7 19/25] intel_iommu: replay pasid binds after context cache invalidation Date: Sat, 4 Jul 2020 04:36:43 -0700 Message-Id: <1593862609-36135-20-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593862609-36135-1-git-send-email-yi.l.liu@intel.com> References: <1593862609-36135-1-git-send-email-yi.l.liu@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.43; envelope-from=yi.l.liu@intel.com; helo=mga05.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/07/04 07:30:14 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, kevin.tian@intel.com, yi.l.liu@intel.com, Yi Sun , Eduardo Habkost , kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, Jacob Pan , pbonzini@redhat.com, hao.wu@intel.com, jasowang@redhat.com, Richard Henderson , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch replays guest pasid bindings after context cache invalidation. This is a behavior to ensure safety. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing a context cache invalidation. Cc: Kevin Tian Cc: Jacob Pan Cc: Peter Xu Cc: Yi Sun Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Signed-off-by: Liu Yi L --- hw/i386/intel_iommu.c | 50 ++++++++++++++++++++++++++++++++++++++= ++++ hw/i386/intel_iommu_internal.h | 1 + hw/i386/trace-events | 1 + 3 files changed, 52 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index cf0dad8..9977e70 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -68,6 +68,10 @@ static void vtd_address_space_refresh_all(IntelIOMMUStat= e *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 static void vtd_pasid_cache_reset(IntelIOMMUState *s); +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info); +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + VTDBus *vtd_bus, uint16_t devfn); =20 static void vtd_panic_require_caching_mode(void) { @@ -1853,7 +1857,10 @@ static void vtd_iommu_replay_all(IntelIOMMUState *s) =20 static void vtd_context_global_invalidate(IntelIOMMUState *s) { + VTDPASIDCacheInfo pc_info; + trace_vtd_inv_desc_cc_global(); + /* Protects context cache */ vtd_iommu_lock(s); s->context_cache_gen++; @@ -1870,6 +1877,9 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + vtd_pasid_cache_sync(s, &pc_info); } =20 /** @@ -2006,6 +2016,21 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_sync_shadow_page_table(vtd_as); + /* + * Per spec, context flush should also followed with PASID + * cache and iotlb flush. Regards to a device selective + * context cache invalidation: + * if (emaulted_device) + * invalidate pasid cahce and pasid-based iotlb + * else if (assigned_device) + * check if the device has been bound to any pasid + * invoke pasid_unbind regards to each bound pasid + * Here, we have vtd_pasid_cache_devsi() to invalidate pas= id + * caches, while for piotlb in QEMU, we don't have it yet,= so + * no handling. For assigned device, host iommu driver wou= ld + * flush piotlb when a pasid unbind is pass down to it. + */ + vtd_pasid_cache_devsi(s, vtd_bus, devfn_it); } } } @@ -2620,6 +2645,12 @@ static gboolean vtd_flush_pasid(gpointer key, gpoint= er value, /* Fall through */ case VTD_PASID_CACHE_GLOBAL_INV: break; + case VTD_PASID_CACHE_DEVSI: + if (pc_info->vtd_bus !=3D vtd_bus || + pc_info->devfn !=3D devfn) { + return false; + } + break; default: error_report("invalid pc_info->type"); abort(); @@ -2819,6 +2850,11 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_DEVSI: + walk_info.vtd_bus =3D pc_info->vtd_bus; + walk_info.devfn =3D pc_info->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + return; case VTD_PASID_CACHE_FORCE_RESET: /* For force reset, no need to go further replay */ return; @@ -2904,6 +2940,20 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, vtd_iommu_unlock(s); } =20 +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + VTDBus *vtd_bus, uint16_t devfn) +{ + VTDPASIDCacheInfo pc_info; + + trace_vtd_pasid_cache_devsi(devfn); + + pc_info.type =3D VTD_PASID_CACHE_DEVSI; + pc_info.vtd_bus =3D vtd_bus; + pc_info.devfn =3D devfn; + + vtd_pasid_cache_sync(s, &pc_info); +} + /** * Caller of this function should hold iommu_lock */ diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 51691d0..9805b84 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -548,6 +548,7 @@ typedef enum VTDPCInvType { VTD_PASID_CACHE_FORCE_RESET =3D 0, /* pasid cache invalidation rely on guest PASID entry */ VTD_PASID_CACHE_GLOBAL_INV, + VTD_PASID_CACHE_DEVSI, VTD_PASID_CACHE_DOMSI, VTD_PASID_CACHE_PASIDSI, } VTDPCInvType; diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 60d20c1..3853fa8 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -26,6 +26,7 @@ vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_reset(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domian slective PC invalidation doma= in 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID slective PC in= validation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint16_t devfn) "Dev selective PC invalidation dev: = 0x%"PRIx16 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.7.4