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Date: Mon, 15 Jun 2020 21:22:19 +0200 Message-Id: <1592248953-8162-5-git-send-email-aleksandar.qemu.devel@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1592248953-8162-1-git-send-email-aleksandar.qemu.devel@gmail.com> References: <1592248953-8162-1-git-send-email-aleksandar.qemu.devel@gmail.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=aleksandar.qemu.devel@gmail.com; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.qemu.devel@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Achieves clearer code and slightly better performance. Reviewed-by: Aleksandar Rikalo Signed-off-by: Aleksandar Markovic Message-Id: <20200613152133.8964-3-aleksandar.qemu.devel@gmail.com> --- target/mips/helper.h | 6 +++- target/mips/msa_helper.c | 79 +++++++++++++++++++++++++++++++++++++++++++-= ---- target/mips/translate.c | 19 ++++++++++-- 3 files changed, 93 insertions(+), 11 deletions(-) diff --git a/target/mips/helper.h b/target/mips/helper.h index e479a22..7ca0036 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -955,6 +955,11 @@ DEF_HELPER_4(msa_maddv_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_maddv_w, void, env, i32, i32, i32) DEF_HELPER_4(msa_maddv_d, void, env, i32, i32, i32) =20 +DEF_HELPER_4(msa_msubv_b, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_h, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_w, void, env, i32, i32, i32) +DEF_HELPER_4(msa_msubv_d, void, env, i32, i32, i32) + DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32) DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32) DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32) @@ -1074,7 +1079,6 @@ DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32,= i32) DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32) -DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dotp_s_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dotp_u_df, void, env, i32, i32, i32, i32) DEF_HELPER_5(msa_dpadd_s_df, void, env, i32, i32, i32, i32) diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c index 3b75bdc..2b54de0 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/msa_helper.c @@ -2955,6 +2955,78 @@ void helper_msa_maddv_d(CPUMIPSState *env, pwd->d[1] =3D msa_maddv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[= 1]); } =20 +static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1, + int64_t arg2) +{ + return dest - arg1 * arg2; +} + +void helper_msa_msubv_b(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->b[0] =3D msa_msubv_df(DF_BYTE, pwt->b[0], pws->b[0], pwt->b[0]= ); + pwd->b[1] =3D msa_msubv_df(DF_BYTE, pwt->b[1], pws->b[1], pwt->b[1]= ); + pwd->b[2] =3D msa_msubv_df(DF_BYTE, pwt->b[2], pws->b[2], pwt->b[2]= ); + pwd->b[3] =3D msa_msubv_df(DF_BYTE, pwt->b[3], pws->b[3], pwt->b[3]= ); + pwd->b[4] =3D msa_msubv_df(DF_BYTE, pwt->b[4], pws->b[4], pwt->b[4]= ); + pwd->b[5] =3D msa_msubv_df(DF_BYTE, pwt->b[5], pws->b[5], pwt->b[5]= ); + pwd->b[6] =3D msa_msubv_df(DF_BYTE, pwt->b[6], pws->b[6], pwt->b[6]= ); + pwd->b[7] =3D msa_msubv_df(DF_BYTE, pwt->b[7], pws->b[7], pwt->b[7]= ); + pwd->b[8] =3D msa_msubv_df(DF_BYTE, pwt->b[8], pws->b[8], pwt->b[8]= ); + pwd->b[9] =3D msa_msubv_df(DF_BYTE, pwt->b[9], pws->b[9], pwt->b[9]= ); + pwd->b[10] =3D msa_msubv_df(DF_BYTE, pwt->b[10], pws->b[10], pwt->b[10= ]); + pwd->b[11] =3D msa_msubv_df(DF_BYTE, pwt->b[11], pws->b[11], pwt->b[11= ]); + pwd->b[12] =3D msa_msubv_df(DF_BYTE, pwt->b[12], pws->b[12], pwt->b[12= ]); + pwd->b[13] =3D msa_msubv_df(DF_BYTE, pwt->b[13], pws->b[13], pwt->b[13= ]); + pwd->b[14] =3D msa_msubv_df(DF_BYTE, pwt->b[14], pws->b[14], pwt->b[14= ]); + pwd->b[15] =3D msa_msubv_df(DF_BYTE, pwt->b[15], pws->b[15], pwt->b[15= ]); +} + +void helper_msa_msubv_h(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->h[0] =3D msa_msubv_df(DF_HALF, pwd->h[0], pws->h[0], pwt->h[0]= ); + pwd->h[1] =3D msa_msubv_df(DF_HALF, pwd->h[1], pws->h[1], pwt->h[1]= ); + pwd->h[2] =3D msa_msubv_df(DF_HALF, pwd->h[2], pws->h[2], pwt->h[2]= ); + pwd->h[3] =3D msa_msubv_df(DF_HALF, pwd->h[3], pws->h[3], pwt->h[3]= ); + pwd->h[4] =3D msa_msubv_df(DF_HALF, pwd->h[4], pws->h[4], pwt->h[4]= ); + pwd->h[5] =3D msa_msubv_df(DF_HALF, pwd->h[5], pws->h[5], pwt->h[5]= ); + pwd->h[6] =3D msa_msubv_df(DF_HALF, pwd->h[6], pws->h[6], pwt->h[6]= ); + pwd->h[7] =3D msa_msubv_df(DF_HALF, pwd->h[7], pws->h[7], pwt->h[7]= ); +} + +void helper_msa_msubv_w(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->w[0] =3D msa_msubv_df(DF_WORD, pwd->w[0], pws->w[0], pwt->w[0]= ); + pwd->w[1] =3D msa_msubv_df(DF_WORD, pwd->w[1], pws->w[1], pwt->w[1]= ); + pwd->w[2] =3D msa_msubv_df(DF_WORD, pwd->w[2], pws->w[2], pwt->w[2]= ); + pwd->w[3] =3D msa_msubv_df(DF_WORD, pwd->w[3], pws->w[3], pwt->w[3]= ); +} + +void helper_msa_msubv_d(CPUMIPSState *env, + uint32_t wd, uint32_t ws, uint32_t wt) +{ + wr_t *pwd =3D &(env->active_fpu.fpr[wd].wr); + wr_t *pws =3D &(env->active_fpu.fpr[ws].wr); + wr_t *pwt =3D &(env->active_fpu.fpr[wt].wr); + + pwd->d[0] =3D msa_msubv_df(DF_DOUBLE, pwd->d[0], pws->d[0], pwt->d[= 0]); + pwd->d[1] =3D msa_msubv_df(DF_DOUBLE, pwd->d[1], pws->d[1], pwt->d[= 1]); +} + =20 /* * Int Subtract @@ -4886,12 +4958,6 @@ void helper_msa_sld_df(CPUMIPSState *env, uint32_t d= f, uint32_t wd, msa_sld_df(df, pwd, pws, env->active_tc.gpr[rt]); } =20 -static inline int64_t msa_msubv_df(uint32_t df, int64_t dest, int64_t arg1, - int64_t arg2) -{ - return dest - arg1 * arg2; -} - static inline int64_t msa_dpadd_s_df(uint32_t df, int64_t dest, int64_t ar= g1, int64_t arg2) { @@ -5066,7 +5132,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, ui= nt32_t df, uint32_t wd, \ } = \ } =20 -MSA_TEROP_DF(msubv) MSA_TEROP_DF(dpadd_s) MSA_TEROP_DF(dpadd_u) MSA_TEROP_DF(dpsub_s) diff --git a/target/mips/translate.c b/target/mips/translate.c index 4975e57..7388a16 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -29074,6 +29074,22 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCon= text *ctx) break; } break; + case OPC_MSUBV_df: + switch (df) { + case DF_BYTE: + gen_helper_msa_msubv_b(cpu_env, twd, tws, twt); + break; + case DF_HALF: + gen_helper_msa_msubv_h(cpu_env, twd, tws, twt); + break; + case DF_WORD: + gen_helper_msa_msubv_w(cpu_env, twd, tws, twt); + break; + case DF_DOUBLE: + gen_helper_msa_msubv_d(cpu_env, twd, tws, twt); + break; + } + break; case OPC_ASUB_S_df: switch (df) { case DF_BYTE: @@ -29306,9 +29322,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasCont= ext *ctx) case OPC_SUBSUS_U_df: gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt); break; - case OPC_MSUBV_df: - gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt); - break; case OPC_SUBSUU_S_df: gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt); break; --=20 2.7.4