From nobody Sun Feb 8 18:09:05 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1591879871; cv=none; d=zohomail.com; s=zohoarc; b=SWLwioe+AmNY0oNmkSfj5V3iiP49+kX3iXHsujDUaGEMhKVc+5FiURnq9ybn7Qn0M2dioyuV3uPiPmN2E7DirZt+96MLmDqvou7qlfiZpEfF7DL/PY+cXIxerXTCpjZD4mGTmJHroCn/l8NvObywhw+9DJkrecCV3z44xORPYW8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1591879871; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=NbY6IV1hfO6NCiLw54ExGwDqLqWcJL0Lgc3DCL9OXgk=; b=FANt1v7MqPZh5ZHfjCr1F/8SOVjk5yK0mf7Z3MvyKm9qZzSgAlgI9WdLWgbZhJ51MSUh8yXV2ph7w3m8KHF69I+Ue+9EKj0HTQ4bHtXT6/hHHwwwWUclexFpn5sATcytfcX9GvIdBODsD4jvf5j+YXfp8Ms7cdu6o2+flOduqbE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1591879871155260.1570090235125; Thu, 11 Jun 2020 05:51:11 -0700 (PDT) Received: from localhost ([::1]:50140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jjMfl-0007qy-QO for importer@patchew.org; Thu, 11 Jun 2020 08:51:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jjMcw-0002WQ-KC for qemu-devel@nongnu.org; Thu, 11 Jun 2020 08:48:14 -0400 Received: from mga14.intel.com ([192.55.52.115]:37617) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jjMcu-0007zT-UO for qemu-devel@nongnu.org; Thu, 11 Jun 2020 08:48:14 -0400 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Jun 2020 05:48:00 -0700 Received: from jacob-builder.jf.intel.com ([10.7.199.155]) by orsmga005.jf.intel.com with ESMTP; 11 Jun 2020 05:48:00 -0700 IronPort-SDR: aGHuSnv0VxY890qnt5bULxF9z5O9zUUZm8ux+AACqO7CzLWmKriPfd4/UKkaXj7bT/s3btRIYy RUEL4fXs0k9A== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: YamqfkDNGaG4KyWpZSk94YR36+y4edlKaZ+ijZuv1UCU8OCIpg2eBUsJbUKTQSI5Lit6i1wNfp /ztkYWhN1Xuw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.73,499,1583222400"; d="scan'208";a="447911244" From: Liu Yi L To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Subject: [RFC v6 10/25] intel_iommu: add set/unset_iommu_context callback Date: Thu, 11 Jun 2020 05:54:09 -0700 Message-Id: <1591880064-30638-11-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1591880064-30638-1-git-send-email-yi.l.liu@intel.com> References: <1591880064-30638-1-git-send-email-yi.l.liu@intel.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yi.l.liu@intel.com; helo=mga14.intel.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/06/11 08:48:00 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Spam_score_int: -68 X-Spam_score: -6.9 X-Spam_bar: ------ X-Spam_report: (-6.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, kevin.tian@intel.com, yi.l.liu@intel.com, Yi Sun , Eduardo Habkost , kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, Jacob Pan , pbonzini@redhat.com, hao.wu@intel.com, Richard Henderson , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds set/unset_iommu_context() impelementation in Intel vIOMMU. PCIe devices (VFIO case) sets HostIOMMUContext to vIOMMU as an ack of vIOMMU's "want_nested" attribute. Thus vIOMMU could build DMA protection based on nested paging of host IOMMU. Cc: Kevin Tian Cc: Jacob Pan Cc: Peter Xu Cc: Yi Sun Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Signed-off-by: Liu Yi L --- hw/i386/intel_iommu.c | 71 +++++++++++++++++++++++++++++++++++++++= +--- include/hw/i386/intel_iommu.h | 21 ++++++++++--- 2 files changed, 83 insertions(+), 9 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a8b7627..6f30616 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3354,23 +3354,33 @@ static const MemoryRegionOps vtd_mem_ir_ops =3D { }, }; =20 -VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n) +/** + * Fetch a VTDBus instance for given PCIBus. If no existing instance, + * allocate one. + */ +static VTDBus *vtd_find_add_bus(IntelIOMMUState *s, PCIBus *bus) { uintptr_t key =3D (uintptr_t)bus; VTDBus *vtd_bus =3D g_hash_table_lookup(s->vtd_as_by_busptr, &key); - VTDAddressSpace *vtd_dev_as; - char name[128]; =20 if (!vtd_bus) { uintptr_t *new_key =3D g_malloc(sizeof(*new_key)); *new_key =3D (uintptr_t)bus; /* No corresponding free() */ - vtd_bus =3D g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) *= \ - PCI_DEVFN_MAX); + vtd_bus =3D g_malloc0(sizeof(VTDBus)); vtd_bus->bus =3D bus; g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); } + return vtd_bus; +} =20 +VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n) +{ + VTDBus *vtd_bus; + VTDAddressSpace *vtd_dev_as; + char name[128]; + + vtd_bus =3D vtd_find_add_bus(s, bus); vtd_dev_as =3D vtd_bus->dev_as[devfn]; =20 if (!vtd_dev_as) { @@ -3458,6 +3468,55 @@ static int vtd_dev_get_iommu_attr(PCIBus *bus, void = *opaque, int32_t devfn, return ret; } =20 +static int vtd_dev_set_iommu_context(PCIBus *bus, void *opaque, + int devfn, + HostIOMMUContext *iommu_ctx) +{ + IntelIOMMUState *s =3D opaque; + VTDBus *vtd_bus; + VTDHostIOMMUContext *vtd_dev_icx; + + assert(0 <=3D devfn && devfn < PCI_DEVFN_MAX); + + vtd_bus =3D vtd_find_add_bus(s, bus); + + vtd_iommu_lock(s); + + vtd_dev_icx =3D vtd_bus->dev_icx[devfn]; + + assert(!vtd_dev_icx); + + vtd_bus->dev_icx[devfn] =3D vtd_dev_icx =3D + g_malloc0(sizeof(VTDHostIOMMUContext)); + vtd_dev_icx->vtd_bus =3D vtd_bus; + vtd_dev_icx->devfn =3D (uint8_t)devfn; + vtd_dev_icx->iommu_state =3D s; + vtd_dev_icx->iommu_ctx =3D iommu_ctx; + + vtd_iommu_unlock(s); + + return 0; +} + +static void vtd_dev_unset_iommu_context(PCIBus *bus, void *opaque, int dev= fn) +{ + IntelIOMMUState *s =3D opaque; + VTDBus *vtd_bus; + VTDHostIOMMUContext *vtd_dev_icx; + + assert(0 <=3D devfn && devfn < PCI_DEVFN_MAX); + + vtd_bus =3D vtd_find_add_bus(s, bus); + + vtd_iommu_lock(s); + + vtd_dev_icx =3D vtd_bus->dev_icx[devfn]; + g_free(vtd_dev_icx); + vtd_bus->dev_icx[devfn] =3D NULL; + + vtd_iommu_unlock(s); +} + static uint64_t get_naturally_aligned_size(uint64_t start, uint64_t size, int gaw) { @@ -3754,6 +3813,8 @@ static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, = void *opaque, int devfn) static PCIIOMMUOps vtd_iommu_ops =3D { .get_address_space =3D vtd_host_dma_iommu, .get_iommu_attr =3D vtd_dev_get_iommu_attr, + .set_iommu_context =3D vtd_dev_set_iommu_context, + .unset_iommu_context =3D vtd_dev_unset_iommu_context, }; =20 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 3870052..b5fefb9 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -64,6 +64,7 @@ typedef union VTD_IR_TableEntry VTD_IR_TableEntry; typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; typedef struct VTDPASIDEntry VTDPASIDEntry; +typedef struct VTDHostIOMMUContext VTDHostIOMMUContext; =20 /* Context-Entry */ struct VTDContextEntry { @@ -112,10 +113,20 @@ struct VTDAddressSpace { IOVATree *iova_tree; /* Traces mapped IOVA ranges */ }; =20 +struct VTDHostIOMMUContext { + VTDBus *vtd_bus; + uint8_t devfn; + HostIOMMUContext *iommu_ctx; + IntelIOMMUState *iommu_state; +}; + struct VTDBus { - PCIBus* bus; /* A reference to the bus to provide translation for */ + /* A reference to the bus to provide translation for */ + PCIBus *bus; /* A table of VTDAddressSpace objects indexed by devfn */ - VTDAddressSpace *dev_as[]; + VTDAddressSpace *dev_as[PCI_DEVFN_MAX]; + /* A table of VTDHostIOMMUContext objects indexed by devfn */ + VTDHostIOMMUContext *dev_icx[PCI_DEVFN_MAX]; }; =20 struct VTDIOTLBEntry { @@ -269,8 +280,10 @@ struct IntelIOMMUState { bool dma_drain; /* Whether DMA r/w draining enabled */ =20 /* - * Protects IOMMU states in general. Currently it protects the - * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. + * iommu_lock protects below: + * - per-IOMMU IOTLB caches + * - context entry cache in VTDAddressSpace + * - HostIOMMUContext pointer cached in vIOMMU */ QemuMutex iommu_lock; }; --=20 2.7.4