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That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Bin Meng Add a new property to represent the number of GPIO pins supported by the GPIO controller. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis --- hw/riscv/sifive_gpio.c | 30 +++++++++++++++++++----------- include/hw/riscv/sifive_gpio.h | 3 +++ 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/hw/riscv/sifive_gpio.c b/hw/riscv/sifive_gpio.c index c9cffa2..0d0fd2b 100644 --- a/hw/riscv/sifive_gpio.c +++ b/hw/riscv/sifive_gpio.c @@ -14,6 +14,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "hw/irq.h" +#include "hw/qdev-properties.h" #include "hw/riscv/sifive_gpio.h" #include "migration/vmstate.h" #include "trace.h" @@ -28,7 +29,7 @@ static void update_output_irq(SIFIVEGPIOState *s) pending |=3D s->rise_ip & s->rise_ie; pending |=3D s->fall_ip & s->fall_ie; =20 - for (int i =3D 0; i < SIFIVE_GPIO_PINS; i++) { + for (int i =3D 0; i < s->ngpio; i++) { pin =3D 1 << i; qemu_set_irq(s->irq[i], (pending & pin) !=3D 0); trace_sifive_gpio_update_output_irq(i, (pending & pin) !=3D 0); @@ -41,7 +42,7 @@ static void update_state(SIFIVEGPIOState *s) bool prev_ival, in, in_mask, port, out_xor, pull, output_en, input_en, rise_ip, fall_ip, low_ip, high_ip, oval, actual_value, ival; =20 - for (i =3D 0; i < SIFIVE_GPIO_PINS; i++) { + for (i =3D 0; i < s->ngpio; i++) { =20 prev_ival =3D extract32(s->value, i, 1); in =3D extract32(s->in, i, 1); @@ -346,27 +347,35 @@ static const VMStateDescription vmstate_sifive_gpio = =3D { } }; =20 -static void sifive_gpio_init(Object *obj) +static Property sifive_gpio_properties[] =3D { + DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_gpio_realize(DeviceState *dev, Error **errp) { - SIFIVEGPIOState *s =3D SIFIVE_GPIO(obj); + SIFIVEGPIOState *s =3D SIFIVE_GPIO(dev); =20 - memory_region_init_io(&s->mmio, obj, &gpio_ops, s, + memory_region_init_io(&s->mmio, OBJECT(dev), &gpio_ops, s, TYPE_SIFIVE_GPIO, SIFIVE_GPIO_SIZE); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); =20 - for (int i =3D 0; i < SIFIVE_GPIO_PINS; i++) { - sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq[i]); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); + + for (int i =3D 0; i < s->ngpio; i++) { + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]); } =20 - qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, SIFIVE_GPIO_PINS); - qdev_init_gpio_out(DEVICE(s), s->output, SIFIVE_GPIO_PINS); + qdev_init_gpio_in(DEVICE(s), sifive_gpio_set, s->ngpio); + qdev_init_gpio_out(DEVICE(s), s->output, s->ngpio); } =20 static void sifive_gpio_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + device_class_set_props(dc, sifive_gpio_properties); dc->vmsd =3D &vmstate_sifive_gpio; + dc->realize =3D sifive_gpio_realize; dc->reset =3D sifive_gpio_reset; dc->desc =3D "SiFive GPIO"; } @@ -375,7 +384,6 @@ static const TypeInfo sifive_gpio_info =3D { .name =3D TYPE_SIFIVE_GPIO, .parent =3D TYPE_SYS_BUS_DEVICE, .instance_size =3D sizeof(SIFIVEGPIOState), - .instance_init =3D sifive_gpio_init, .class_init =3D sifive_gpio_class_init }; =20 diff --git a/include/hw/riscv/sifive_gpio.h b/include/hw/riscv/sifive_gpio.h index ad915b2..cf12fcf 100644 --- a/include/hw/riscv/sifive_gpio.h +++ b/include/hw/riscv/sifive_gpio.h @@ -68,6 +68,9 @@ typedef struct SIFIVEGPIOState { uint32_t out_xor; uint32_t in; uint32_t in_mask; + + /* config */ + uint32_t ngpio; } SIFIVEGPIOState; =20 #endif /* SIFIVE_GPIO_H */ --=20 2.7.4