From nobody Sun Feb 8 18:19:23 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) client-ip=208.118.235.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zoho.com: domain of gnu.org designates 208.118.235.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [208.118.235.17]) by mx.zohomail.com with SMTPS id 150325144497752.639200802638925; Sun, 20 Aug 2017 10:50:44 -0700 (PDT) Received: from localhost ([::1]:43007 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1djUN1-0005eq-Qr for importer@patchew.org; Sun, 20 Aug 2017 13:50:43 -0400 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39805) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1djUKy-000456-HB for qemu-devel@nongnu.org; Sun, 20 Aug 2017 13:48:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1djUKv-00053t-J3 for qemu-devel@nongnu.org; Sun, 20 Aug 2017 13:48:36 -0400 Received: from zero.eik.bme.hu ([152.66.115.2]:27117) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1djUKv-00052g-5Z; Sun, 20 Aug 2017 13:48:33 -0400 Received: from zero.eik.bme.hu (blah.eik.bme.hu [152.66.115.182]) by localhost (Postfix) with SMTP id A6B54747DDC; Sun, 20 Aug 2017 19:48:31 +0200 (CEST) Received: by zero.eik.bme.hu (Postfix, from userid 432) id 14A04747BD3; Sun, 20 Aug 2017 19:48:31 +0200 (CEST) Message-Id: <158c09e2f3e7930786edcc49bcd9b19b9f92bfa5.1503249785.git.balaton@eik.bme.hu> In-Reply-To: References: From: BALATON Zoltan Date: Sun, 20 Aug 2017 19:23:05 +0200 To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 152.66.115.2 Subject: [Qemu-devel] [PATCH 02/15] ppc4xx: Make MAL emulation more generic X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Francois Revol , Alexander Graf , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail: RSF_0 Z_629925259 SPT_0 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Allow MAL with more RX and TX channels as found in newer versions. Signed-off-by: BALATON Zoltan Reviewed-by: David Gibson --- hw/ppc/ppc405_uc.c | 2 +- hw/ppc/ppc4xx_devs.c | 171 +++++++++++++++++++-------------------------= ---- include/hw/ppc/ppc4xx.h | 3 +- 3 files changed, 70 insertions(+), 106 deletions(-) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index 3c74402..03856d5 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -2281,7 +2281,7 @@ CPUPPCState *ppc405ep_init(MemoryRegion *address_spac= e_mem, mal_irqs[1] =3D pic[12]; mal_irqs[2] =3D pic[13]; mal_irqs[3] =3D pic[14]; - ppc405_mal_init(env, mal_irqs); + ppc4xx_mal_init(env, 4, 2, mal_irqs); /* Ethernet */ /* Uses pic[9], pic[15], pic[17] */ /* CPU control */ diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 8e4f78e..6e1cc09 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -737,6 +737,7 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int= nr_banks, =20 /*************************************************************************= ****/ /* MAL */ + enum { MAL0_CFG =3D 0x180, MAL0_ESR =3D 0x181, @@ -750,17 +751,13 @@ enum { MAL0_RXEOBISR =3D 0x192, MAL0_RXDEIR =3D 0x193, MAL0_TXCTP0R =3D 0x1A0, - MAL0_TXCTP1R =3D 0x1A1, - MAL0_TXCTP2R =3D 0x1A2, - MAL0_TXCTP3R =3D 0x1A3, MAL0_RXCTP0R =3D 0x1C0, - MAL0_RXCTP1R =3D 0x1C1, MAL0_RCBS0 =3D 0x1E0, MAL0_RCBS1 =3D 0x1E1, }; =20 -typedef struct ppc40x_mal_t ppc40x_mal_t; -struct ppc40x_mal_t { +typedef struct ppc4xx_mal_t ppc4xx_mal_t; +struct ppc4xx_mal_t { qemu_irq irqs[4]; uint32_t cfg; uint32_t esr; @@ -773,16 +770,32 @@ struct ppc40x_mal_t { uint32_t rxcarr; uint32_t rxeobisr; uint32_t rxdeir; - uint32_t txctpr[4]; - uint32_t rxctpr[2]; - uint32_t rcbs[2]; + uint32_t *txctpr; + uint32_t *rxctpr; + uint32_t *rcbs; + uint8_t txcnum; + uint8_t rxcnum; }; =20 -static void ppc40x_mal_reset(void *opaque); +static void ppc4xx_mal_reset(void *opaque) +{ + ppc4xx_mal_t *mal; + + mal =3D opaque; + mal->cfg =3D 0x0007C000; + mal->esr =3D 0x00000000; + mal->ier =3D 0x00000000; + mal->rxcasr =3D 0x00000000; + mal->rxdeir =3D 0x00000000; + mal->rxeobisr =3D 0x00000000; + mal->txcasr =3D 0x00000000; + mal->txdeir =3D 0x00000000; + mal->txeobisr =3D 0x00000000; +} =20 static uint32_t dcr_read_mal(void *opaque, int dcrn) { - ppc40x_mal_t *mal; + ppc4xx_mal_t *mal; uint32_t ret; =20 mal =3D opaque; @@ -820,48 +833,32 @@ static uint32_t dcr_read_mal(void *opaque, int dcrn) case MAL0_RXDEIR: ret =3D mal->rxdeir; break; - case MAL0_TXCTP0R: - ret =3D mal->txctpr[0]; - break; - case MAL0_TXCTP1R: - ret =3D mal->txctpr[1]; - break; - case MAL0_TXCTP2R: - ret =3D mal->txctpr[2]; - break; - case MAL0_TXCTP3R: - ret =3D mal->txctpr[3]; - break; - case MAL0_RXCTP0R: - ret =3D mal->rxctpr[0]; - break; - case MAL0_RXCTP1R: - ret =3D mal->rxctpr[1]; - break; - case MAL0_RCBS0: - ret =3D mal->rcbs[0]; - break; - case MAL0_RCBS1: - ret =3D mal->rcbs[1]; - break; default: ret =3D 0; break; } + if (dcrn >=3D MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { + ret =3D mal->txctpr[dcrn - MAL0_TXCTP0R]; + } + if (dcrn >=3D MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { + ret =3D mal->rxctpr[dcrn - MAL0_RXCTP0R]; + } + if (dcrn >=3D MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { + ret =3D mal->rcbs[dcrn - MAL0_RCBS0]; + } =20 return ret; } =20 static void dcr_write_mal(void *opaque, int dcrn, uint32_t val) { - ppc40x_mal_t *mal; - int idx; + ppc4xx_mal_t *mal; =20 mal =3D opaque; switch (dcrn) { case MAL0_CFG: if (val & 0x80000000) { - ppc40x_mal_reset(mal); + ppc4xx_mal_reset(mal); } mal->cfg =3D val & 0x00FFC087; break; @@ -900,65 +897,35 @@ static void dcr_write_mal(void *opaque, int dcrn, uin= t32_t val) /* Read/clear */ mal->rxdeir &=3D ~val; break; - case MAL0_TXCTP0R: - idx =3D 0; - goto update_tx_ptr; - case MAL0_TXCTP1R: - idx =3D 1; - goto update_tx_ptr; - case MAL0_TXCTP2R: - idx =3D 2; - goto update_tx_ptr; - case MAL0_TXCTP3R: - idx =3D 3; - update_tx_ptr: - mal->txctpr[idx] =3D val; - break; - case MAL0_RXCTP0R: - idx =3D 0; - goto update_rx_ptr; - case MAL0_RXCTP1R: - idx =3D 1; - update_rx_ptr: - mal->rxctpr[idx] =3D val; - break; - case MAL0_RCBS0: - idx =3D 0; - goto update_rx_size; - case MAL0_RCBS1: - idx =3D 1; - update_rx_size: - mal->rcbs[idx] =3D val & 0x000000FF; - break; + } + if (dcrn >=3D MAL0_TXCTP0R && dcrn < MAL0_TXCTP0R + mal->txcnum) { + mal->txctpr[dcrn - MAL0_TXCTP0R] =3D val; + } + if (dcrn >=3D MAL0_RXCTP0R && dcrn < MAL0_RXCTP0R + mal->rxcnum) { + mal->rxctpr[dcrn - MAL0_RXCTP0R] =3D val; + } + if (dcrn >=3D MAL0_RCBS0 && dcrn < MAL0_RCBS0 + mal->rxcnum) { + mal->rcbs[dcrn - MAL0_RCBS0] =3D val & 0x000000FF; } } =20 -static void ppc40x_mal_reset(void *opaque) -{ - ppc40x_mal_t *mal; - - mal =3D opaque; - mal->cfg =3D 0x0007C000; - mal->esr =3D 0x00000000; - mal->ier =3D 0x00000000; - mal->rxcasr =3D 0x00000000; - mal->rxdeir =3D 0x00000000; - mal->rxeobisr =3D 0x00000000; - mal->txcasr =3D 0x00000000; - mal->txdeir =3D 0x00000000; - mal->txeobisr =3D 0x00000000; -} - -void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]) +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, + qemu_irq irqs[4]) { - ppc40x_mal_t *mal; + ppc4xx_mal_t *mal; int i; =20 - mal =3D g_malloc0(sizeof(ppc40x_mal_t)); + assert(txcnum <=3D 32 && rxcnum <=3D 32); + mal =3D g_malloc0(sizeof(*mal)); + mal->txcnum =3D txcnum; + mal->rxcnum =3D rxcnum; + mal->txctpr =3D g_new0(uint32_t, txcnum); + mal->rxctpr =3D g_new0(uint32_t, rxcnum); + mal->rcbs =3D g_new0(uint32_t, rxcnum); for (i =3D 0; i < 4; i++) { mal->irqs[i] =3D irqs[i]; } - qemu_register_reset(&ppc40x_mal_reset, mal); + qemu_register_reset(&ppc4xx_mal_reset, mal); ppc_dcr_register(env, MAL0_CFG, mal, &dcr_read_mal, &dcr_write_mal); ppc_dcr_register(env, MAL0_ESR, @@ -981,20 +948,16 @@ void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[= 4]) mal, &dcr_read_mal, &dcr_write_mal); ppc_dcr_register(env, MAL0_RXDEIR, mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP0R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP1R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP2R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_TXCTP3R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXCTP0R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RXCTP1R, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RCBS0, - mal, &dcr_read_mal, &dcr_write_mal); - ppc_dcr_register(env, MAL0_RCBS1, - mal, &dcr_read_mal, &dcr_write_mal); + for (i =3D 0; i < txcnum; i++) { + ppc_dcr_register(env, MAL0_TXCTP0R + i, + mal, &dcr_read_mal, &dcr_write_mal); + } + for (i =3D 0; i < rxcnum; i++) { + ppc_dcr_register(env, MAL0_RXCTP0R + i, + mal, &dcr_read_mal, &dcr_write_mal); + } + for (i =3D 0; i < rxcnum; i++) { + ppc_dcr_register(env, MAL0_RCBS0 + i, + mal, &dcr_read_mal, &dcr_write_mal); + } } diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index db50cfa..cb0bb55 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -53,7 +53,8 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, i= nt nbanks, hwaddr *ram_sizes, int do_init); =20 -void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4]); +void ppc4xx_mal_init(CPUPPCState *env, uint8_t txcnum, uint8_t rxcnum, + qemu_irq irqs[4]); =20 #define TYPE_PPC4xx_PCI_HOST_BRIDGE "ppc4xx-pcihost" =20 --=20 2.7.6