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[34.92.144.28]) by smtp.gmail.com with ESMTPSA id r26sm6329902pfq.75.2020.05.03.03.16.04 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 03 May 2020 03:16:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references; bh=kOVnj3XkmvoYc1hC7Cs7mmwNxUSyPxksKsz1131mOP4=; b=S1cV3nu5S1WC0b/A8YnYhZ4oYU4HyqxGelTdfMuWNPi7+FkYSpaQ55zhwuTtX1tvYM KEgbRoAUR4x8Gf6lBpFl99sPVmAWRzi7j0H/MzSv+B1mqPLWMFj7MWNAfK16Sio+ENGC l/TEaGGH1jrpFicV9++wPih+n0bpjrRzZdV5K3yTvTomI10lYtFctLEdkX0n50aAKRWi N7SQv4VTKIrdOO7sFl2QS07zYK1FG8wsYm7oVWSjXiVFyfTZMCFNz/Da5hjxgJ3TNrZ2 hRGe1mHt9reiKg4+sZ1F8SE5VmBKbpm4T+cfOR4UhKYRsHWqCPXXqYe6GsBvNTPiWK6u e+kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references; bh=kOVnj3XkmvoYc1hC7Cs7mmwNxUSyPxksKsz1131mOP4=; b=pIPA+PJMlwI2cfUAwulayQR854C6BnsQMfVw46AM+wgw5rcpI6T3CTcl63o+cmbI4k 5ijClehpoMiPKrkNoVOVVnA33AyCq5b4Hg8VryOtpQPQ5DhoyXZzV2AaomtA4T6UhUeA 8jeSWZ/a6YjZOAEsaTDoWhi93XRdCLkzPFa0E3JjFi58OQz6n1VPZBm0VRXetJdYPOEo ZcfB7OHjDWFKosA+TLrV9mHYetmLKQGVfzyfe/xIqEC0tUw4gbhw94JfgvebmRj/M5TF cV1NutRCowsAe/B5+KkxalyKMqOF2g1rbmnXtFjYMn+nK2VJoFaeFxGKaGfWWVPKi2V/ YM/A== X-Gm-Message-State: AGi0PuaEw7siDYB7npYqiVeC7ugAkbf1QOaUXHRN18gl0kdoLHcPiaJ6 TJWILeYUQngTkzUJytJJqZw= X-Google-Smtp-Source: APiQypJIcPvd7AMKh12K8Pq+HalMDkLTJGvhHHb2XIU4LvVIN3R6TW3jVlz0dRV+v/Qjxt70VTS36w== X-Received: by 2002:a17:90a:ba84:: with SMTP id t4mr10460527pjr.81.1588500967166; Sun, 03 May 2020 03:16:07 -0700 (PDT) From: Huacai Chen To: Paolo Bonzini , Thomas Bogendoerfer Subject: [PATCH V3 13/14] KVM: MIPS: Add more MMIO load/store instructions emulation Date: Sun, 3 May 2020 18:06:06 +0800 Message-Id: <1588500367-1056-14-git-send-email-chenhc@lemote.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1588500367-1056-1-git-send-email-chenhc@lemote.com> References: <1588500367-1056-1-git-send-email-chenhc@lemote.com> Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=chenhuacai@gmail.com; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.001, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kvm@vger.kernel.org, Huacai Chen , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jiaxun Yang , qemu-devel@nongnu.org, Aleksandar Markovic , Fuxin Zhang , Huacai Chen , linux-mips@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch add more MMIO load/store instructions emulation, which can be observed in QXL and some other device drivers: 1, LWL, LWR, LDW, LDR, SWL, SWR, SDL and SDR for all MIPS; 2, GSLBX, GSLHX, GSLWX, GSLDX, GSSBX, GSSHX, GSSWX and GSSDX for Loongson-3. Signed-off-by: Huacai Chen Co-developed-by: Jiaxun Yang Reviewed-by: Aleksandar Markovic --- arch/mips/kvm/emulate.c | 480 ++++++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 470 insertions(+), 10 deletions(-) diff --git a/arch/mips/kvm/emulate.c b/arch/mips/kvm/emulate.c index 3946499..71316fa 100644 --- a/arch/mips/kvm/emulate.c +++ b/arch/mips/kvm/emulate.c @@ -1604,6 +1604,7 @@ enum emulation_result kvm_mips_emulate_store(union mi= ps_instruction inst, enum emulation_result er; u32 rt; void *data =3D run->mmio.data; + unsigned int imme; unsigned long curr_pc; =20 /* @@ -1661,6 +1662,211 @@ enum emulation_result kvm_mips_emulate_store(union = mips_instruction inst, vcpu->arch.gprs[rt], *(u8 *)data); break; =20 + case swl_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x3); + run->mmio.len =3D 4; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x3; + switch (imme) { + case 0: + *(u32 *)data =3D ((*(u32 *)data) & 0xffffff00) | + (vcpu->arch.gprs[rt] >> 24); + break; + case 1: + *(u32 *)data =3D ((*(u32 *)data) & 0xffff0000) | + (vcpu->arch.gprs[rt] >> 16); + break; + case 2: + *(u32 *)data =3D ((*(u32 *)data) & 0xff000000) | + (vcpu->arch.gprs[rt] >> 8); + break; + case 3: + *(u32 *)data =3D vcpu->arch.gprs[rt]; + break; + default: + break; + } + + kvm_debug("[%#lx] OP_SWL: eaddr: %#lx, gpr: %#lx, data: %#x\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u32 *)data); + break; + + case swr_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x3); + run->mmio.len =3D 4; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x3; + switch (imme) { + case 0: + *(u32 *)data =3D vcpu->arch.gprs[rt]; + break; + case 1: + *(u32 *)data =3D ((*(u32 *)data) & 0xff) | + (vcpu->arch.gprs[rt] << 8); + break; + case 2: + *(u32 *)data =3D ((*(u32 *)data) & 0xffff) | + (vcpu->arch.gprs[rt] << 16); + break; + case 3: + *(u32 *)data =3D ((*(u32 *)data) & 0xffffff) | + (vcpu->arch.gprs[rt] << 24); + break; + default: + break; + } + + kvm_debug("[%#lx] OP_SWR: eaddr: %#lx, gpr: %#lx, data: %#x\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u32 *)data); + break; + + case sdl_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x7); + + run->mmio.len =3D 8; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x7; + switch (imme) { + case 0: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffffffffff00) | + ((vcpu->arch.gprs[rt] >> 56) & 0xff); + break; + case 1: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffffffff0000) | + ((vcpu->arch.gprs[rt] >> 48) & 0xffff); + break; + case 2: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffffff000000) | + ((vcpu->arch.gprs[rt] >> 40) & 0xffffff); + break; + case 3: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffff00000000) | + ((vcpu->arch.gprs[rt] >> 32) & 0xffffffff); + break; + case 4: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffff0000000000) | + ((vcpu->arch.gprs[rt] >> 24) & 0xffffffffff); + break; + case 5: + *(u64 *)data =3D ((*(u64 *)data) & 0xffff000000000000) | + ((vcpu->arch.gprs[rt] >> 16) & 0xffffffffffff); + break; + case 6: + *(u64 *)data =3D ((*(u64 *)data) & 0xff00000000000000) | + ((vcpu->arch.gprs[rt] >> 8) & 0xffffffffffffff); + break; + case 7: + *(u64 *)data =3D vcpu->arch.gprs[rt]; + break; + default: + break; + } + + kvm_debug("[%#lx] OP_SDL: eaddr: %#lx, gpr: %#lx, data: %llx\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u64 *)data); + break; + + case sdr_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x7); + + run->mmio.len =3D 8; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x7; + switch (imme) { + case 0: + *(u64 *)data =3D vcpu->arch.gprs[rt]; + break; + case 1: + *(u64 *)data =3D ((*(u64 *)data) & 0xff) | + (vcpu->arch.gprs[rt] << 8); + break; + case 2: + *(u64 *)data =3D ((*(u64 *)data) & 0xffff) | + (vcpu->arch.gprs[rt] << 16); + break; + case 3: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffff) | + (vcpu->arch.gprs[rt] << 24); + break; + case 4: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffff) | + (vcpu->arch.gprs[rt] << 32); + break; + case 5: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffffff) | + (vcpu->arch.gprs[rt] << 40); + break; + case 6: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffffffff) | + (vcpu->arch.gprs[rt] << 48); + break; + case 7: + *(u64 *)data =3D ((*(u64 *)data) & 0xffffffffffffff) | + (vcpu->arch.gprs[rt] << 56); + break; + default: + break; + } + + kvm_debug("[%#lx] OP_SDR: eaddr: %#lx, gpr: %#lx, data: %llx\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u64 *)data); + break; + +#ifdef CONFIG_CPU_LOONGSON64 + case sdc2_op: + rt =3D inst.loongson3_lsdc2_format.rt; + switch (inst.loongson3_lsdc2_format.opcode1) { + /* + * Loongson-3 overridden sdc2 instructions. + * opcode1 instruction + * 0x0 gssbx: store 1 bytes from GPR + * 0x1 gsshx: store 2 bytes from GPR + * 0x2 gsswx: store 4 bytes from GPR + * 0x3 gssdx: store 8 bytes from GPR + */ + case 0x0: + run->mmio.len =3D 1; + *(u8 *)data =3D vcpu->arch.gprs[rt]; + + kvm_debug("[%#lx] OP_GSSBX: eaddr: %#lx, gpr: %#lx, data: %#x\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u8 *)data); + break; + case 0x1: + run->mmio.len =3D 2; + *(u16 *)data =3D vcpu->arch.gprs[rt]; + + kvm_debug("[%#lx] OP_GSSSHX: eaddr: %#lx, gpr: %#lx, data: %#x\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u16 *)data); + break; + case 0x2: + run->mmio.len =3D 4; + *(u32 *)data =3D vcpu->arch.gprs[rt]; + + kvm_debug("[%#lx] OP_GSSWX: eaddr: %#lx, gpr: %#lx, data: %#x\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u32 *)data); + break; + case 0x3: + run->mmio.len =3D 8; + *(u64 *)data =3D vcpu->arch.gprs[rt]; + + kvm_debug("[%#lx] OP_GSSDX: eaddr: %#lx, gpr: %#lx, data: %#llx\n", + vcpu->arch.pc, vcpu->arch.host_cp0_badvaddr, + vcpu->arch.gprs[rt], *(u64 *)data); + break; + default: + kvm_err("Godson Exteneded GS-Store not yet supported (inst=3D0x%08x)\n", + inst.word); + break; + } + break; +#endif default: kvm_err("Store not yet supported (inst=3D0x%08x)\n", inst.word); @@ -1695,6 +1901,7 @@ enum emulation_result kvm_mips_emulate_load(union mip= s_instruction inst, enum emulation_result er; unsigned long curr_pc; u32 op, rt; + unsigned int imme; =20 rt =3D inst.i_format.rt; op =3D inst.i_format.opcode; @@ -1747,6 +1954,162 @@ enum emulation_result kvm_mips_emulate_load(union m= ips_instruction inst, run->mmio.len =3D 1; break; =20 + case lwl_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x3); + + run->mmio.len =3D 4; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x3; + switch (imme) { + case 0: + vcpu->mmio_needed =3D 3; /* 1 byte */ + break; + case 1: + vcpu->mmio_needed =3D 4; /* 2 bytes */ + break; + case 2: + vcpu->mmio_needed =3D 5; /* 3 bytes */ + break; + case 3: + vcpu->mmio_needed =3D 6; /* 4 bytes */ + break; + default: + break; + } + break; + + case lwr_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x3); + + run->mmio.len =3D 4; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x3; + switch (imme) { + case 0: + vcpu->mmio_needed =3D 7; /* 4 bytes */ + break; + case 1: + vcpu->mmio_needed =3D 8; /* 3 bytes */ + break; + case 2: + vcpu->mmio_needed =3D 9; /* 2 bytes */ + break; + case 3: + vcpu->mmio_needed =3D 10; /* 1 byte */ + break; + default: + break; + } + break; + + case ldl_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x7); + + run->mmio.len =3D 8; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x7; + switch (imme) { + case 0: + vcpu->mmio_needed =3D 11; /* 1 byte */ + break; + case 1: + vcpu->mmio_needed =3D 12; /* 2 bytes */ + break; + case 2: + vcpu->mmio_needed =3D 13; /* 3 bytes */ + break; + case 3: + vcpu->mmio_needed =3D 14; /* 4 bytes */ + break; + case 4: + vcpu->mmio_needed =3D 15; /* 5 bytes */ + break; + case 5: + vcpu->mmio_needed =3D 16; /* 6 bytes */ + break; + case 6: + vcpu->mmio_needed =3D 17; /* 7 bytes */ + break; + case 7: + vcpu->mmio_needed =3D 18; /* 8 bytes */ + break; + default: + break; + } + break; + + case ldr_op: + run->mmio.phys_addr =3D kvm_mips_callbacks->gva_to_gpa( + vcpu->arch.host_cp0_badvaddr) & (~0x7); + + run->mmio.len =3D 8; + imme =3D vcpu->arch.host_cp0_badvaddr & 0x7; + switch (imme) { + case 0: + vcpu->mmio_needed =3D 19; /* 8 bytes */ + break; + case 1: + vcpu->mmio_needed =3D 20; /* 7 bytes */ + break; + case 2: + vcpu->mmio_needed =3D 21; /* 6 bytes */ + break; + case 3: + vcpu->mmio_needed =3D 22; /* 5 bytes */ + break; + case 4: + vcpu->mmio_needed =3D 23; /* 4 bytes */ + break; + case 5: + vcpu->mmio_needed =3D 24; /* 3 bytes */ + break; + case 6: + vcpu->mmio_needed =3D 25; /* 2 bytes */ + break; + case 7: + vcpu->mmio_needed =3D 26; /* 1 byte */ + break; + default: + break; + } + break; + +#ifdef CONFIG_CPU_LOONGSON64 + case ldc2_op: + rt =3D inst.loongson3_lsdc2_format.rt; + switch (inst.loongson3_lsdc2_format.opcode1) { + /* + * Loongson-3 overridden ldc2 instructions. + * opcode1 instruction + * 0x0 gslbx: store 1 bytes from GPR + * 0x1 gslhx: store 2 bytes from GPR + * 0x2 gslwx: store 4 bytes from GPR + * 0x3 gsldx: store 8 bytes from GPR + */ + case 0x0: + run->mmio.len =3D 1; + vcpu->mmio_needed =3D 27; /* signed */ + break; + case 0x1: + run->mmio.len =3D 2; + vcpu->mmio_needed =3D 28; /* signed */ + break; + case 0x2: + run->mmio.len =3D 4; + vcpu->mmio_needed =3D 29; /* signed */ + break; + case 0x3: + run->mmio.len =3D 8; + vcpu->mmio_needed =3D 30; /* signed */ + break; + default: + kvm_err("Godson Exteneded GS-Load for float not yet supported (inst=3D0= x%08x)\n", + inst.word); + break; + } + break; +#endif + default: kvm_err("Load not yet supported (inst=3D0x%08x)\n", inst.word); @@ -2612,28 +2975,125 @@ enum emulation_result kvm_mips_complete_mmio_load(= struct kvm_vcpu *vcpu, =20 switch (run->mmio.len) { case 8: - *gpr =3D *(s64 *)run->mmio.data; + switch (vcpu->mmio_needed) { + case 11: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffffff) | + (((*(s64 *)run->mmio.data) & 0xff) << 56); + break; + case 12: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffff) | + (((*(s64 *)run->mmio.data) & 0xffff) << 48); + break; + case 13: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffff) | + (((*(s64 *)run->mmio.data) & 0xffffff) << 40); + break; + case 14: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffff) | + (((*(s64 *)run->mmio.data) & 0xffffffff) << 32); + break; + case 15: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff) | + (((*(s64 *)run->mmio.data) & 0xffffffffff) << 24); + break; + case 16: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff) | + (((*(s64 *)run->mmio.data) & 0xffffffffffff) << 16); + break; + case 17: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff) | + (((*(s64 *)run->mmio.data) & 0xffffffffffffff) << 8); + break; + case 18: + case 19: + *gpr =3D *(s64 *)run->mmio.data; + break; + case 20: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff00000000000000) | + ((((*(s64 *)run->mmio.data)) >> 8) & 0xffffffffffffff); + break; + case 21: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff000000000000) | + ((((*(s64 *)run->mmio.data)) >> 16) & 0xffffffffffff); + break; + case 22: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff0000000000) | + ((((*(s64 *)run->mmio.data)) >> 24) & 0xffffffffff); + break; + case 23: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffff00000000) | + ((((*(s64 *)run->mmio.data)) >> 32) & 0xffffffff); + break; + case 24: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffff000000) | + ((((*(s64 *)run->mmio.data)) >> 40) & 0xffffff); + break; + case 25: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffff0000) | + ((((*(s64 *)run->mmio.data)) >> 48) & 0xffff); + break; + case 26: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffffffffffff00) | + ((((*(s64 *)run->mmio.data)) >> 56) & 0xff); + break; + default: + *gpr =3D *(s64 *)run->mmio.data; + } break; =20 case 4: - if (vcpu->mmio_needed =3D=3D 2) - *gpr =3D *(s32 *)run->mmio.data; - else + switch (vcpu->mmio_needed) { + case 1: *gpr =3D *(u32 *)run->mmio.data; + break; + case 2: + *gpr =3D *(s32 *)run->mmio.data; + break; + case 3: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff) | + (((*(s32 *)run->mmio.data) & 0xff) << 24); + break; + case 4: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff) | + (((*(s32 *)run->mmio.data) & 0xffff) << 16); + break; + case 5: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff) | + (((*(s32 *)run->mmio.data) & 0xffffff) << 8); + break; + case 6: + case 7: + *gpr =3D *(s32 *)run->mmio.data; + break; + case 8: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xff000000) | + ((((*(s32 *)run->mmio.data)) >> 8) & 0xffffff); + break; + case 9: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffff0000) | + ((((*(s32 *)run->mmio.data)) >> 16) & 0xffff); + break; + case 10: + *gpr =3D (vcpu->arch.gprs[vcpu->arch.io_gpr] & 0xffffff00) | + ((((*(s32 *)run->mmio.data)) >> 24) & 0xff); + break; + default: + *gpr =3D *(s32 *)run->mmio.data; + } break; =20 case 2: - if (vcpu->mmio_needed =3D=3D 2) - *gpr =3D *(s16 *) run->mmio.data; - else + if (vcpu->mmio_needed =3D=3D 1) *gpr =3D *(u16 *)run->mmio.data; + else + *gpr =3D *(s16 *)run->mmio.data; =20 break; case 1: - if (vcpu->mmio_needed =3D=3D 2) - *gpr =3D *(s8 *) run->mmio.data; + if (vcpu->mmio_needed =3D=3D 1) + *gpr =3D *(u8 *)run->mmio.data; else - *gpr =3D *(u8 *) run->mmio.data; + *gpr =3D *(s8 *)run->mmio.data; break; } =20 --=20 2.7.0