From nobody Thu May 16 10:21:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1586883380; cv=none; d=zohomail.com; s=zohoarc; b=k6M1Z32IDBb6VdJARX6D/xu3cVNNcNINwBKpBgNgR47B9TqzhX79hTeZxwDdz9useKVae8A6Akzw12vSGWO+ighTlnAwoI++wPh2ePfvCF2aeXDEV7du/XIEv7J2ksmE4YGIILbXGawh6I6RXwLe/KWxCNAMxqnLdYEXEIisZ2c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586883380; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Q+VQSZr27Y9jgdh+7h8Ttf/aLMkDDFKY6HXCIa4W4Ug=; b=AU6itnYgOPSWBVtggqow9j8BG9vlpUVXYD8aEYZRMoZnZ1GPfSamXPPR/ABA06LOCeqlJUMN90oeHoclc2U6Aqfxl9Tk1E3+2JLBZhNcXUvxjTVTBcJFX/zU17SipLcBJmB1a15LXPWp1FhrpdoY+FNcTeHRx52Rp3SIfCcyNyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586883380128721.8576420786178; Tue, 14 Apr 2020 09:56:20 -0700 (PDT) Received: from localhost ([::1]:35170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOOrC-0006QT-P1 for importer@patchew.org; Tue, 14 Apr 2020 12:56:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58638) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOOfC-0003cx-9X for qemu-devel@nongnu.org; Tue, 14 Apr 2020 12:43:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOOf9-0007CE-Br for qemu-devel@nongnu.org; Tue, 14 Apr 2020 12:43:54 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:39141) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jON5M-0003ct-7i; Tue, 14 Apr 2020 11:02:48 -0400 Received: by mail-pf1-x436.google.com with SMTP id k15so32599pfh.6; Tue, 14 Apr 2020 08:02:48 -0700 (PDT) Received: from hyd1358.marvell.com ([115.113.156.2]) by smtp.googlemail.com with ESMTPSA id f9sm12175240pjt.45.2020.04.14.08.02.44 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Apr 2020 08:02:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q+VQSZr27Y9jgdh+7h8Ttf/aLMkDDFKY6HXCIa4W4Ug=; b=FoVV6D+35mkn1rgX2uS7VmY2wal3nWMZLd1CJljQDh8Blw3BtfqDEX+p7CY+5ct06L eiI9PgTrtHayCErkw3xMncFcLqy1E4ISeNsGLMIUJWxe+4TI0fMMM7Bk7x9kX11DFs2t CLROi+j4LCxnB/uO40wKGnyfaLBzHIv6rXFUOo2NvtQeObrOKXz1ePCY9lQlITbH/7+P KLBvFyWyARYbgCwK6hkobBGDyRVLDoeLuDvNJGlsK0AFUArYFPNpFr8ag1p6/VfnjyP7 kWuq73JBhPG9eXMdbwbczf6RXbQSsHOUT/wvb61+2vEQ+aIwCAiSm5AxSC2VRqPdZ8ni mS3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q+VQSZr27Y9jgdh+7h8Ttf/aLMkDDFKY6HXCIa4W4Ug=; b=sG803UsnsoXELSRdjqj+BeqdOGddELVyLbp2byFGQIQv30oQVI9naTA8ZD+fAcgByv EZz9rYbGmr6YnpD2lLwdSS+GmqbkWDjWDFKeZ+69bkIEERPcZbRIAehNSfSC+sX35K9n fcbHy8WulKwSp7Ct2ii82ax1h09LaNt4RA1vcNVK9RSHJdi9GXEsYXYDwjL9R4wcJHBE Lm2w4hVDEsXIvbmp7X2E99+Exi78HfTy2ui4j9s6jrix8XzwR7mv5PDUUqjcOaw40fB5 KZ6L0PGup1GD7MaXQtwdLoVLbaVkIWn3nilWqgzrHyIU5kS0H7w0NwIhjqS6pWtycNQi +gZQ== X-Gm-Message-State: AGi0PuYofZjKnXFWeywXpoEG03XPrgO5aSbm8ECuFrwcFPd0IVmNd+vz kdCTTOf0w7DATD0nLmzOamE= X-Google-Smtp-Source: APiQypKgq/ZsjctBWB3aPCUMr4t8kS6Kvh2rMuS0Y0Kq4RyHdfq6Hg+niDTpEY++dJwF5dIFrkTYrg== X-Received: by 2002:a62:cd46:: with SMTP id o67mr1845380pfg.257.1586876566892; Tue, 14 Apr 2020 08:02:46 -0700 (PDT) From: sundeep.lkml@gmail.com To: jasowang@redhat.com, peter.maydell@linaro.org, philmd@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [Qemu devel PATCH v5 1/3] hw/net: Add Smartfusion2 emac block Date: Tue, 14 Apr 2020 20:32:29 +0530 Message-Id: <1586876551-3695-2-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586876551-3695-1-git-send-email-sundeep.lkml@gmail.com> References: <1586876551-3695-1-git-send-email-sundeep.lkml@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Subbaraya Sundeep Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) From: Subbaraya Sundeep Modelled Ethernet MAC of Smartfusion2 SoC. Micrel KSZ8051 PHY is present on Emcraft's SOM kit hence same PHY is emulated. Signed-off-by: Subbaraya Sundeep Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 2 + hw/net/Makefile.objs | 1 + hw/net/msf2-emac.c | 566 +++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/net/msf2-emac.h | 53 +++++ 4 files changed, 622 insertions(+) create mode 100644 hw/net/msf2-emac.c create mode 100644 include/hw/net/msf2-emac.h diff --git a/MAINTAINERS b/MAINTAINERS index 642c8e0..9d0ff20 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -919,6 +919,8 @@ F: include/hw/arm/msf2-soc.h F: include/hw/misc/msf2-sysreg.h F: include/hw/timer/mss-timer.h F: include/hw/ssi/mss-spi.h +F: hw/net/msf2-emac.c +F: include/hw/net/msf2-emac.h =20 Emcraft M2S-FG484 M: Subbaraya Sundeep diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index af4d194..f2b7398 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -55,3 +55,4 @@ common-obj-$(CONFIG_ROCKER) +=3D rocker/rocker.o rocker/r= ocker_fp.o \ obj-$(call lnot,$(CONFIG_ROCKER)) +=3D rocker/qmp-norocker.o =20 common-obj-$(CONFIG_CAN_BUS) +=3D can/ +common-obj-$(CONFIG_MSF2) +=3D msf2-emac.o diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c new file mode 100644 index 0000000..cae40fd --- /dev/null +++ b/hw/net/msf2-emac.c @@ -0,0 +1,566 @@ +/* + * QEMU model of the Smartfusion2 Ethernet MAC. + * + * Copyright (c) 2020 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + * + * Refer to section Ethernet MAC in the document: + * UG0331: SmartFusion2 Microcontroller Subsystem User Guide + * Datasheet URL: + * https://www.microsemi.com/document-portal/cat_view/56661-internal-docum= ents/ + * 56758-soc?lang=3Den&limit=3D20&limitstart=3D220 + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "hw/registerfields.h" +#include "hw/net/msf2-emac.h" +#include "hw/net/mii.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +REG32(CFG1, 0x0) + FIELD(CFG1, RESET, 31, 1) + FIELD(CFG1, RX_EN, 2, 1) + FIELD(CFG1, TX_EN, 0, 1) + FIELD(CFG1, LB_EN, 8, 1) +REG32(CFG2, 0x4) +REG32(IFG, 0x8) +REG32(HALF_DUPLEX, 0xc) +REG32(MAX_FRAME_LENGTH, 0x10) +REG32(MII_CMD, 0x24) + FIELD(MII_CMD, READ, 0, 1) +REG32(MII_ADDR, 0x28) + FIELD(MII_ADDR, REGADDR, 0, 5) + FIELD(MII_ADDR, PHYADDR, 8, 5) +REG32(MII_CTL, 0x2c) +REG32(MII_STS, 0x30) +REG32(STA1, 0x40) +REG32(STA2, 0x44) +REG32(FIFO_CFG0, 0x48) +REG32(DMA_TX_CTL, 0x180) + FIELD(DMA_TX_CTL, EN, 0, 1) +REG32(DMA_TX_DESC, 0x184) +REG32(DMA_TX_STATUS, 0x188) + FIELD(DMA_TX_STATUS, PKTCNT, 16, 8) + FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1) + FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1) +REG32(DMA_RX_CTL, 0x18c) + FIELD(DMA_RX_CTL, EN, 0, 1) +REG32(DMA_RX_DESC, 0x190) +REG32(DMA_RX_STATUS, 0x194) + FIELD(DMA_RX_STATUS, PKTCNT, 16, 8) + FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1) + FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1) +REG32(DMA_IRQ_MASK, 0x198) +REG32(DMA_IRQ, 0x19c) + +#define EMPTY_MASK (1 << 31) +#define PKT_SIZE 0x7FF +#define PHYADDR 0x1 +#define MAX_PKT_SIZE 2048 + +typedef struct { + uint32_t pktaddr; + uint32_t pktsize; + uint32_t next; +} EmacDesc; + +static uint32_t emac_get_isr(MSF2EmacState *s) +{ + uint32_t ier =3D s->regs[R_DMA_IRQ_MASK]; + uint32_t tx =3D s->regs[R_DMA_TX_STATUS] & 0xF; + uint32_t rx =3D s->regs[R_DMA_RX_STATUS] & 0xF; + uint32_t isr =3D (rx << 4) | tx; + + s->regs[R_DMA_IRQ] =3D ier & isr; + return s->regs[R_DMA_IRQ]; +} + +static void emac_update_irq(MSF2EmacState *s) +{ + bool intr =3D emac_get_isr(s); + + qemu_set_irq(s->irq, intr); +} + +static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) +{ + address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof= *d); + /* Convert from LE into host endianness. */ + d->pktaddr =3D le32_to_cpu(d->pktaddr); + d->pktsize =3D le32_to_cpu(d->pktsize); + d->next =3D le32_to_cpu(d->next); +} + +static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) +{ + /* Convert from host endianness into LE. */ + d->pktaddr =3D cpu_to_le32(d->pktaddr); + d->pktsize =3D cpu_to_le32(d->pktsize); + d->next =3D cpu_to_le32(d->next); + + address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeo= f *d); +} + +static void msf2_dma_tx(MSF2EmacState *s) +{ + NetClientState *nc =3D qemu_get_queue(s->nic); + hwaddr desc =3D s->regs[R_DMA_TX_DESC]; + uint8_t buf[MAX_PKT_SIZE]; + EmacDesc d; + int size; + uint8_t pktcnt; + uint32_t status; + + if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) { + return; + } + + while (1) { + emac_load_desc(s, &d, desc); + if (d.pktsize & EMPTY_MASK) { + break; + } + size =3D d.pktsize & PKT_SIZE; + address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, + buf, size); + /* + * This is very basic way to send packets. Ideally there should be + * a FIFO and packets should be sent out from FIFO only when + * R_CFG1 bit 0 is set. + */ + if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) { + nc->info->receive(nc, buf, size); + } else { + qemu_send_packet(nc, buf, size); + } + d.pktsize |=3D EMPTY_MASK; + emac_store_desc(s, &d, desc); + /* update sent packets count */ + status =3D s->regs[R_DMA_TX_STATUS]; + pktcnt =3D FIELD_EX32(status, DMA_TX_STATUS, PKTCNT); + pktcnt++; + s->regs[R_DMA_TX_STATUS] =3D FIELD_DP32(status, DMA_TX_STATUS, + PKTCNT, pktcnt); + s->regs[R_DMA_TX_STATUS] |=3D R_DMA_TX_STATUS_PKT_SENT_MASK; + desc =3D d.next; + } + s->regs[R_DMA_TX_STATUS] |=3D R_DMA_TX_STATUS_UNDERRUN_MASK; + s->regs[R_DMA_TX_CTL] &=3D ~R_DMA_TX_CTL_EN_MASK; +} + +static void msf2_phy_update_link(MSF2EmacState *s) +{ + /* Autonegotiation status mirrors link status. */ + if (qemu_get_queue(s->nic)->link_down) { + s->phy_regs[MII_BMSR] &=3D ~(MII_BMSR_AN_COMP | + MII_BMSR_LINK_ST); + } else { + s->phy_regs[MII_BMSR] |=3D (MII_BMSR_AN_COMP | + MII_BMSR_LINK_ST); + } +} + +static void msf2_phy_reset(MSF2EmacState *s) +{ + memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); + s->phy_regs[MII_BMCR] =3D 0x1140; + s->phy_regs[MII_BMSR] =3D 0x7968; + s->phy_regs[MII_PHYID1] =3D 0x0022; + s->phy_regs[MII_PHYID2] =3D 0x1550; + s->phy_regs[MII_ANAR] =3D 0x01E1; + s->phy_regs[MII_ANLPAR] =3D 0xCDE1; + + msf2_phy_update_link(s); +} + +static void write_to_phy(MSF2EmacState *s) +{ + uint8_t reg_addr =3D s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; + uint8_t phy_addr =3D (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT)= & + R_MII_ADDR_REGADDR_MASK; + uint16_t data =3D s->regs[R_MII_CTL] & 0xFFFF; + + if (phy_addr !=3D PHYADDR) { + return; + } + + switch (reg_addr) { + case MII_BMCR: + if (data & MII_BMCR_RESET) { + /* Phy reset */ + msf2_phy_reset(s); + data &=3D ~MII_BMCR_RESET; + } + if (data & MII_BMCR_AUTOEN) { + /* Complete autonegotiation immediately */ + data &=3D ~MII_BMCR_AUTOEN; + s->phy_regs[MII_BMSR] |=3D MII_BMSR_AN_COMP; + } + break; + } + + s->phy_regs[reg_addr] =3D data; +} + +static uint16_t read_from_phy(MSF2EmacState *s) +{ + uint8_t reg_addr =3D s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; + uint8_t phy_addr =3D (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT)= & + R_MII_ADDR_REGADDR_MASK; + + if (phy_addr =3D=3D PHYADDR) { + return s->phy_regs[reg_addr]; + } else { + return 0xFFFF; + } +} + +static void msf2_emac_do_reset(MSF2EmacState *s) +{ + memset(&s->regs[0], 0, sizeof(s->regs)); + s->regs[R_CFG1] =3D 0x80000000; + s->regs[R_CFG2] =3D 0x00007000; + s->regs[R_IFG] =3D 0x40605060; + s->regs[R_HALF_DUPLEX] =3D 0x00A1F037; + s->regs[R_MAX_FRAME_LENGTH] =3D 0x00000600; + + msf2_phy_reset(s); +} + +static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSF2EmacState *s =3D opaque; + uint32_t r =3D 0; + + addr >>=3D 2; + + switch (addr) { + case R_DMA_IRQ: + r =3D emac_get_isr(s); + break; + default: + if (addr >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + return r; + } + r =3D s->regs[addr]; + break; + } + return r; +} + +static void emac_write(void *opaque, hwaddr addr, uint64_t val64, + unsigned int size) +{ + MSF2EmacState *s =3D opaque; + uint32_t value =3D val64; + uint32_t enreqbits; + uint8_t pktcnt; + + addr >>=3D 2; + switch (addr) { + case R_DMA_TX_CTL: + s->regs[addr] =3D value; + if (value & R_DMA_TX_CTL_EN_MASK) { + msf2_dma_tx(s); + } + break; + case R_DMA_RX_CTL: + s->regs[addr] =3D value; + if (value & R_DMA_RX_CTL_EN_MASK) { + s->rx_desc =3D s->regs[R_DMA_RX_DESC]; + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } + break; + case R_CFG1: + if (value & R_CFG1_RESET_MASK) { + msf2_emac_do_reset(s); + } + case R_FIFO_CFG0: + /* + * For our implementation, turning on modules is instantaneous, + * so the states requested via the *ENREQ bits appear in the + * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC + * module are not emulated here since it deals with start of frames, + * inter-packet gap and control frames. + */ + enreqbits =3D extract32(value, 8, 5); + s->regs[addr] =3D deposit32(value, 16, 5, enreqbits); + break; + case R_DMA_TX_DESC: + if (value & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should b= e" + " 32 bit aligned\n"); + } + /* Ignore [1:0] bits */ + s->regs[addr] =3D value & ~3; + break; + case R_DMA_RX_DESC: + if (value & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should b= e" + " 32 bit aligned\n"); + } + /* Ignore [1:0] bits */ + s->regs[addr] =3D value & ~3; + break; + case R_DMA_TX_STATUS: + if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) { + s->regs[addr] &=3D ~R_DMA_TX_STATUS_UNDERRUN_MASK; + } + if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) { + pktcnt =3D FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT); + pktcnt--; + s->regs[addr] =3D FIELD_DP32(s->regs[addr], DMA_TX_STATUS, + PKTCNT, pktcnt); + if (pktcnt =3D=3D 0) { + s->regs[addr] &=3D ~R_DMA_TX_STATUS_PKT_SENT_MASK; + } + } + break; + case R_DMA_RX_STATUS: + if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) { + s->regs[addr] &=3D ~R_DMA_RX_STATUS_OVERFLOW_MASK; + } + if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) { + pktcnt =3D FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT); + pktcnt--; + s->regs[addr] =3D FIELD_DP32(s->regs[addr], DMA_RX_STATUS, + PKTCNT, pktcnt); + if (pktcnt =3D=3D 0) { + s->regs[addr] &=3D ~R_DMA_RX_STATUS_PKT_RCVD_MASK; + } + } + break; + case R_DMA_IRQ: + break; + case R_MII_CMD: + if (value & R_MII_CMD_READ_MASK) { + s->regs[R_MII_STS] =3D read_from_phy(s); + } + break; + case R_MII_CTL: + s->regs[addr] =3D value; + write_to_phy(s); + break; + case R_STA1: + s->regs[addr] =3D value; + /* + * R_STA1 [31:24] : octet 1 of mac address + * R_STA1 [23:16] : octet 2 of mac address + * R_STA1 [15:8] : octet 3 of mac address + * R_STA1 [7:0] : octet 4 of mac address + */ + stl_le_p(s->mac_addr, value); + break; + case R_STA2: + s->regs[addr] =3D value; + /* + * R_STA2 [31:24] : octet 5 of mac address + * R_STA2 [23:16] : octet 6 of mac address + */ + stw_le_p(s->mac_addr + 4, value >> 16); + break; + default: + if (addr >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + return; + } + s->regs[addr] =3D value; + break; + } + emac_update_irq(s); +} + +static const MemoryRegionOps emac_ops =3D { + .read =3D emac_read, + .write =3D emac_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static bool emac_can_rx(NetClientState *nc) +{ + MSF2EmacState *s =3D qemu_get_nic_opaque(nc); + + return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) && + (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK); +} + +static bool match_addr(MSF2EmacState *s, const uint8_t *buf) +{ + /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */ + static const uint8_t broadcast_addr[] =3D { 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF }; + + if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) { + return true; + } + + if (!memcmp(buf, s->mac_addr, sizeof(s->mac_addr))) { + return false; + } + + return true; +} + +static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size) +{ + MSF2EmacState *s =3D qemu_get_nic_opaque(nc); + EmacDesc d; + uint8_t pktcnt; + uint32_t status; + + if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) { + return size; + } + if (!match_addr(s, buf)) { + return size; + } + + emac_load_desc(s, &d, s->rx_desc); + + if (d.pktsize & EMPTY_MASK) { + address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, + buf, size & PKT_SIZE); + d.pktsize =3D size & PKT_SIZE; + emac_store_desc(s, &d, s->rx_desc); + /* update received packets count */ + status =3D s->regs[R_DMA_RX_STATUS]; + pktcnt =3D FIELD_EX32(status, DMA_RX_STATUS, PKTCNT); + pktcnt++; + s->regs[R_DMA_RX_STATUS] =3D FIELD_DP32(status, DMA_RX_STATUS, + PKTCNT, pktcnt); + s->regs[R_DMA_RX_STATUS] |=3D R_DMA_RX_STATUS_PKT_RCVD_MASK; + s->rx_desc =3D d.next; + } else { + s->regs[R_DMA_RX_CTL] &=3D ~R_DMA_RX_CTL_EN_MASK; + s->regs[R_DMA_RX_STATUS] |=3D R_DMA_RX_STATUS_OVERFLOW_MASK; + } + emac_update_irq(s); + return size; +} + +static void msf2_emac_reset(DeviceState *dev) +{ + MSF2EmacState *s =3D MSS_EMAC(dev); + + msf2_emac_do_reset(s); +} + +static void emac_set_link(NetClientState *nc) +{ + MSF2EmacState *s =3D qemu_get_nic_opaque(nc); + + msf2_phy_update_link(s); +} + +static NetClientInfo net_msf2_emac_info =3D { + .type =3D NET_CLIENT_DRIVER_NIC, + .size =3D sizeof(NICState), + .can_receive =3D emac_can_rx, + .receive =3D emac_rx, + .link_status_changed =3D emac_set_link, +}; + +static void msf2_emac_realize(DeviceState *dev, Error **errp) +{ + MSF2EmacState *s =3D MSS_EMAC(dev); + + if (!s->dma_mr) { + error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); + return; + } + + address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); + + qemu_macaddr_default_if_unset(&s->conf.macaddr); + s->nic =3D qemu_new_nic(&net_msf2_emac_info, &s->conf, + object_get_typename(OBJECT(dev)), dev->id, s); + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); +} + +static void msf2_emac_init(Object *obj) +{ + MSF2EmacState *s =3D MSS_EMAC(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &emac_ops, s, + "msf2-emac", R_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static Property msf2_emac_properties[] =3D { + DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_NIC_PROPERTIES(MSF2EmacState, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_msf2_emac =3D { + .name =3D TYPE_MSS_EMAC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN), + VMSTATE_UINT32(rx_desc, MSF2EmacState), + VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS), + VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void msf2_emac_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D msf2_emac_realize; + dc->reset =3D msf2_emac_reset; + dc->vmsd =3D &vmstate_msf2_emac; + device_class_set_props(dc, msf2_emac_properties); +} + +static const TypeInfo msf2_emac_info =3D { + .name =3D TYPE_MSS_EMAC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSF2EmacState), + .instance_init =3D msf2_emac_init, + .class_init =3D msf2_emac_class_init, +}; + +static void msf2_emac_register_types(void) +{ + type_register_static(&msf2_emac_info); +} + +type_init(msf2_emac_register_types) diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h new file mode 100644 index 0000000..37966d3 --- /dev/null +++ b/include/hw/net/msf2-emac.h @@ -0,0 +1,53 @@ +/* + * QEMU model of the Smartfusion2 Ethernet MAC. + * + * Copyright (c) 2020 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "hw/sysbus.h" +#include "exec/memory.h" +#include "net/net.h" +#include "net/eth.h" + +#define TYPE_MSS_EMAC "msf2-emac" +#define MSS_EMAC(obj) \ + OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC) + +#define R_MAX (0x1a0 / 4) +#define PHY_MAX_REGS 32 + +typedef struct MSF2EmacState { + SysBusDevice parent; + + MemoryRegion mmio; + MemoryRegion *dma_mr; + AddressSpace dma_as; + + qemu_irq irq; + NICState *nic; + NICConf conf; + + uint8_t mac_addr[ETH_ALEN]; + uint32_t rx_desc; + uint16_t phy_regs[PHY_MAX_REGS]; + + uint32_t regs[R_MAX]; +} MSF2EmacState; --=20 2.7.4 From nobody Thu May 16 10:21:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1586885806; cv=none; d=zohomail.com; s=zohoarc; b=Gtag3JmIkfCTRt2obf6L94zecxm+D2KFo5nR+Mp5hb75KekujcQYEUQ4RJVDqt3sucKUdpCQSl3dutErlNabtwcng9za5cyN5l8qJ6o/EKRCLz/5isMrwwdHDVvU8E692cS/CcZvlmmhmWQjkBVYNmDUSUS77tTsuyd0CS1eRJw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586885806; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CUyXXTyShFlx2/maCp5HGaaaIrvw4HRoNrxDU7Mf/kQ=; b=DRMXWanWc7CGQXutHzVbjTYRTcE7JNVlGIgEqxet6d9VkDgDR42Hjn7g8cDaalW86qiSAbh7tlFOljy6F+vG01OdR0K1Dn76syc1fxSaNC0qKMTP8j8GKBwgl5+n7zt66VzDFOrjNbAzgOTus8hl30lqX9CGQnJe3N9PLgYi7zw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586885806351634.3190058805374; Tue, 14 Apr 2020 10:36:46 -0700 (PDT) Received: from localhost ([::1]:36486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOPUL-0000iy-4r for importer@patchew.org; Tue, 14 Apr 2020 13:36:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46773) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOP9J-0001e0-Qf for qemu-devel@nongnu.org; Tue, 14 Apr 2020 13:15:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOP9H-0005t4-Of for qemu-devel@nongnu.org; Tue, 14 Apr 2020 13:15:01 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:36041) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jON5O-0003dY-JW; Tue, 14 Apr 2020 11:02:50 -0400 Received: by mail-pf1-x443.google.com with SMTP id n10so39092pff.3; Tue, 14 Apr 2020 08:02:50 -0700 (PDT) Received: from hyd1358.marvell.com ([115.113.156.2]) by smtp.googlemail.com with ESMTPSA id f9sm12175240pjt.45.2020.04.14.08.02.47 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Apr 2020 08:02:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CUyXXTyShFlx2/maCp5HGaaaIrvw4HRoNrxDU7Mf/kQ=; b=WluseXrBHnVseij7jQRu9iNU5Wspkl85BKByw1Ua6dODwWIgNS01Q+3np+07qVQ957 o7syHT4q3eI+sEPmYMQFUi5R6yr/xUQjQp5A+Ruxf55+3IFoyB9qC+AImyuKAtZdp8sZ 9D/M1wQPCXLLizkp83+404zHMTn+cofqj+RZSRhA633VLVWcmPlSW4AmzoBT3xV/xxsH BJ+sdVrQLlLWnIC2yeN3d8e3HL59jyJVnKV0O1Wr1dSNkt62tIzK82oiTjrXSgGVqJEZ Tak0Ef6TSC9D0Qm7SKB7nr5qNpuFXge4rPd2fQJbuvn3gXwMgfq3NTzYAOfHKLRCxqA9 C1RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CUyXXTyShFlx2/maCp5HGaaaIrvw4HRoNrxDU7Mf/kQ=; b=DH+s8sJSvYyriSol6ODS1HyzbK0YA03eGbh4JkN5xdzooMpl1WVGoYU8mXVtgh1Vl6 jxFyddcqddCR75q95KczDL4w6gr1CjYirPaF8tbSXddF8XzJLNPNcQBRixb3p2C7VcTk xBMER21ZPQP4d92KEcNJXL2sUpp8TdzA2oELMaui8LhXc9LSMLyd3y8Cgar6Ko5CavXk qMfH9pBFd0YBr7e1J6fGoY+XNJrr3amHmB9XE5huEn7KGSIEmPMoLv/Jqk/u1Rdn2PGg 6boD1Byw6wteRFm9se3x2gRfX91bGc/BjHZm1UghfYV75rDL+M2nM3ZCaL9EH5qc5z60 9Dmg== X-Gm-Message-State: AGi0PuaJIqwVwa1tVtWqGSWL967EmartqoOwbsFqLY/Xvs7bMmrhy84M 8mlk/b9ofOrHCNVHhMdLKSM= X-Google-Smtp-Source: APiQypLA3nkmae9WXEicCHRkDPc7v+YfS2XFktrXRQqafvYcW8ENN61I9Uer7+5uZnqhltc5hB5Gcw== X-Received: by 2002:a63:4004:: with SMTP id n4mr11361362pga.234.1586876569594; Tue, 14 Apr 2020 08:02:49 -0700 (PDT) From: sundeep.lkml@gmail.com To: jasowang@redhat.com, peter.maydell@linaro.org, philmd@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [Qemu devel PATCH v5 2/3] msf2: Add EMAC block to SmartFusion2 SoC Date: Tue, 14 Apr 2020 20:32:30 +0530 Message-Id: <1586876551-3695-3-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586876551-3695-1-git-send-email-sundeep.lkml@gmail.com> References: <1586876551-3695-1-git-send-email-sundeep.lkml@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Subbaraya Sundeep Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) From: Subbaraya Sundeep With SmartFusion2 Ethernet MAC model in place this patch adds the same to SoC. Signed-off-by: Subbaraya Sundeep Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/msf2-soc.c | 26 ++++++++++++++++++++++++-- include/hw/arm/msf2-soc.h | 2 ++ 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 588d643..a455b88 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -1,7 +1,7 @@ /* * SmartFusion2 SoC emulation. * - * Copyright (c) 2017 Subbaraya Sundeep + * Copyright (c) 2017-2020 Subbaraya Sundeep * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -35,11 +35,14 @@ =20 #define MSF2_TIMER_BASE 0x40004000 #define MSF2_SYSREG_BASE 0x40038000 +#define MSF2_EMAC_BASE 0x40041000 =20 #define ENVM_BASE_ADDRESS 0x60000000 =20 #define SRAM_BASE_ADDRESS 0x20000000 =20 +#define MSF2_EMAC_IRQ 12 + #define MSF2_ENVM_MAX_SIZE (512 * KiB) =20 /* @@ -81,6 +84,13 @@ static void m2sxxx_soc_initfn(Object *obj) sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), TYPE_MSS_SPI); } + + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), + TYPE_MSS_EMAC); + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC); + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); + } } =20 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -192,6 +202,19 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, E= rror **errp) g_free(bus_name); } =20 + dev =3D DEVICE(&s->emac); + object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()), + "ahb-bus", &error_abort); + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ)); + /* Below devices are not modelled yet. */ create_unimplemented_device("i2c_0", 0x40002000, 0x1000); create_unimplemented_device("dma", 0x40003000, 0x1000); @@ -202,7 +225,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) create_unimplemented_device("can", 0x40015000, 0x1000); create_unimplemented_device("rtc", 0x40017000, 0x1000); create_unimplemented_device("apb_config", 0x40020000, 0x10000); - create_unimplemented_device("emac", 0x40041000, 0x1000); create_unimplemented_device("usb", 0x40043000, 0x1000); } =20 diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 3cfe5c7..c9cb214 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -29,6 +29,7 @@ #include "hw/timer/mss-timer.h" #include "hw/misc/msf2-sysreg.h" #include "hw/ssi/mss-spi.h" +#include "hw/net/msf2-emac.h" =20 #define TYPE_MSF2_SOC "msf2-soc" #define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) @@ -62,6 +63,7 @@ typedef struct MSF2State { MSF2SysregState sysreg; MSSTimerState timer; MSSSpiState spi[MSF2_NUM_SPIS]; + MSF2EmacState emac; } MSF2State; =20 #endif --=20 2.7.4 From nobody Thu May 16 10:21:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1586884621; cv=none; d=zohomail.com; s=zohoarc; b=nKnLUx5TQYcaYaRh85QZYRq5OjXwqvlPwAHE/GV1QQMn2HKbn5mlrsFozluvtjI2gcZmrC9P14SrPBUWyhKvyzopyxyPHVaHtBpn4Ou2sraIf2HHXWt3teBmjZke8ZeYeJKF2WDe0oeqpvHO56NxHe6sH1W1bPbunJZlwFihNKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586884621; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gXNblUO4SiKtKIE29/5D+Fmm4HZBRwhfz9A4bbnSMB4=; b=RFcgJr7CBm/OpLS9E3OfNVvJSdb9BNadi8X//p3g1v15Tc+wqgY6zgCvO+8Y3roXP5sa+BfvZEY0AkUT3BP5fdGS1HlM72t/LegNYVV0PDmoybzmab8dqMjhZ0nxjniJJyTwU3uzc9uEK/SKTCC9ndVd033t6nOrvGtRAGaG58Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586884621261464.6097996552171; Tue, 14 Apr 2020 10:17:01 -0700 (PDT) Received: from localhost ([::1]:35924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOPBE-0002bb-2c for importer@patchew.org; Tue, 14 Apr 2020 13:17:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42074) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOP0e-0006lE-NN for qemu-devel@nongnu.org; Tue, 14 Apr 2020 13:06:05 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOP0d-0006JC-DP for qemu-devel@nongnu.org; Tue, 14 Apr 2020 13:06:04 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:43869) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jON5R-0003e7-7n; Tue, 14 Apr 2020 11:02:53 -0400 Received: by mail-pf1-x443.google.com with SMTP id l1so23846pff.10; Tue, 14 Apr 2020 08:02:53 -0700 (PDT) Received: from hyd1358.marvell.com ([115.113.156.2]) by smtp.googlemail.com with ESMTPSA id f9sm12175240pjt.45.2020.04.14.08.02.49 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Tue, 14 Apr 2020 08:02:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gXNblUO4SiKtKIE29/5D+Fmm4HZBRwhfz9A4bbnSMB4=; b=ihnlJiCaqcTHchqB2ttsaySfBAA08IHsJ0NEpXxDg2fgeFuRtyoZxzguGPjIxTD9gK 5unU4FoyTUTNcHcN63ZNFOI0444P4nig/vEjcy+4XHd1Z+/xfkyRGpxzoSCQCjPYYZuW fPlW7Mh5ThMIYYVgKmiBHgyloK1q6duvPRraVQNzgkfoJ24WCrL6kuwq6/OncYxgTqPC TkUokb43PsZD70pP9QpU/aMm26qsfnkPWO8YT2cqyiWoqfSCieptDBfBRorD0F9W1OgX zbJeKHbcFxoBXuOpxPE8AbeN1PTaqfja0rp0PCzhI0aam8PNGC0PwGAIY4Goho/DJiSK YVUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gXNblUO4SiKtKIE29/5D+Fmm4HZBRwhfz9A4bbnSMB4=; b=k6dy4LOIrV22s6Uqa9tYufnS2zHAAs4AYt8Vx2HKz/VYDR06K/0AQdxpnY6Oss6w70 QOBZiIeEKK6+9McuY35C+LKk3Uj3DEv31h5/a29kM6nzCLxpquKMmeEvD4xaYfziQZ5/ SmIlG+s9wCyTtorRVxhPag9bOQBjQTcWYG212vhOR+S4UBOYlYO1mHc0KRRv+80ZmGCf 7mtMa5TybNbFOqF8wcPdo+h7vmHYBWkF5EGY0DK/4E8e8HJ8VntFeBiSqQLGFm0uOzTQ u7sHyCfRX1d1cLz/zXYU3Et1ksMe9vM3xMetDX5FJk0qdN1mOknHfRl2zS2reEePZx5I 47OQ== X-Gm-Message-State: AGi0PuZbtaNxBEpjTRLikFrM4p984OS6Cj+2wX90NuK2Xh7LEjQzMg/N xnefXVd6Bti0/Amhdj+ghSqChJ7o1/I= X-Google-Smtp-Source: APiQypJ66Dn6kgPMqFzuOKCnNT9aHp0VZP5mPHQNojdGWTVbh17eYfsOTw9HoxVDqhVJ8K9M1D7EFQ== X-Received: by 2002:a65:6805:: with SMTP id l5mr21834666pgt.256.1586876572332; Tue, 14 Apr 2020 08:02:52 -0700 (PDT) From: sundeep.lkml@gmail.com To: jasowang@redhat.com, peter.maydell@linaro.org, philmd@redhat.com, qemu-devel@nongnu.org, qemu-arm@nongnu.org Subject: [Qemu devel PATCH v5 3/3] tests/boot_linux_console: Add ethernet test to SmartFusion2 Date: Tue, 14 Apr 2020 20:32:31 +0530 Message-Id: <1586876551-3695-4-git-send-email-sundeep.lkml@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1586876551-3695-1-git-send-email-sundeep.lkml@gmail.com> References: <1586876551-3695-1-git-send-email-sundeep.lkml@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Subbaraya Sundeep Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) From: Subbaraya Sundeep In addition to simple serial test this patch uses ping to test the ethernet block modelled in SmartFusion2 SoC. Signed-off-by: Subbaraya Sundeep Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 --- tests/acceptance/boot_linux_console.py | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py index f825cd9..c6b06a1 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -336,13 +336,13 @@ class BootLinuxConsole(Test): """ uboot_url =3D ('https://raw.githubusercontent.com/' 'Subbaraya-Sundeep/qemu-test-binaries/' - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/u-boot') - uboot_hash =3D 'abba5d9c24cdd2d49cdc2a8aa92976cf20737eff' + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/u-boot') + uboot_hash =3D 'cbb8cbab970f594bf6523b9855be209c08374ae2' uboot_path =3D self.fetch_asset(uboot_url, asset_hash=3Duboot_hash) spi_url =3D ('https://raw.githubusercontent.com/' 'Subbaraya-Sundeep/qemu-test-binaries/' - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/spi.bin') - spi_hash =3D '85f698329d38de63aea6e884a86fbde70890a78a' + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/spi.bin') + spi_hash =3D '65523a1835949b6f4553be96dec1b6a38fb05501' spi_path =3D self.fetch_asset(spi_url, asset_hash=3Dspi_hash) =20 self.vm.set_console() @@ -352,7 +352,12 @@ class BootLinuxConsole(Test): '-drive', 'file=3D' + spi_path + ',if=3Dmtd,forma= t=3Draw', '-no-reboot') self.vm.launch() - self.wait_for_console_pattern('init started: BusyBox') + self.wait_for_console_pattern('Enter \'help\' for a list') + + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 10.0.2.15', + 'eth0: link becomes ready= ') + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2', + '3 packets transmitted, 3 packets received, 0% packet loss') =20 def do_test_arm_raspi2(self, uart_id): """ --=20 2.7.4