From nobody Thu May 16 05:55:09 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1586761079; cv=none; d=zohomail.com; s=zohoarc; b=VM30w0jTJt4Sm1QaiRYelLOsE1PE/utHDo+DQhA/0XnX7mHwu6ON0vwQpe7jNVAf7XNY75V5xLM7KzlRKw5OG5mw1saR0r+cZzS64vVK07tuUtI1v8t7GxghUGWZ0NQHKxTJgaqhxUKp2a3Q2V3EOjUPGTHhfsbvCISrtQQkFCU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586761079; h=Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:Sender:Subject:To; bh=SXUtHSH33HUcOqixVkJtaVsrAc5UPY0/GyXRLvqchWg=; b=HRFLxILTOB7okawTQ0Zfq41d/RNUcjD7BjllgCW+OGLne9+4HeltysWrIeqxodO7F1b1GTD3rwkYqdTvTo4qS+nIM6O90wPDCA06lHNYhTTTeSGKHllBmQ7VZJkacFmu6GDmDiUEpxvFoC1KADRIPaK6SQJaPBZ9/UbYuSP+d74= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586761079805858.9493961820912; Sun, 12 Apr 2020 23:57:59 -0700 (PDT) Received: from localhost ([::1]:40994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jNt2b-0003tn-Uh for importer@patchew.org; Mon, 13 Apr 2020 02:57:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35074) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jNt21-0003VA-BL for qemu-devel@nongnu.org; Mon, 13 Apr 2020 02:57:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jNt1z-0005BW-Jm for qemu-devel@nongnu.org; Mon, 13 Apr 2020 02:57:20 -0400 Received: from mga06.intel.com ([134.134.136.31]:34271) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jNt1z-00059n-6n for qemu-devel@nongnu.org; Mon, 13 Apr 2020 02:57:19 -0400 Received: from orsmga002.jf.intel.com ([10.7.209.21]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 12 Apr 2020 23:57:10 -0700 Received: from unknown (HELO localhost.localdomain.bj.intel.com) ([10.238.156.101]) by orsmga002.jf.intel.com with ESMTP; 12 Apr 2020 23:57:08 -0700 IronPort-SDR: BGsi1Nj3q1KGbO1pPurngzL2+wNBBT265X6F1lApbhgPd8Z/VMXj5ADMRrhAOSwstw7AkPskGv SP8+dJo9bzZg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: Lr7knNyBEDv3IuwB+Yr7uZp02UD3fJvELuabZgNEkn5IhQP5+CF7DKV51f8IU5sM0GeDGBwcRT 7yai+tzj0cwg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,377,1580803200"; d="scan'208";a="270992545" From: Cathy Zhang To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Subject: [PATCH] x86/cpu: Enable AVX512_VP2INTERSECT cpu feature Date: Mon, 13 Apr 2020 14:52:38 +0800 Message-Id: <1586760758-13638-1-git-send-email-cathy.zhang@intel.com> X-Mailer: git-send-email 1.8.3.1 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 134.134.136.31 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org, cathy.zhang@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" AVX512_VP2INTERSECT compute vector pair intersection to a pair of mask registers, which is introduced with intel Tiger Lake, defining as CPUID.(EAX=3D7,ECX=3D0):EDX[bit 08]. Refer to the following release spec: https://software.intel.com/sites/default/files/managed/c5/15/\ architecture-instruction-set-extensions-programming-reference.pdf Signed-off-by: Cathy Zhang --- target/i386/cpu.c | 2 +- target/i386/cpu.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 92fafa2..c8c95c3 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1078,7 +1078,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORD= S] =3D { .feat_names =3D { NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", NULL, NULL, NULL, NULL, - NULL, NULL, "md-clear", NULL, + "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL /* pconfig */, NULL, NULL, NULL, NULL, NULL, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 576f309..5c34795 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -770,6 +770,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) +/* AVX512 Vector Pair Intersection to a Pair of Mask Registers */ +#define CPUID_7_0_EDX_AVX512_VP2INTERSECT (1U << 8) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ --=20 1.8.3.1