From nobody Mon Feb 9 09:52:38 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1585542078; cv=none; d=zohomail.com; s=zohoarc; b=c528NAOfnkxsiDvN06mEyk9C1l912VC26uE6sT0dNZVqidKvVikrzP7EEMvzy7pF04KhiNE/pgRX9CgQ63MZbl5MWkRMtXqGoKROtla5LWgjgAwzk3vsFCrUHEGAvc4AS4D23IrwN0SyJUbdKD82Xlts/Kmn9uHZebgHQNPnxPU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1585542078; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=ah3x8BZp5ZhMfJfMM2KFoZLM7KNnvWCKsTLutxdPK50=; b=D7jmoZK69/QGKpCwkwd2VKIM570Tq9mc67RBmM937ttYTN9WQ8y9zcynbgk0B7Vdk5e0iE0c2Ns4GwTHEGgMlU+CAquFbzhW62aGc/tTw6MnHXD34Krb8GbvgIQ1Kom94j3JOlWOMrYujyaC+wtnafXUkEpnb5K+VuuEZvy4dJk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1585542078214809.2632274347603; Sun, 29 Mar 2020 21:21:18 -0700 (PDT) Received: from localhost ([::1]:44636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jIlvI-00048H-T2 for importer@patchew.org; Mon, 30 Mar 2020 00:21:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:37824) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jIltT-0000qo-8b for qemu-devel@nongnu.org; Mon, 30 Mar 2020 00:19:24 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jIltR-0007qk-GU for qemu-devel@nongnu.org; Mon, 30 Mar 2020 00:19:23 -0400 Received: from mga07.intel.com ([134.134.136.100]:12573) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jIltR-0007o2-6w for qemu-devel@nongnu.org; Mon, 30 Mar 2020 00:19:21 -0400 Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 Mar 2020 21:19:15 -0700 Received: from jacob-builder.jf.intel.com ([10.7.199.155]) by orsmga001.jf.intel.com with ESMTP; 29 Mar 2020 21:19:15 -0700 IronPort-SDR: Oz/XLgqOaoi9LjQ8q5NCUrl7awbYlBaX/VNj803K6NQPX+mZRYBs18F71caBn2qU6BcT94hnXw nL5Ne8MS8Vxg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: OybUe+OIIaTxJ5/AJtn153r7J+TcgAogiJdZ/VmBy0gdRVWIMoukEGfzJFDloOTy8XixGh0oiC AmlbtIUve/Sg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,322,1580803200"; d="scan'208";a="327632029" From: Liu Yi L To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Subject: [PATCH v2 07/22] intel_iommu: add set/unset_iommu_context callback Date: Sun, 29 Mar 2020 21:24:46 -0700 Message-Id: <1585542301-84087-8-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1585542301-84087-1-git-send-email-yi.l.liu@intel.com> References: <1585542301-84087-1-git-send-email-yi.l.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 134.134.136.100 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe@linaro.org, kevin.tian@intel.com, yi.l.liu@intel.com, Yi Sun , Eduardo Habkost , kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, Jacob Pan , pbonzini@redhat.com, hao.wu@intel.com, Richard Henderson , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch adds set/unset_iommu_context() impelementation in Intel vIOMMU. For Intel platform, pass-through modules (e.g. VFIO) could set HostIOMMUContext to Intel vIOMMU emulator. Cc: Kevin Tian Cc: Jacob Pan Cc: Peter Xu Cc: Yi Sun Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Signed-off-by: Liu Yi L --- hw/i386/intel_iommu.c | 71 +++++++++++++++++++++++++++++++++++++++= +--- include/hw/i386/intel_iommu.h | 21 ++++++++++--- 2 files changed, 83 insertions(+), 9 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 4b22910..fd349c6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3354,23 +3354,33 @@ static const MemoryRegionOps vtd_mem_ir_ops =3D { }, }; =20 -VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n) +/** + * Fetch a VTDBus instance for given PCIBus. If no existing instance, + * allocate one. + */ +static VTDBus *vtd_find_add_bus(IntelIOMMUState *s, PCIBus *bus) { uintptr_t key =3D (uintptr_t)bus; VTDBus *vtd_bus =3D g_hash_table_lookup(s->vtd_as_by_busptr, &key); - VTDAddressSpace *vtd_dev_as; - char name[128]; =20 if (!vtd_bus) { uintptr_t *new_key =3D g_malloc(sizeof(*new_key)); *new_key =3D (uintptr_t)bus; /* No corresponding free() */ - vtd_bus =3D g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) *= \ - PCI_DEVFN_MAX); + vtd_bus =3D g_malloc0(sizeof(VTDBus)); vtd_bus->bus =3D bus; g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); } + return vtd_bus; +} =20 +VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n) +{ + VTDBus *vtd_bus; + VTDAddressSpace *vtd_dev_as; + char name[128]; + + vtd_bus =3D vtd_find_add_bus(s, bus); vtd_dev_as =3D vtd_bus->dev_as[devfn]; =20 if (!vtd_dev_as) { @@ -3436,6 +3446,55 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, int devfn) return vtd_dev_as; } =20 +static int vtd_dev_set_iommu_context(PCIBus *bus, void *opaque, + int devfn, + HostIOMMUContext *iommu_ctx) +{ + IntelIOMMUState *s =3D opaque; + VTDBus *vtd_bus; + VTDHostIOMMUContext *vtd_dev_icx; + + assert(0 <=3D devfn && devfn < PCI_DEVFN_MAX); + + vtd_bus =3D vtd_find_add_bus(s, bus); + + vtd_iommu_lock(s); + + vtd_dev_icx =3D vtd_bus->dev_icx[devfn]; + + assert(!vtd_dev_icx); + + vtd_bus->dev_icx[devfn] =3D vtd_dev_icx =3D + g_malloc0(sizeof(VTDHostIOMMUContext)); + vtd_dev_icx->vtd_bus =3D vtd_bus; + vtd_dev_icx->devfn =3D (uint8_t)devfn; + vtd_dev_icx->iommu_state =3D s; + vtd_dev_icx->iommu_ctx =3D iommu_ctx; + + vtd_iommu_unlock(s); + + return 0; +} + +static void vtd_dev_unset_iommu_context(PCIBus *bus, void *opaque, int dev= fn) +{ + IntelIOMMUState *s =3D opaque; + VTDBus *vtd_bus; + VTDHostIOMMUContext *vtd_dev_icx; + + assert(0 <=3D devfn && devfn < PCI_DEVFN_MAX); + + vtd_bus =3D vtd_find_add_bus(s, bus); + + vtd_iommu_lock(s); + + vtd_dev_icx =3D vtd_bus->dev_icx[devfn]; + g_free(vtd_dev_icx); + vtd_bus->dev_icx[devfn] =3D NULL; + + vtd_iommu_unlock(s); +} + static uint64_t get_naturally_aligned_size(uint64_t start, uint64_t size, int gaw) { @@ -3731,6 +3790,8 @@ static AddressSpace *vtd_host_dma_iommu(PCIBus *bus, = void *opaque, int devfn) =20 static PCIIOMMUOps vtd_iommu_ops =3D { .get_address_space =3D vtd_host_dma_iommu, + .set_iommu_context =3D vtd_dev_set_iommu_context, + .unset_iommu_context =3D vtd_dev_unset_iommu_context, }; =20 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 3870052..b5fefb9 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -64,6 +64,7 @@ typedef union VTD_IR_TableEntry VTD_IR_TableEntry; typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; typedef struct VTDPASIDEntry VTDPASIDEntry; +typedef struct VTDHostIOMMUContext VTDHostIOMMUContext; =20 /* Context-Entry */ struct VTDContextEntry { @@ -112,10 +113,20 @@ struct VTDAddressSpace { IOVATree *iova_tree; /* Traces mapped IOVA ranges */ }; =20 +struct VTDHostIOMMUContext { + VTDBus *vtd_bus; + uint8_t devfn; + HostIOMMUContext *iommu_ctx; + IntelIOMMUState *iommu_state; +}; + struct VTDBus { - PCIBus* bus; /* A reference to the bus to provide translation for */ + /* A reference to the bus to provide translation for */ + PCIBus *bus; /* A table of VTDAddressSpace objects indexed by devfn */ - VTDAddressSpace *dev_as[]; + VTDAddressSpace *dev_as[PCI_DEVFN_MAX]; + /* A table of VTDHostIOMMUContext objects indexed by devfn */ + VTDHostIOMMUContext *dev_icx[PCI_DEVFN_MAX]; }; =20 struct VTDIOTLBEntry { @@ -269,8 +280,10 @@ struct IntelIOMMUState { bool dma_drain; /* Whether DMA r/w draining enabled */ =20 /* - * Protects IOMMU states in general. Currently it protects the - * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. + * iommu_lock protects below: + * - per-IOMMU IOTLB caches + * - context entry cache in VTDAddressSpace + * - HostIOMMUContext pointer cached in vIOMMU */ QemuMutex iommu_lock; }; --=20 2.7.4