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Tue, 24 Mar 2020 21:43:01 +0000 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Tue, 24 Mar 2020 14:43:08 -0700 From: Kirti Wankhede To: , Subject: [PATCH v16 QEMU 04/16] vfio: Add save and load functions for VFIO PCI devices Date: Wed, 25 Mar 2020 02:39:02 +0530 Message-ID: <1585084154-29461-5-git-send-email-kwankhede@nvidia.com> X-Mailer: git-send-email 2.7.0 In-Reply-To: <1585084154-29461-1-git-send-email-kwankhede@nvidia.com> References: <1585084154-29461-1-git-send-email-kwankhede@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1585086098; bh=8GNHHJN6bYqzJEgHS83v8xtDI+MVHcgFYs0/xRA0l8o=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=EQaPvxk5//5lnY9Sn1I4xuNfwPUUd+nWL4Gh8oLe1uN8tY2n3joHIBYb/ZPXSRNvr xIjUTeFBiz6D+g/MCtqs4dNpGwlOq0NOW0e3at1ZkMgJgBYKfEYO6UZMuyqfQWtHet HFNPz1tEa8y/AiQnWZMmnF3bReoKh/8eMX3N3nzn7gjKyOrxmhnkzD0HzuYoIDuxol eG6ovb6Yb1l3C/1uOcnBPsxmXV+9TI08D9igGXedd0MBPtbUeXDtvMf6auSWd+Zd8A BL86jY983yb9XwV5tli51eSZEXQrMGJqUeLIrkOfUXSTdQtIQSv5xggSuYMqhb1pIh 0Io7cyJEhV+Vw== X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 216.228.121.143 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Zhengxiao.zx@Alibaba-inc.com, kevin.tian@intel.com, yi.l.liu@intel.com, yan.y.zhao@intel.com, eskultet@redhat.com, ziye.yang@intel.com, qemu-devel@nongnu.org, cohuck@redhat.com, shuangtai.tst@alibaba-inc.com, dgilbert@redhat.com, zhi.a.wang@intel.com, mlevitsk@redhat.com, pasic@linux.ibm.com, aik@ozlabs.ru, Kirti Wankhede , eauger@redhat.com, felipe@nutanix.com, jonathan.davies@nutanix.com, changpeng.liu@intel.com, Ken.Xue@amd.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" These functions save and restore PCI device specific data - config space of PCI device. Tested save and restore with MSI and MSIX type. Signed-off-by: Kirti Wankhede Reviewed-by: Neo Jia --- hw/vfio/pci.c | 163 ++++++++++++++++++++++++++++++++++++++= ++++ include/hw/vfio/vfio-common.h | 2 + 2 files changed, 165 insertions(+) diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 6c77c12e44b9..8deb11e87ef7 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -41,6 +41,7 @@ #include "trace.h" #include "qapi/error.h" #include "migration/blocker.h" +#include "migration/qemu-file.h" =20 #define TYPE_VFIO_PCI "vfio-pci" #define PCI_VFIO(obj) OBJECT_CHECK(VFIOPCIDevice, obj, TYPE_VFIO_PCI) @@ -1632,6 +1633,50 @@ static void vfio_bars_prepare(VFIOPCIDevice *vdev) } } =20 +static int vfio_bar_validate(VFIOPCIDevice *vdev, int nr) +{ + PCIDevice *pdev =3D &vdev->pdev; + VFIOBAR *bar =3D &vdev->bars[nr]; + uint64_t addr; + uint32_t addr_lo, addr_hi =3D 0; + + /* Skip unimplemented BARs and the upper half of 64bit BARS. */ + if (!bar->size) { + return 0; + } + + addr_lo =3D pci_default_read_config(pdev, PCI_BASE_ADDRESS_0 + nr * 4,= 4); + + addr_lo =3D addr_lo & (bar->ioport ? PCI_BASE_ADDRESS_IO_MASK : + PCI_BASE_ADDRESS_MEM_MASK); + if (bar->type =3D=3D PCI_BASE_ADDRESS_MEM_TYPE_64) { + addr_hi =3D pci_default_read_config(pdev, + PCI_BASE_ADDRESS_0 + (nr + 1) * 4= , 4); + } + + addr =3D ((uint64_t)addr_hi << 32) | addr_lo; + + if (!QEMU_IS_ALIGNED(addr, bar->size)) { + return -EINVAL; + } + + return 0; +} + +static int vfio_bars_validate(VFIOPCIDevice *vdev) +{ + int i, ret; + + for (i =3D 0; i < PCI_ROM_SLOT; i++) { + ret =3D vfio_bar_validate(vdev, i); + if (ret) { + error_report("vfio: BAR address %d validation failed", i); + return ret; + } + } + return 0; +} + static void vfio_bar_register(VFIOPCIDevice *vdev, int nr) { VFIOBAR *bar =3D &vdev->bars[nr]; @@ -2414,11 +2459,129 @@ static Object *vfio_pci_get_object(VFIODevice *vba= sedev) return OBJECT(vdev); } =20 +static void vfio_pci_save_config(VFIODevice *vbasedev, QEMUFile *f) +{ + VFIOPCIDevice *vdev =3D container_of(vbasedev, VFIOPCIDevice, vbasedev= ); + PCIDevice *pdev =3D &vdev->pdev; + uint16_t pci_cmd; + int i; + + for (i =3D 0; i < PCI_ROM_SLOT; i++) { + uint32_t bar; + + bar =3D pci_default_read_config(pdev, PCI_BASE_ADDRESS_0 + i * 4, = 4); + qemu_put_be32(f, bar); + } + + qemu_put_be32(f, vdev->interrupt); + if (vdev->interrupt =3D=3D VFIO_INT_MSI) { + uint32_t msi_flags, msi_addr_lo, msi_addr_hi =3D 0, msi_data; + bool msi_64bit; + + msi_flags =3D pci_default_read_config(pdev, pdev->msi_cap + PCI_MS= I_FLAGS, + 2); + msi_64bit =3D (msi_flags & PCI_MSI_FLAGS_64BIT); + + msi_addr_lo =3D pci_default_read_config(pdev, + pdev->msi_cap + PCI_MSI_ADDRESS_L= O, 4); + qemu_put_be32(f, msi_addr_lo); + + if (msi_64bit) { + msi_addr_hi =3D pci_default_read_config(pdev, + pdev->msi_cap + PCI_MSI_ADDRE= SS_HI, + 4); + } + qemu_put_be32(f, msi_addr_hi); + + msi_data =3D pci_default_read_config(pdev, + pdev->msi_cap + (msi_64bit ? PCI_MSI_DATA_64 : PCI_MSI_DAT= A_32), + 2); + qemu_put_be32(f, msi_data); + } else if (vdev->interrupt =3D=3D VFIO_INT_MSIX) { + uint16_t offset; + + /* save enable bit and maskall bit */ + offset =3D pci_default_read_config(pdev, + pdev->msix_cap + PCI_MSIX_FLAGS + 1= , 2); + qemu_put_be16(f, offset); + msix_save(pdev, f); + } + pci_cmd =3D pci_default_read_config(pdev, PCI_COMMAND, 2); + qemu_put_be16(f, pci_cmd); +} + +static int vfio_pci_load_config(VFIODevice *vbasedev, QEMUFile *f) +{ + VFIOPCIDevice *vdev =3D container_of(vbasedev, VFIOPCIDevice, vbasedev= ); + PCIDevice *pdev =3D &vdev->pdev; + uint32_t interrupt_type; + uint32_t msi_flags, msi_addr_lo, msi_addr_hi =3D 0, msi_data; + uint16_t pci_cmd; + bool msi_64bit; + int i, ret; + + /* retore pci bar configuration */ + pci_cmd =3D pci_default_read_config(pdev, PCI_COMMAND, 2); + vfio_pci_write_config(pdev, PCI_COMMAND, + pci_cmd & (!(PCI_COMMAND_IO | PCI_COMMAND_MEMORY))= , 2); + for (i =3D 0; i < PCI_ROM_SLOT; i++) { + uint32_t bar =3D qemu_get_be32(f); + + vfio_pci_write_config(pdev, PCI_BASE_ADDRESS_0 + i * 4, bar, 4); + } + + ret =3D vfio_bars_validate(vdev); + if (ret) { + return ret; + } + + interrupt_type =3D qemu_get_be32(f); + + if (interrupt_type =3D=3D VFIO_INT_MSI) { + /* restore msi configuration */ + msi_flags =3D pci_default_read_config(pdev, + pdev->msi_cap + PCI_MSI_FLAGS,= 2); + msi_64bit =3D (msi_flags & PCI_MSI_FLAGS_64BIT); + + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_FLAGS, + msi_flags & (!PCI_MSI_FLAGS_ENABLE), 2); + + msi_addr_lo =3D qemu_get_be32(f); + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_LO, + msi_addr_lo, 4); + + msi_addr_hi =3D qemu_get_be32(f); + if (msi_64bit) { + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_ADDRESS_HI, + msi_addr_hi, 4); + } + msi_data =3D qemu_get_be32(f); + vfio_pci_write_config(pdev, + pdev->msi_cap + (msi_64bit ? PCI_MSI_DATA_64 : PCI_MSI_DAT= A_32), + msi_data, 2); + + vfio_pci_write_config(pdev, pdev->msi_cap + PCI_MSI_FLAGS, + msi_flags | PCI_MSI_FLAGS_ENABLE, 2); + } else if (interrupt_type =3D=3D VFIO_INT_MSIX) { + uint16_t offset =3D qemu_get_be16(f); + + /* load enable bit and maskall bit */ + vfio_pci_write_config(pdev, pdev->msix_cap + PCI_MSIX_FLAGS + 1, + offset, 2); + msix_load(pdev, f); + } + pci_cmd =3D qemu_get_be16(f); + vfio_pci_write_config(pdev, PCI_COMMAND, pci_cmd, 2); + return 0; +} + static VFIODeviceOps vfio_pci_ops =3D { .vfio_compute_needs_reset =3D vfio_pci_compute_needs_reset, .vfio_hot_reset_multi =3D vfio_pci_hot_reset_multi, .vfio_eoi =3D vfio_intx_eoi, .vfio_get_object =3D vfio_pci_get_object, + .vfio_save_config =3D vfio_pci_save_config, + .vfio_load_config =3D vfio_pci_load_config, }; =20 int vfio_populate_vga(VFIOPCIDevice *vdev, Error **errp) diff --git a/include/hw/vfio/vfio-common.h b/include/hw/vfio/vfio-common.h index 74261feaeac9..d69a7f3ae31e 100644 --- a/include/hw/vfio/vfio-common.h +++ b/include/hw/vfio/vfio-common.h @@ -120,6 +120,8 @@ struct VFIODeviceOps { int (*vfio_hot_reset_multi)(VFIODevice *vdev); void (*vfio_eoi)(VFIODevice *vdev); Object *(*vfio_get_object)(VFIODevice *vdev); + void (*vfio_save_config)(VFIODevice *vdev, QEMUFile *f); + int (*vfio_load_config)(VFIODevice *vdev, QEMUFile *f); }; =20 typedef struct VFIOGroup { --=20 2.7.0