From nobody Mon Feb 9 17:23:35 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1583461444; cv=none; d=zohomail.com; s=zohoarc; b=FhRsd1ErCymR5l2gVYRpynZweKQgyuQdPNElV8uEpwVsAabElPhsjIUBJ6uKMoXnREKzYGUqL5I1IUwbXtddg0xT+Of24Z2jwx+zRknLkSHz7UY4WXWbK6uTHeEokRsNNW3euxTuq5kI42cPed9u1baZq72KlyN9Of2kSBicJs8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583461444; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=EABIzFamTeGOxnAfGW+W+OnuLZ1SpOD/r/PPGmCBHjY=; b=C9nTHvMDutKW0rkeY+NjSt2tV8j+0ECiIRG0/Mg7+68qQhJHrFCQRtDmFzaNi2QXw4KvuQWsadpbl1B4tQLOjtx5Se03QoIy+6RU1eA1uwnDrkmWM6bgDhKMh+M5BNzterYXaQKOQK23mDxoqN752d1eKdLj9Eco44ij6FoWCYE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1583461444819577.8809118534062; Thu, 5 Mar 2020 18:24:04 -0800 (PST) Received: from localhost ([::1]:58722 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jA2eh-0000fj-G2 for importer@patchew.org; Thu, 05 Mar 2020 21:24:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57862) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jA2cc-0005RE-59 for qemu-devel@nongnu.org; Thu, 05 Mar 2020 21:21:58 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jA2ca-0003dm-TV for qemu-devel@nongnu.org; Thu, 05 Mar 2020 21:21:54 -0500 Received: from mga05.intel.com ([192.55.52.43]:61181) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jA2ca-0003ak-Ju for qemu-devel@nongnu.org; Thu, 05 Mar 2020 21:21:52 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2020 18:21:51 -0800 Received: from snr.bj.intel.com ([10.240.193.90]) by orsmga005.jf.intel.com with ESMTP; 05 Mar 2020 18:21:48 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,520,1574150400"; d="scan'208";a="413742217" From: Luwei Kang To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH v1 3/3] i386: Add support for save/load IA32_PEBS_DATA_CFG MSR Date: Fri, 6 Mar 2020 18:20:05 +0800 Message-Id: <1583490005-27761-4-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1583490005-27761-1-git-send-email-luwei.kang@intel.com> References: <1583490005-27761-1-git-send-email-luwei.kang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luwei Kang , qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add support for save/load PEBS baseline feature IA32_PEBS_DATA_CFG MSR. Signed-off-by: Luwei Kang --- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 14 ++++++++++++++ target/i386/machine.c | 24 ++++++++++++++++++++++++ 3 files changed, 40 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 872a495..a9a7b3f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -413,6 +413,7 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 #define MSR_IA32_PEBS_ENABLE 0x3f1 +#define MSR_IA32_PEBS_DATA_CFG 0x3f2 #define MSR_IA32_DS_AREA 0x600 =20 #define MSR_MC0_CTL 0x400 @@ -1449,6 +1450,7 @@ typedef struct CPUX86State { =20 uint64_t msr_pebs_enable; uint64_t msr_ds_area; + uint64_t msr_pebs_data_cfg; =20 uint64_t pat; uint32_t smbase; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 1043961..ab4e7bb 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -104,6 +104,7 @@ static bool has_msr_core_capabs; static bool has_msr_vmx_vmfunc; static bool has_msr_pebs_enable; static bool has_msr_ds_area; +static bool has_msr_pebs_data_cfg; =20 static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -2056,6 +2057,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_DS_AREA: has_msr_ds_area =3D true; break; + case MSR_IA32_PEBS_DATA_CFG: + has_msr_pebs_data_cfg =3D true; + break; } } } @@ -2786,6 +2790,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, env->msr_ds_area); } + if (has_msr_pebs_data_cfg) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_DATA_CFG, + env->msr_pebs_data_cfg); + } } =20 /* @@ -3177,6 +3185,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_ds_area) { kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0); } + if (has_msr_pebs_data_cfg) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_DATA_CFG, 0); + } } =20 if (env->mcg_cap) { @@ -3431,6 +3442,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_IA32_DS_AREA: env->msr_ds_area =3D msrs[i].data; break; + case MSR_IA32_PEBS_DATA_CFG: + env->msr_pebs_data_cfg =3D msrs[i].data; + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 82a2101..58b786d 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -670,6 +670,29 @@ static const VMStateDescription vmstate_msr_pebs_via_d= s =3D { } }; =20 +static bool pebs_baseline_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + if (env->msr_pebs_data_cfg) { + return true; + } + + return false; +} + +static const VMStateDescription vmstate_msr_pebs_baseline =3D { + .name =3D "cpu/msr_pebs_baseline", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pebs_baseline_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_pebs_data_cfg, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + static bool mpx_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -1424,6 +1447,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_ia32_feature_control, &vmstate_msr_architectural_pmu, &vmstate_msr_pebs_via_ds, + &vmstate_msr_pebs_baseline, &vmstate_mpx, &vmstate_msr_hypercall_hypercall, &vmstate_msr_hyperv_vapic, --=20 1.8.3.1