From nobody Mon Feb 9 06:01:50 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1583461371; cv=none; d=zohomail.com; s=zohoarc; b=Wwni00dyFTemww/tQuTRwMc+mouExlRFs8DRtKYhv6bWsjfnzbJkaqS5DfrZgiYrnoBPpwphPNBAevqO7RTwUb22N+4Gy7f61WOFyfOdLmf2TNNauO0DrOySbOWaZcO1W5QlfmcrZj1LMWFk39RVEuS7AZhXcqxGVQN8YUikTF0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1583461371; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=nhkDkYEeG4oEx0WE66XOXgaozYtq/SKSQc9FbbJHRkA=; b=BlV0ebOY359eCKdhkXOvwTfjvwppvODl4hwMdSUH/WZ314tl+Qto2GUaXG6eqC3Qi7H3AR2+x7cTAk+beIGziOrz/YPDq650beGN50hOiNP9huSKaYzfh7ZNWTtyvjEcTiAHd9F62j93VnmjYInielivyGiqrFLGlpheXzJ0aMs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1583461371915836.0943582001826; Thu, 5 Mar 2020 18:22:51 -0800 (PST) Received: from localhost ([::1]:58708 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jA2dW-0006vB-VG for importer@patchew.org; Thu, 05 Mar 2020 21:22:50 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57684) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jA2cW-0005KY-LJ for qemu-devel@nongnu.org; Thu, 05 Mar 2020 21:21:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jA2cV-0003Qj-0j for qemu-devel@nongnu.org; Thu, 05 Mar 2020 21:21:48 -0500 Received: from mga12.intel.com ([192.55.52.136]:23298) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jA2cU-0003OY-NI for qemu-devel@nongnu.org; Thu, 05 Mar 2020 21:21:46 -0500 Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 05 Mar 2020 18:21:44 -0800 Received: from snr.bj.intel.com ([10.240.193.90]) by orsmga005.jf.intel.com with ESMTP; 05 Mar 2020 18:21:42 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,520,1574150400"; d="scan'208";a="413742198" From: Luwei Kang To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com, mst@redhat.com, marcel.apfelbaum@gmail.com Subject: [PATCH v1 2/3] i386: Add support for save/load PEBS MSRs Date: Fri, 6 Mar 2020 18:20:04 +0800 Message-Id: <1583490005-27761-3-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1583490005-27761-1-git-send-email-luwei.kang@intel.com> References: <1583490005-27761-1-git-send-email-luwei.kang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.136 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luwei Kang , qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" PEBS feature virtualization required IA32_PEBS_ENABLE and DS_AREA MSRs. This patch is to add the support of these MSRs saved/loaded in guest. Signed-off-by: Luwei Kang --- target/i386/cpu.h | 6 ++++++ target/i386/kvm.c | 29 +++++++++++++++++++++++++++++ target/i386/machine.c | 25 +++++++++++++++++++++++++ 3 files changed, 60 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 398810f..872a495 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -412,6 +412,9 @@ typedef enum X86Seg { #define MSR_CORE_PERF_GLOBAL_CTRL 0x38f #define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390 =20 +#define MSR_IA32_PEBS_ENABLE 0x3f1 +#define MSR_IA32_DS_AREA 0x600 + #define MSR_MC0_CTL 0x400 #define MSR_MC0_STATUS 0x401 #define MSR_MC0_ADDR 0x402 @@ -1444,6 +1447,9 @@ typedef struct CPUX86State { uint64_t msr_gp_counters[MAX_GP_COUNTERS]; uint64_t msr_gp_evtsel[MAX_GP_COUNTERS]; =20 + uint64_t msr_pebs_enable; + uint64_t msr_ds_area; + uint64_t pat; uint32_t smbase; uint64_t msr_smi_count; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index bfd09bd..1043961 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -102,6 +102,8 @@ static bool has_msr_smi_count; static bool has_msr_arch_capabs; static bool has_msr_core_capabs; static bool has_msr_vmx_vmfunc; +static bool has_msr_pebs_enable; +static bool has_msr_ds_area; =20 static uint32_t has_architectural_pmu_version; static uint32_t num_architectural_pmu_gp_counters; @@ -2048,6 +2050,12 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_IA32_VMX_VMFUNC: has_msr_vmx_vmfunc =3D true; break; + case MSR_IA32_PEBS_ENABLE: + has_msr_pebs_enable =3D true; + break; + case MSR_IA32_DS_AREA: + has_msr_ds_area =3D true; + break; } } } @@ -2770,7 +2778,16 @@ static int kvm_put_msrs(X86CPU *cpu, int level) kvm_msr_entry_add(cpu, MSR_CORE_PERF_GLOBAL_CTRL, env->msr_global_ctrl); } + if (has_msr_pebs_enable) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, + env->msr_pebs_enable); + } + if (has_msr_ds_area) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, + env->msr_ds_area); + } } + /* * Hyper-V partition-wide MSRs: to avoid clearing them on cpu hot-= add, * only sync them to KVM on the first cpu @@ -3154,6 +3171,12 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_P6_PERFCTR0 + i, 0); kvm_msr_entry_add(cpu, MSR_P6_EVNTSEL0 + i, 0); } + if (has_msr_pebs_enable) { + kvm_msr_entry_add(cpu, MSR_IA32_PEBS_ENABLE, 0); + } + if (has_msr_ds_area) { + kvm_msr_entry_add(cpu, MSR_IA32_DS_AREA, 0); + } } =20 if (env->mcg_cap) { @@ -3402,6 +3425,12 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_P6_EVNTSEL0 ... MSR_P6_EVNTSEL0 + MAX_GP_COUNTERS - 1: env->msr_gp_evtsel[index - MSR_P6_EVNTSEL0] =3D msrs[i].data; break; + case MSR_IA32_PEBS_ENABLE: + env->msr_pebs_enable =3D msrs[i].data; + break; + case MSR_IA32_DS_AREA: + env->msr_ds_area =3D msrs[i].data; + break; case HV_X64_MSR_HYPERCALL: env->msr_hv_hypercall =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 6481f84..82a2101 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -646,6 +646,30 @@ static const VMStateDescription vmstate_msr_architectu= ral_pmu =3D { } }; =20 +static bool pebs_via_ds_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + if (env->msr_pebs_enable || env->msr_ds_area) { + return true; + } + + return false; +} + +static const VMStateDescription vmstate_msr_pebs_via_ds =3D { + .name =3D "cpu/msr_pebs_via_ds", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pebs_via_ds_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_pebs_enable, X86CPU), + VMSTATE_UINT64(env.msr_ds_area, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + static bool mpx_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -1399,6 +1423,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_ia32_misc_enable, &vmstate_msr_ia32_feature_control, &vmstate_msr_architectural_pmu, + &vmstate_msr_pebs_via_ds, &vmstate_mpx, &vmstate_msr_hypercall_hypercall, &vmstate_msr_hyperv_vapic, --=20 1.8.3.1