From nobody Thu Nov 13 22:06:43 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1582911103; cv=none; d=zohomail.com; s=zohoarc; b=EWLN/qSme3+GKEb3vjdza+VHnBWAir5qieUhH7xp+FW/LeIvGjldIP3o0Af7eEKOkeQ/fmyvQJgevInuzHS+uY0CBDFCoK0QZWn/KvFQ9vsdd1jFO9EAkHcNW/tNSg6POkGAKc7YY6NY5UXx6EQ5efGMgJ48rD2iQbFMZYESrX0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582911103; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=raV0a5Ai84DQTSYp+zAGTgKUh+hIWVz9RLCOHFVyX5g=; b=ZnbkLnotWtfl5CmJYhuOK2Cvo1bxoDCQl07ZJsymRAIZzDK4yioq0GuWprZTkfeplthDgx1hfUM1lt1jlarvXFIPSnd2KAnwttyH6IsP2w4uA+GARr4NeGkYzoKf2JRkAoshcGKo2qYLtynEWuyD0cutYQfp+yL9JilT7FoH1Wo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582911103796959.8915051578832; Fri, 28 Feb 2020 09:31:43 -0800 (PST) Received: from localhost ([::1]:51418 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7jUE-00035U-C7 for importer@patchew.org; Fri, 28 Feb 2020 12:31:42 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58635) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7imT-0005sQ-F0 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7imP-0007Ss-0Z for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:29 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:27035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j7imK-0005Ug-V7 for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:22 -0500 Received: from unknown (HELO ironmsg04-sd.qualcomm.com) ([10.53.140.144]) by alexa-out-sd-02.qualcomm.com with ESMTP; 28 Feb 2020 08:44:34 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg04-sd.qualcomm.com with ESMTP; 28 Feb 2020 08:44:33 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 5B50E1163; Fri, 28 Feb 2020 10:44:33 -0600 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1582908381; x=1614444381; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=raV0a5Ai84DQTSYp+zAGTgKUh+hIWVz9RLCOHFVyX5g=; b=DA/+AbMlYIF/kC0CE+370WghiEhSojyXd1xp1nqrgUiTNW19IGZyCOYN S0mUoRAfv4J/EQoz5Vs6qpXYRuiuE2rS2Qtnq1bbylT+gQyKVvooV8Ytc oO6e2wC3882ZFuz74Jr/89TL+BmCHMVrQAFcbT0JSUWCzn/KvO9HHzP2v I=; From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 58/67] Hexagon HVX import macro definitions Date: Fri, 28 Feb 2020 10:43:54 -0600 Message-Id: <1582908244-304-59-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> References: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Imported from the Hexagon architecture library imported/allext_macros.def Top level macro include for all extens= ions imported/mmvec/macros.def HVX macro definitions The macro definition files specify instruction attributes that are applied to each instruction that reverences the macro. Signed-off-by: Taylor Simpson --- target/hexagon/imported/allext_macros.def | 25 + target/hexagon/imported/mmvec/macros.def | 1110 +++++++++++++++++++++++++= ++++ 2 files changed, 1135 insertions(+) create mode 100644 target/hexagon/imported/allext_macros.def create mode 100755 target/hexagon/imported/mmvec/macros.def diff --git a/target/hexagon/imported/allext_macros.def b/target/hexagon/imp= orted/allext_macros.def new file mode 100644 index 0000000..e1f16eb --- /dev/null +++ b/target/hexagon/imported/allext_macros.def @@ -0,0 +1,25 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +/* + * Top level file for all instruction set extensions + */ +#define EXTNAME mmvec +#define EXTSTR "mmvec" +#include "mmvec/macros.def" +#undef EXTNAME +#undef EXTSTR diff --git a/target/hexagon/imported/mmvec/macros.def b/target/hexagon/impo= rted/mmvec/macros.def new file mode 100755 index 0000000..fa0beb1 --- /dev/null +++ b/target/hexagon/imported/mmvec/macros.def @@ -0,0 +1,1110 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +DEF_MACRO(fDUMPQ,(STR,REG), + "dump REG", + "dump REG", + do { + printf(STR ":" #REG ": 0x%016llx\n",REG.ud[0]); + } while (0), + () +) + +DEF_MACRO(fUSE_LOOKUP_ADDRESS_BY_REV,(PROC), + "", + "Use full VA address for lookup and exception based on REV ", + PROC->arch_proc_options->mmvec_use_full_va_for_lookup, + () +) + +DEF_MACRO(fUSE_LOOKUP_ADDRESS,(), + "", + "Use full VA address for lookup and exception", + 1, + () +) + +DEF_MACRO(fRT8NOTE, (), + "", + "", + , + (A_NOTE_RT8) +) + +DEF_MACRO(fNOTQ,(VAL), + "~VAL", + "~VAL", + /* Will break Visual Studio? */ + ({mmqreg_t _ret =3D {0}; int _i_; for (_i_ =3D 0; _i_ < fVECSIZE()/64; _i= _++) _ret.ud[_i_] =3D ~VAL.ud[_i_]; _ret;}), + () +) + +DEF_MACRO(fGETQBITS,(REG,WIDTH,MASK,BITNO), + "REG[BITNO+WIDTH-1:BITNO]", + "Get MASK bits at BITNO from REG", + ((MASK) & (REG.w[(BITNO)>>5] >> ((BITNO) & 0x1f))), + () +) + +DEF_MACRO(fGETQBIT,(REG,BITNO), + "REG[BITNO]", + "Get bit BITNO from REG", + fGETQBITS(REG,1,1,BITNO), + () +) + +DEF_MACRO(fGENMASKW,(QREG,IDX), + "maskw(QREG,IDX)", + "Generate mask from QREG for word IDX", + (((fGETQBIT(QREG,(IDX*4+0)) ? 0xFF : 0x0) << 0) + |((fGETQBIT(QREG,(IDX*4+1)) ? 0xFF : 0x0) << 8) + |((fGETQBIT(QREG,(IDX*4+2)) ? 0xFF : 0x0) << 16) + |((fGETQBIT(QREG,(IDX*4+3)) ? 0xFF : 0x0) << 24)), + () +) +DEF_MACRO(fGET10BIT,(COE,VAL,POS), + "COE=3D(((((fGETUBYTE(3,VAL) >> (2 * POS)) & 3) << 8) | fGETUBYTE(POS,VAL= )) << 6) >> 6;", + "Get 10-bit coefficient from current word value and byte position", + { + COE =3D (((((fGETUBYTE(3,VAL) >> (2 * POS)) & 3) << 8) | fGETUBYTE(POS,V= AL)) << 6); + COE >>=3D 6; + }, + () +) + +DEF_MACRO(fVMAX,(X,Y), + "max(X,Y)", + "", + (X>Y) ? X : Y, + () +) + + +DEF_MACRO(fREAD_VEC, + (DST,IDX), + "DST=3DVREG[IDX]", /* short desc */ + "Read Vector IDX", /* long desc */ + (DST =3D READ_VREG(fMODCIRCU((IDX),5))), + () +) + +DEF_MACRO(fGETNIBBLE,(IDX,SRC), + "SRC.s4[IDX]", + "Get nibble", + ( fSXTN(4,8,(SRC >> (4*IDX)) & 0xF) ), + () +) + +DEF_MACRO(fGETCRUMB,(IDX,SRC), + "SRC.s2[IDX]", + "Get 2bits", + ( fSXTN(2,8,(SRC >> (2*IDX)) & 0x3) ), + () +) + +DEF_MACRO(fGETCRUMB_SYMMETRIC,(IDX,SRC), + "SRC.s2[IDX] >=3D 0 ? (2-SRC.s2[IDX]) : SRC.s2[IDX]", + "Get 2bits", + ( (fGETCRUMB(IDX,SRC)>=3D0 ? (2-fGETCRUMB(IDX,SRC)) : fGETCRUMB(IDX,SR= C) ) ), + () +) + +#define ZERO_OFFSET_2B + + +DEF_MACRO(fWRITE_VEC, + (IDX,VAR), + "VREG[IDX]=3DVAR", /* short desc */ + "Write Vector IDX", /* long desc */ + (WRITE_VREG(fMODCIRCU((IDX),5),VAR)), + () +) + +DEF_MACRO(fGENMASKH,(QREG,IDX), + "maskh(QREG,IDX)", + "generate mask from QREG for halfword IDX", + (((fGETQBIT(QREG,(IDX*2+0)) ? 0xFF : 0x0) << 0) + |((fGETQBIT(QREG,(IDX*2+1)) ? 0xFF : 0x0) << 8)), + () +) + +DEF_MACRO(fGETMASKW,(VREG,QREG,IDX), + "VREG.w[IDX] & fGENMASKW(QREG,IDX)", + "Mask word IDX from VREG using QREG", + (VREG.w[IDX] & fGENMASKW((QREG),IDX)), + () +) + +DEF_MACRO(fGETMASKH,(VREG,QREG,IDX), + "VREG.h[IDX] & fGENMASKH(QREG,IDX)", + "Mask word IDX from VREG using QREG", + (VREG.h[IDX] & fGENMASKH((QREG),IDX)), + () +) + +DEF_MACRO(fCONDMASK8,(QREG,IDX,YESVAL,NOVAL), + "QREG.IDX ? YESVAL : NOVAL", + "QREG.IDX ? YESVAL : NOVAL", + (fGETQBIT(QREG,IDX) ? (YESVAL) : (NOVAL)), + () +) + +DEF_MACRO(fCONDMASK16,(QREG,IDX,YESVAL,NOVAL), + "select_bytes(QREG,IDX,YESVAL,NOVAL)", + "select_bytes(QREG,IDX,YESVAL,NOVAL)", + ((fGENMASKH(QREG,IDX) & (YESVAL)) | (fGENMASKH(fNOTQ(QREG),IDX) & (NOVAL)= )), + () +) + +DEF_MACRO(fCONDMASK32,(QREG,IDX,YESVAL,NOVAL), + "select_bytes(QREG,IDX,YESVAL,NOVAL)", + "select_bytes(QREG,IDX,YESVAL,NOVAL)", + ((fGENMASKW(QREG,IDX) & (YESVAL)) | (fGENMASKW(fNOTQ(QREG),IDX) & (NOVAL)= )), + () +) + + +DEF_MACRO(fSETQBITS,(REG,WIDTH,MASK,BITNO,VAL), + "REG[BITNO+WIDTH-1:BITNO] =3D VAL", + "Put bits into REG", + do { + size4u_t __TMP =3D (VAL); + REG.w[(BITNO)>>5] &=3D ~((MASK) << ((BITNO) & 0x1f)); + REG.w[(BITNO)>>5] |=3D (((__TMP) & (MASK)) << ((BITNO) & 0x1f)); + } while (0), + () +) + +DEF_MACRO(fSETQBIT,(REG,BITNO,VAL), + "REG[BITNO]=3DVAL", + "Put bit into REG", + fSETQBITS(REG,1,1,BITNO,VAL), + () +) + +DEF_MACRO(fVBYTES,(), + "VWIDTH", + "Number of bytes in a vector", + (fVECSIZE()), + () +) + +DEF_MACRO(fVHALVES,(), + "VWIDTH/2", + "Number of halves in a vector", + (fVECSIZE()/2), + () +) + +DEF_MACRO(fVWORDS,(), + "VWIDTH/2", + "Number of words in a vector", + (fVECSIZE()/4), + () +) + +DEF_MACRO(fVDWORDS,(), + "VWIDTH/8", + "Number of double words in a vector", + (fVECSIZE()/8), + () +) + +DEF_MACRO(fVALIGN, (ADDR, LOG2_ALIGNMENT), + "ADDR =3D ADDR & ~(LOG2_ALIGNMENT-1)", + "Align to Element Size", + ( ADDR =3D ADDR & ~(LOG2_ALIGNMENT-1)), + () +) + +DEF_MACRO(fVLASTBYTE, (ADDR, LOG2_ALIGNMENT), + "ADDR =3D ADDR | (LOG2_ALIGNMENT-1)", + "Set LSB of length to last byte", + ( ADDR =3D ADDR | (LOG2_ALIGNMENT-1)), + () +) + + +DEF_MACRO(fVELEM, (WIDTH), + "VBITS/WIDTH", + "Number of WIDTH-bit elements in a vector", + ((fVECSIZE()*8)/WIDTH), + () +) + +DEF_MACRO(fVECLOGSIZE,(), + "log2(VECTOR_SIZE)", + "Log base 2 of the number of bytes in a vector", + (mmvec_current_veclogsize(thread)), + () +) + +DEF_MACRO(fVBUF_IDX,(EA), + "(EA >> log2(VECTOR_SIZE)) & 0xFF", + "(EA >> log2(VECTOR_SIZE)) & 0xFF", + (((EA) >> fVECLOGSIZE()) & 0xFF), + (A_FAKEINSN) +) + +DEF_MACRO(fREAD_VBUF,(IDX,WIDX), + "vbuf[IDX].w[WIDX]", + "vbuf[IDX].w[WIDX]", + READ_VBUF(IDX,WIDX), + (A_FAKEINSN) +) + +DEF_MACRO(fLOG_VBUF,(IDX,VAL,WIDX), + "vbuf[IDX].w[WIDX] =3D VAL", + "vbuf[IDX].w[WIDX] =3D VAL", + LOG_VBUF(IDX,VAL,WIDX), + (A_FAKEINSN) +) + +DEF_MACRO(fVECSIZE,(), + "VBYTES", + "Number of bytes in a vector currently", + (1<VRegs_updated & (((VRegMask)1)<future_VRegs[VNUM] : mmvec_zero_vector()), + (A_DOTNEWVALUE,A_RESTRICT_SLOT0ONLY) +) + +DEF_MACRO( + fV_AL_CHECK, + (EA,MASK), + "", + "", + if ((EA) & (MASK)) { + warn("aligning misaligned vector. PC=3D%08x EA=3D%08x",thread->Regs[REG_= PC],(EA)); + }, + () +) +DEF_MACRO(fSCATTER_INIT, ( REGION_START, LENGTH, ELEMENT_SIZE), + "", + "", + { + mem_vector_scatter_init(thread, insn, REGION_START, LENGTH, ELEMENT_= SIZE); + if (EXCEPTION_DETECTED) return; + }, + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST,A_RESTRICT_SLOT0ONLY) +) + +DEF_MACRO(fGATHER_INIT, ( REGION_START, LENGTH, ELEMENT_SIZE), + "", + "", + { + mem_vector_gather_init(thread, insn, REGION_START, LENGTH, ELEMENT_S= IZE); + if (EXCEPTION_DETECTED) return; + }, + (A_LOAD,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST,A_RESTRICT_SLOT1ONLY) +) + +DEF_MACRO(fSCATTER_FINISH, (OP), + "", + "", + { + if (EXCEPTION_DETECTED) return; + mem_vector_scatter_finish(thread, insn, OP); + }, + () +) + +DEF_MACRO(fGATHER_FINISH, (), + "", + "", + { + if (EXCEPTION_DETECTED) return; + mem_vector_gather_finish(thread, insn); + }, + () +) + + +DEF_MACRO(CHECK_VTCM_PAGE, (FLAG, BASE, LENGTH, OFFSET, ALIGNMENT), + "FLAG=3D((BASE+OFFSET) < (BASE+LENGTH))", + "FLAG=3D((BASE+OFFSET) < (BASE+LENGTH))", + { + int slot =3D insn->slot; + paddr_t pa =3D thread->mem_access[slot].paddr+OFFSET; + pa =3D pa & ~(ALIGNMENT-1); + FLAG =3D (pa < (thread->mem_access[slot].paddr+LENGTH)); + }, + () +) +DEF_MACRO(COUNT_OUT_OF_BOUNDS, (FLAG, SIZE), + " ", + "", + { + if (!FLAG) + { + THREAD2STRUCT->vtcm_log.oob_access +=3D SIZE; + warn("Scatter/Gather out of bounds of region"); + } + }, + () +) + +DEF_MACRO(fLOG_SCATTER_OP, (SIZE), + " ", + " ", + { + // Log the size and indicate that the extension ext.c file needs t= o increment right before memory write + THREAD2STRUCT->vtcm_log.op =3D 1; + THREAD2STRUCT->vtcm_log.op_size =3D SIZE; + }, + () +) + + + +DEF_MACRO(fVLOG_VTCM_WORD_INCREMENT, (EA,OFFSET,INC,IDX,ALIGNMENT,LEN), + "if (RtV <=3D EA <=3D RtV + LEN) *EA +=3D INC.uw[IDX] ", + "if (RtV <=3D EA <=3D RtV + LEN) *EA +=3D INC.uw[IDX] ", + { + int slot =3D insn->slot; + int log_bank =3D 0; + int log_byte =3D0; + paddr_t pa =3D thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMEN= T-1)); + paddr_t pa_high =3D thread->mem_access[slot].paddr+LEN; + for(int i0 =3D 0; i0 < 4; i0++) + { + log_byte =3D ((OFFSET>=3D0)&&((pa+i0)<=3Dpa_high)); + log_bank |=3D (log_byte<slot; + int log_bank =3D 0; + int log_byte =3D 0; + paddr_t pa =3D thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMEN= T-1)); + paddr_t pa_high =3D thread->mem_access[slot].paddr+LEN; + for(int i0 =3D 0; i0 < 2; i0++) { + log_byte =3D ((OFFSET>=3D0)&&((pa+i0)<=3Dpa_high)); + log_bank |=3D (log_byte<slot; + int log_bank =3D 0; + int log_byte =3D 0; + paddr_t pa =3D thread->mem_access[slot].paddr+(OFFSET & ~(ALIGNMEN= T-1)); + paddr_t pa_high =3D thread->mem_access[slot].paddr+LEN; + for(int i0 =3D 0; i0 < 2; i0++) { + log_byte =3D ((OFFSET>=3D0)&&((pa+i0)<=3Dpa_high)); + log_bank |=3D (log_byte<slot; + int i0; + paddr_t pa =3D thread->mem_access[slot].paddr+OFFSET; + paddr_t pa_high =3D thread->mem_access[slot].paddr+LEN; + int log_bank =3D 0; + int log_byte =3D 0; + for(i0 =3D 0; i0 < ELEMENT_SIZE; i0++) + { + log_byte =3D ((OFFSET>=3D0)&&((pa+i0)<=3Dpa_high)) && QVAL; + log_bank |=3D (log_byte<system_ptr, thread->thre= adId, thread->mem_access[slot].paddr+OFFSET+i0); + THREAD2STRUCT->tmp_VRegs[0].ub[ELEMENT_SIZE*IDX+i0] =3D B; + LOG_VTCM_BYTE(pa+i0,log_byte,B,ELEMENT_SIZE*IDX+i0); + } + LOG_VTCM_BANK(pa, log_bank,BANK_IDX); +}, +() +) + + + +DEF_MACRO(fVLOG_VTCM_GATHER_WORD, (EA,OFFSET,IDX, LEN), + "if (RtV <=3D EA <=3D RtV + LEN) TEMP.uw[IDX] =3D *EA ", + "if (RtV <=3D EA <=3D RtV + LEN) TEMP.uw[IDX] =3D *EA ", + { + GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 4, IDX, 1); + }, + () +) +DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORD, (EA,OFFSET,IDX, LEN), + " if (RtV <=3D EA <=3D RtV + LEN) TEMP.uh[IDX] =3D *EA ", + " if (RtV <=3D EA <=3D RtV + LEN) TEMP.uh[IDX] =3D *EA ", + { + GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, IDX, 1); + }, + () +) +DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORD_DV, (EA,OFFSET,IDX,IDX2,IDX_H, LEN), + "if (RtV <=3D EA <=3D RtV + LEN) TEMP.uw[IDX2].uh[IDX_H] =3D *EA ", + "if (RtV <=3D EA <=3D RtV + LEN) TEMP.uw[IDX2].uh[IDX_H] =3D *EA ", + { + GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), 1); + }, + () +) +DEF_MACRO(fVLOG_VTCM_GATHER_WORDQ, (EA,OFFSET,IDX, Q, LEN), + " if ( (RtV <=3D EA <=3D RtV + LEN) & Q) TEMP.uw[IDX] =3D *EA ", + " if ( (RtV <=3D EA <=3D RtV + LEN) & Q) TEMP.uw[IDX] =3D *EA ", + { + GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 4, IDX, fGETQBIT(QsV,4*IDX+i0)); + }, + () +) +DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORDQ, (EA,OFFSET,IDX, Q, LEN), + " if ( (RtV <=3D EA <=3D RtV + LEN) & Q) TEMP.uh[IDX] =3D *EA ", + " if ( (RtV <=3D EA <=3D RtV + LEN) & Q) TEMP.uh[IDX] =3D *EA ", + { + GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, IDX, fGETQBIT(QsV,2*IDX+i0)); + }, + () +) + +DEF_MACRO(fVLOG_VTCM_GATHER_HALFWORDQ_DV, (EA,OFFSET,IDX,IDX2,IDX_H, Q, LE= N), + " if ( (RtV <=3D EA <=3D RtV + LEN) & Q) TEMP.uw[IDX2].uh[IDX_H] =3D *= EA ", + " if ( (RtV <=3D EA <=3D RtV + LEN) & Q) TEMP.uw[IDX2].uh[IDX_H] =3D *= EA ", + { + GATHER_FUNCTION(EA,OFFSET,IDX, LEN, 2, (2*IDX2+IDX_H), fGETQBIT(QsV,2*ID= X+i0)); + }, + () +) + + +DEF_MACRO(DEBUG_LOG_ADDR, (OFFSET), + " ", + " ", + { + + if (thread->processor_ptr->arch_proc_options->mmvec_network_addr_l= og2) + { + + int slot =3D insn->slot; + paddr_t pa =3D thread->mem_access[slot].paddr+OFFSET; + } + }, + () +) + + + + + + + +DEF_MACRO(SCATTER_OP_WRITE_TO_MEM, (TYPE), + " Read, accumulate, and write to VTCM", + " ", + { + for (int i =3D 0; i < mmvecx->vtcm_log.size; i+=3Dsizeof(TYPE)) + { + if ( mmvecx->vtcm_log.mask.ub[i] !=3D 0) { + TYPE dst =3D 0; + TYPE inc =3D 0; + for(int j =3D 0; j < sizeof(TYPE); j++) { + dst |=3D (sim_mem_read1(thread->system_ptr, thread->th= readId, mmvecx->vtcm_log.pa[i+j]) << (8*j)); + inc |=3D mmvecx->vtcm_log.data.ub[j+i] << (8*j); + + mmvecx->vtcm_log.mask.ub[j+i] =3D 0; + mmvecx->vtcm_log.data.ub[j+i] =3D 0; + mmvecx->vtcm_log.offsets.ub[j+i] =3D 0; + } + dst +=3D inc; + for(int j =3D 0; j < sizeof(TYPE); j++) { + sim_mem_write1(thread->system_ptr,thread->threadId, mm= vecx->vtcm_log.pa[i+j], (dst >> (8*j))& 0xFF ); + } + } + + } + }, + () +) + +DEF_MACRO(SCATTER_FUNCTION, (EA,OFFSET,IDX, LEN, ELEMENT_SIZE, BANK_IDX, Q= VAL, IN), +"", +"", +{ + int slot =3D insn->slot; + int i0; + paddr_t pa =3D thread->mem_access[slot].paddr+OFFSET; + paddr_t pa_high =3D thread->mem_access[slot].paddr+LEN; + int log_bank =3D 0; + int log_byte =3D 0; + for(i0 =3D 0; i0 < ELEMENT_SIZE; i0++) { + log_byte =3D ((OFFSET>=3D0)&&((pa+i0)<=3Dpa_high)) && QVAL; + log_bank |=3D (log_byte<processor_ptr)); + }, + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST) +) + +DEF_MACRO(fVFETCH_AL, (EA), + "Prefetch vector into L2 cache at EA", + "Prefetch vector into L2 cache at EA", + { + fV_AL_CHECK(EA,fVECSIZE()-1); + mem_fetch_vector(thread, insn, EA&~(fVECSIZE()-1), insn->slot, fVECSIZ= E()); + }, + (A_LOAD,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST,A_RESTRICT_NOSLOT1_STORE) +) + + +DEF_MACRO(fLOADMMV_AL, (EA, ALIGNMENT, LEN, DST), + "char* addr =3D EA&~(ALIGNMENT-1); for (i=3D0; ilast_pkt->double_access_vec =3D 0; + mem_load_vector_oddva(thread, insn, EA&~(ALIGNMENT-1), EA, insn->slot,= LEN, &DST.ub[0], LEN, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr)); + }, + (A_LOAD,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST,A_RESTRICT_NOSLOT1_STORE) +) + +DEF_MACRO(fLOADMMV, (EA, DST), + "DST =3D *(EA&~(ALIGNMENT-1))", + "Load vector from memory at EA (forced alignment) to DST.", + fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST), + () +) + +DEF_MACRO(fLOADMMVQ, (EA,DST,QVAL), + "DST =3D vmux(QVAL,*(EA&~(ALIGNMENT-1)),0)", + "Load vector from memory at EA (forced alignment) to DST.", + do { + int __i; + fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST); + fVFOREACH(8,__i) if (!fGETQBIT(QVAL,__i)) DST.b[__i] =3D 0; + } while (0), + () +) + +DEF_MACRO(fLOADMMVNQ, (EA,DST,QVAL), + "DST =3D vmux(QVAL,0,*(EA&~(ALIGNMENT-1)))", + "Load vector from memory at EA (forced alignment) to DST.", + do { + int __i; + fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST); + fVFOREACH(8,__i) if (fGETQBIT(QVAL,__i)) DST.b[__i] =3D 0; + } while (0), + () +) + +DEF_MACRO(fLOADMMVU_AL, (EA, ALIGNMENT, LEN, DST), + "char* addr =3D EA; for (i=3D0; ilast_pkt->double_access_vec =3D 1; + mem_load_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot *= / 1, size2, &DST.ub[size1], size2, fUSE_LOOKUP_ADDRESS()); + mem_load_vector_oddva(thread, insn, EA, EA,/* slot */ 0, size1, &DST.u= b[0], size1, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr)); + }, + (A_LOAD,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST,A_RESTRICT_NOSLOT1_STORE) +) + +DEF_MACRO(fLOADMMVU, (EA, DST), + "DST =3D *EA", + "Load vector from memory at EA (unaligned) to DST.", + { + /* if address happens to be aligned, only do aligned load */ + thread->last_pkt->pkt_has_vtcm_access =3D 0; + thread->last_pkt->pkt_access_count =3D 0; + if ( (EA & (fVECSIZE()-1)) =3D=3D 0) { + thread->last_pkt->pkt_has_vmemu_access =3D 0; + thread->last_pkt->double_access =3D 0; + + fLOADMMV_AL(EA,fVECSIZE(),fVECSIZE(),DST); + } else { + thread->last_pkt->pkt_has_vmemu_access =3D 1; + thread->last_pkt->double_access =3D 1; + + fLOADMMVU_AL(EA,fVECSIZE(),fVECSIZE(),DST); + } + }, + () +) + +DEF_MACRO(fSTOREMMV_AL, (EA, ALIGNMENT, LEN, SRC), + "char* addr =3D EA&~(ALIGNMENT-1); for (i=3D0; islot= , LEN, &SRC.ub[0], 0, 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr)); + }, + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST) +) + +DEF_MACRO(fSTOREMMV, (EA, SRC), + "*(EA&~(ALIGNMENT-1)) =3D SRC", + "Store vector SRC to memory at EA (unaligned).", + fSTOREMMV_AL(EA,fVECSIZE(),fVECSIZE(),SRC), + () +) + +DEF_MACRO(fSTOREMMVQ_AL, (EA, ALIGNMENT, LEN, SRC, MASK), + "char* addr =3D EA&~(ALIGNMENT-1); for (i=3D0; islot, L= EN, &SRC.ub[0], &maskvec.ub[0], 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->proce= ssor_ptr)); + } while (0), + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST) +) + +DEF_MACRO(fSTOREMMVQ, (EA, SRC, MASK), + "*(EA&~(ALIGNMENT-1)) =3D SRC", + "Masked store vector SRC to memory at EA (forced alignment).", + fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK), + () +) + +DEF_MACRO(fSTOREMMVNQ_AL, (EA, ALIGNMENT, LEN, SRC, MASK), + "char* addr =3D EA&~(ALIGNMENT-1); for (i=3D0; islot, L= EN, &SRC.ub[0], &maskvec.ub[0], 1, fUSE_LOOKUP_ADDRESS_BY_REV(thread->proce= ssor_ptr)); + }, + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST) +) + +DEF_MACRO(fSTOREMMVNQ, (EA, SRC, MASK), + "*(EA&~(ALIGNMENT-1)) =3D SRC", + "Masked negated store vector SRC to memory at EA (forced alignment).", + fSTOREMMVNQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK), + () +) + +DEF_MACRO(fSTOREMMVU_AL, (EA, ALIGNMENT, LEN, SRC), + "char* addr =3D EA; for (i=3D0; iLEN) size1 =3D LEN; + size2 =3D LEN-size1; + mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot = */ 1, size2, &SRC.ub[size1], 0, 0, fUSE_LOOKUP_ADDRESS()); + mem_store_vector_oddva(thread, insn, EA, EA, /* slot */ 0, size1, &SRC= .ub[0], 0, 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr)); + }, + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST) +) + +DEF_MACRO(fSTOREMMVU, (EA, SRC), + "*EA =3D SRC", + "Store vector SRC to memory at EA (unaligned).", + { + thread->last_pkt->pkt_has_vtcm_access =3D 0; + thread->last_pkt->pkt_access_count =3D 0; + if ( (EA & (fVECSIZE()-1)) =3D=3D 0) { + thread->last_pkt->double_access =3D 0; + fSTOREMMV_AL(EA,fVECSIZE(),fVECSIZE(),SRC); + } else { + thread->last_pkt->double_access =3D 1; + thread->last_pkt->pkt_has_vmemu_access =3D 1; + fSTOREMMVU_AL(EA,fVECSIZE(),fVECSIZE(),SRC); + } + }, + () +) + +DEF_MACRO(fSTOREMMVQU_AL, (EA, ALIGNMENT, LEN, SRC, MASK), + "char* addr =3D EA; for (i=3D0; iLEN) size1 =3D LEN; + size2 =3D LEN-size1; + mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(),/* slot */ 1= , size2, &SRC.ub[size1], &maskvec.ub[size1], 0, fUSE_LOOKUP_ADDRESS()); + mem_store_vector_oddva(thread, insn, EA, /* slot */ 0, size1, &SRC.ub[0],= &maskvec.ub[0], 0, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr)); + }, + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST) +) + +DEF_MACRO(fSTOREMMVQU, (EA, SRC, MASK), + "*EA =3D SRC", + "Store vector SRC to memory at EA (unaligned).", + { + thread->last_pkt->pkt_has_vtcm_access =3D 0; + thread->last_pkt->pkt_access_count =3D 0; + if ( (EA & (fVECSIZE()-1)) =3D=3D 0) { + thread->last_pkt->double_access =3D 0; + fSTOREMMVQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK); + } else { + thread->last_pkt->double_access =3D 1; + thread->last_pkt->pkt_has_vmemu_access =3D 1; + fSTOREMMVQU_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK); + } + }, + () +) + +DEF_MACRO(fSTOREMMVNQU_AL, (EA, ALIGNMENT, LEN, SRC, MASK), + "char* addr =3D EA; for (i=3D0; iLEN) size1 =3D LEN; + size2 =3D LEN-size1; + mem_store_vector_oddva(thread, insn, EA+size1, EA+fVECSIZE(), /* slot */ = 1, size2, &SRC.ub[size1], &maskvec.ub[size1], 1, fUSE_LOOKUP_ADDRESS()); + mem_store_vector_oddva(thread, insn, EA, EA, /* slot */ 0, size1, &SRC.ub= [0], &maskvec.ub[0], 1, fUSE_LOOKUP_ADDRESS_BY_REV(thread->processor_ptr)); + }, + (A_STORE,A_MEMLIKE,A_RESTRICT_SINGLE_MEM_FIRST) +) + +DEF_MACRO(fSTOREMMVNQU, (EA, SRC, MASK), + "*EA =3D SRC", + "Store vector SRC to memory at EA (unaligned).", + { + thread->last_pkt->pkt_has_vtcm_access =3D 0; + thread->last_pkt->pkt_access_count =3D 0; + if ( (EA & (fVECSIZE()-1)) =3D=3D 0) { + thread->last_pkt->double_access =3D 0; + fSTOREMMVNQ_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK); + } else { + thread->last_pkt->double_access =3D 1; + thread->last_pkt->pkt_has_vmemu_access =3D 1; + fSTOREMMVNQU_AL(EA,fVECSIZE(),fVECSIZE(),SRC,MASK); + } + }, + () +) + + + + +DEF_MACRO(fVFOREACH,(WIDTH, VAR), + "for (VAR =3D 0; VAR < VELEM(WIDTH); VAR++)", + "For VAR in each WIDTH-bit vector index", + for (VAR =3D 0; VAR < fVELEM(WIDTH); VAR++), + /* NOTHING */ +) + +DEF_MACRO(fVARRAY_ELEMENT_ACCESS, (ARRAY, TYPE, INDEX), + "ARRAY.TYPE[INDEX]", + "Access element of type TYPE at position INDEX of flattened ARRAY", + ARRAY.v[(INDEX) / (fVECSIZE()/(sizeof(ARRAY.TYPE[0])))].TYPE[(INDEX) %= (fVECSIZE()/(sizeof(ARRAY.TYPE[0])))], + () +) + +DEF_MACRO(fVNEWCANCEL,(REGNUM), + "Ignore current value for register REGNUM", + "Ignore current value for register REGNUM", + do { THREAD2STRUCT->VRegs_select &=3D ~(1<<(REGNUM)); } while (0), + () +) + +DEF_MACRO(fTMPVDATA,(), + "Data from .tmp load", + "Data from .tmp load and clear tmp status", + mmvec_vtmp_data(thread), + (A_CVI,A_CVI_REQUIRES_TMPLOAD) +) + +DEF_MACRO(fVSATDW, (U,V), + "usat_32(U:V)", + "Use 32-bits of U as MSW and 32-bits of V as LSW and saturate the resu= ltant 64-bits to 32 bits", + fVSATW( ( ( ((long long)U)<<32 ) | fZXTN(32,64,V) ) ), + /* attribs */ +) + +DEF_MACRO(fVASL_SATHI, (U,V), + "uasl_sathi(U:V)", + "Use 32-bits of U as MSW and 32-bits of V as LSW, left shift by 1 and = saturate the result and take high word", + fVSATW(((U)<<1) | ((V)>>31)), + /* attribs */ +) + +DEF_MACRO(fVUADDSAT,(WIDTH,U,V), + "usat_##WIDTH(U+V)", + "Add WIDTH-bit values U and V with saturation", + fVSATUN( WIDTH, fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V)), + /* attribs */ +) + +DEF_MACRO(fVSADDSAT,(WIDTH,U,V), + "sat_##WIDTH(U+V)", + "Add WIDTH-bit values U and V with saturation", + fVSATN( WIDTH, fSXTN(WIDTH, 2*WIDTH, U) + fSXTN(WIDTH, 2*WIDTH, V)), + /* attribs */ +) + +DEF_MACRO(fVUSUBSAT,(WIDTH,U,V), + "usat_##WIDTH(U-V)", + "sub WIDTH-bit values U and V with saturation", + fVSATUN( WIDTH, fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V)), + /* attribs */ +) + +DEF_MACRO(fVSSUBSAT,(WIDTH,U,V), + "sat_##WIDTH(U-V)", + "sub WIDTH-bit values U and V with saturation", + fVSATN( WIDTH, fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V)), + /* attribs */ +) + +DEF_MACRO(fVAVGU,(WIDTH,U,V), + "(U+V)/2", + "average WIDTH-bit values U and V with saturation", + ((fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V))>>1), + /* attribs */ +) + +DEF_MACRO(fVAVGURND,(WIDTH,U,V), + "(U+V+1)/2", + "average WIDTH-bit values U and V with saturation", + ((fZXTN(WIDTH, 2*WIDTH, U) + fZXTN(WIDTH, 2*WIDTH, V)+1)>>1), + /* attribs */ +) + +DEF_MACRO(fVNAVGU,(WIDTH,U,V), + "(U-V)/2", + "average WIDTH-bit values U and V with saturation", + ((fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V))>>1), + /* attribs */ +) + +DEF_MACRO(fVNAVGURNDSAT,(WIDTH,U,V), + "(U-V+1)/2", + "average WIDTH-bit values U and V with saturation", + fVSATUN(WIDTH,((fZXTN(WIDTH, 2*WIDTH, U) - fZXTN(WIDTH, 2*WIDTH, V)+1)>>1= )), + /* attribs */ +) + +DEF_MACRO(fVAVGS,(WIDTH,U,V), + "(U+V)/2", + "average WIDTH-bit values U and V with saturation", + ((fSXTN(WIDTH, 2*WIDTH, U) + fSXTN(WIDTH, 2*WIDTH, V))>>1), + /* attribs */ +) + +DEF_MACRO(fVAVGSRND,(WIDTH,U,V), + "(U+V+1)/2", + "average WIDTH-bit values U and V with saturation", + ((fSXTN(WIDTH, 2*WIDTH, U) + fSXTN(WIDTH, 2*WIDTH, V)+1)>>1), + /* attribs */ +) + +DEF_MACRO(fVNAVGS,(WIDTH,U,V), + "(U-V)/2", + "average WIDTH-bit values U and V with saturation", + ((fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V))>>1), + /* attribs */ +) + +DEF_MACRO(fVNAVGSRND,(WIDTH,U,V), + "(U-V+1)/2", + "average WIDTH-bit values U and negative V followed by rounding", + ((fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V)+1)>>1), + /* attribs */ +) + +DEF_MACRO(fVNAVGSRNDSAT,(WIDTH,U,V), + "(U-V+1)/2", + "average WIDTH-bit values U and V with saturation", + fVSATN(WIDTH,((fSXTN(WIDTH, 2*WIDTH, U) - fSXTN(WIDTH, 2*WIDTH, V)+1)>>1)= ), + /* attribs */ +) + + +DEF_MACRO(fVNOROUND,(VAL,SHAMT), + "VAL", + "VAL", + VAL, + /* NOTHING */ +) +DEF_MACRO(fVNOSAT,(VAL), + "VAL", + "VAL", + VAL, + /* NOTHING */ +) + +DEF_MACRO(fVROUND,(VAL,SHAMT), + "VAL + (1<<(SHAMT-1))", + "VAL + RNDBIT", + ((VAL) + (((SHAMT)>0)?(1LL<<((SHAMT)-1)):0)), + /* NOTHING */ +) + +DEF_MACRO(fCARRY_FROM_ADD32,(A,B,C), + "carry_from(A,B,C)", + "carry_from(A,B,C)", + (((fZXTN(32,64,A)+fZXTN(32,64,B)+C) >> 32) & 1), + /* NOTHING */ +) + +DEF_MACRO(fUARCH_NOTE_PUMP_4X,(), + "", + "", + , + (A_CVI_PUMP_4X) +) + +DEF_MACRO(fUARCH_NOTE_PUMP_2X,(), + "", + "", + , + (A_CVI_PUMP_2X) +) + +DEF_MACRO(fVDOCHKPAGECROSS,(BASE,SUM), + "", + "", + if (UNLIKELY(thread->timing_on)) { + thread->mem_access[slot].check_page_crosses =3D 1; + thread->mem_access[slot].page_cross_base =3D BASE; + thread->mem_access[slot].page_cross_sum =3D SUM; + }, + (A_EA_PAGECROSS) +) + + + --=20 2.7.4