From nobody Thu Nov 13 22:06:42 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com ARC-Seal: i=1; a=rsa-sha256; t=1582911425; cv=none; d=zohomail.com; s=zohoarc; b=KTVdhKFEHu9fOHOVWvebXEWFehoSDI0hsX/OnNiQk5g9LOkTmK0Fj2iN2qM0Hx3Px1PtkTPPwf1k6Zgt5ToOkTQPwxqOv7AiK2jXOs+lUeV/w/nZMqMJLbWqYLzqUcAfDazbEZEPKsmKPgFZSS0iomzHNVSXhdIVckGqv5VaJNk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582911425; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=grG2DWjHiXDpDGIYPvPtPCRBOOeWAaNf7rQdQlzQBKI=; b=f2d0wyhhTl3zheFoXlAqQwRRtcpfRXePk9cLjQ/5QJvKPJGuFIiSaF6H4iwPcgtT4GaRpWlqff8n9C1zdNfLZvZAIYWFsQFN48n7LsNiOiIuwvU0EkxHb6JR3jJxEDtxqlmyEbdjdSG2+wYV1hWbePDaPMXdOY1MZ0KeSDfRwUY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582911425663218.8190890223069; Fri, 28 Feb 2020 09:37:05 -0800 (PST) Received: from localhost ([::1]:51661 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7jZP-00052G-1s for importer@patchew.org; Fri, 28 Feb 2020 12:37:03 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:58409) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j7im2-0005bG-Jm for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:05 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j7ily-00078d-QR for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:46:02 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:27035) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j7ily-0005Ug-Ff for qemu-devel@nongnu.org; Fri, 28 Feb 2020 11:45:58 -0500 Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-02.qualcomm.com with ESMTP; 28 Feb 2020 08:44:33 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg-SD-alpha.qualcomm.com with ESMTP; 28 Feb 2020 08:44:33 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id D172DFD8; Fri, 28 Feb 2020 10:44:32 -0600 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1582908358; x=1614444358; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=grG2DWjHiXDpDGIYPvPtPCRBOOeWAaNf7rQdQlzQBKI=; b=F72dedL7bqx/ydHCS3VBBEkXDJKBYxVT1VOdHv7RJFKa0jxs4vUWcZVY YseUu5qOhamGzCAkbON2se7gzpX0yqVk6OWUCuBAaJZM+lAA2eVfFr0BV LsQBcayZoqTaXHGUL9ckT1kGK77GnRqlinmFkcr1JUmquQYJdv8kit2cU k=; From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH v2 54/67] Hexagon - Add Hexagon Vector eXtensions (HVX) to core definition Date: Fri, 28 Feb 2020 10:43:50 -0600 Message-Id: <1582908244-304-55-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> References: <1582908244-304-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) HVX is a set of wide vector instructions. Machine state includes vector registers (VRegs) vector predicate registers (QRegs) temporary registers for packet semantics store buffer (masked stores and scatter/gather) Signed-off-by: Taylor Simpson --- target/hexagon/cpu.h | 42 +++++++++++++++++++++ target/hexagon/insn.h | 16 ++++++++ target/hexagon/internal.h | 2 + target/hexagon/mmvec/mmvec.h | 87 ++++++++++++++++++++++++++++++++++++++++= ++++ target/hexagon/cpu.c | 51 +++++++++++++++++++++++++- 5 files changed, 197 insertions(+), 1 deletion(-) create mode 100644 target/hexagon/mmvec/mmvec.h diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 6146561..6215f91 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -30,6 +30,7 @@ typedef struct CPUHexagonState CPUHexagonState; #include "qemu-common.h" #include "exec/cpu-defs.h" #include "hex_regs.h" +#include "mmvec/mmvec.h" =20 #define NUM_PREGS 4 #ifdef CONFIG_USER_ONLY @@ -42,6 +43,7 @@ typedef struct CPUHexagonState CPUHexagonState; #define STORES_MAX 2 #define REG_WRITES_MAX 32 #define PRED_WRITES_MAX 5 /* 4 insns + endloop */ +#define VSTORES_MAX 2 =20 #define TYPE_HEXAGON_CPU "hexagon-cpu" =20 @@ -60,6 +62,19 @@ struct MemLog { uint64_t data64; }; =20 +typedef struct { + target_ulong va; + int size; + mmvector_t mask; + mmvector_t data; +} vstorelog_t; + +typedef struct { + unsigned char cdata[256]; + uint32_t range; + uint8_t format; +} mem_access_info_t; + #define EXEC_STATUS_OK 0x0000 #define EXEC_STATUS_STOP 0x0002 #define EXEC_STATUS_REPLAY 0x0010 @@ -72,6 +87,9 @@ struct MemLog { #define CLEAR_EXCEPTION (env->status &=3D (~EXEC_STATUS_EXCEPTION)) #define SET_EXCEPTION (env->status |=3D EXEC_STATUS_EXCEPTION) =20 +/* This needs to be large enough for all the reads and writes in a packet = */ +#define TEMP_VECTORS_MAX 25 + struct CPUHexagonState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; @@ -110,6 +128,30 @@ struct CPUHexagonState { =20 target_ulong is_gather_store_insn; target_ulong gather_issued; + + mmvector_t VRegs[NUM_VREGS]; + mmvector_t future_VRegs[NUM_VREGS]; + mmvector_t tmp_VRegs[NUM_VREGS]; + + VRegMask VRegs_updated_tmp; + VRegMask VRegs_updated; + VRegMask VRegs_select; + + mmqreg_t QRegs[NUM_QREGS]; + mmqreg_t future_QRegs[NUM_QREGS]; + QRegMask QRegs_updated; + + vstorelog_t vstore[VSTORES_MAX]; + uint8_t store_pending[VSTORES_MAX]; + uint8_t vstore_pending[VSTORES_MAX]; + uint8_t vtcm_pending; + vtcm_storelog_t vtcm_log; + mem_access_info_t mem_access[SLOTS_MAX]; + + int status; + + mmvector_t temp_vregs[TEMP_VECTORS_MAX]; + mmqreg_t temp_qregs[TEMP_VECTORS_MAX]; }; =20 #define HEXAGON_CPU_CLASS(klass) \ diff --git a/target/hexagon/insn.h b/target/hexagon/insn.h index a80bcb9..16d298d 100644 --- a/target/hexagon/insn.h +++ b/target/hexagon/insn.h @@ -49,12 +49,16 @@ struct Instruction { size4u_t is_dcfetch:1; /* Has an A_DCFETCH attribute */ size4u_t is_load:1; /* Has A_LOAD attribute */ size4u_t is_store:1; /* Has A_STORE attribute */ + size4u_t is_vmem_ld:1; /* Has an A_LOAD and an A_VMEM attribute */ + size4u_t is_vmem_st:1; /* Has an A_STORE and an A_VMEM attribute */ + size4u_t is_scatgath:1; /* Has an A_CVI_GATHER or A_CVI_SCATTER attr = */ size4u_t is_memop:1; /* Has A_MEMOP attribute */ size4u_t is_dealloc:1; /* Is a dealloc return or dealloc frame */ size4u_t is_aia:1; /* Is a post increment */ size4u_t is_endloop:1; /* This is an end of loop */ size4u_t is_2nd_jump:1; /* This is the second jump of a dual-jump pac= ket */ size4u_t new_value_producer_slot:4; + size4u_t hvx_resource:8; size4s_t immed[IMMEDS_MAX]; /* immediate field */ }; =20 @@ -121,10 +125,22 @@ struct Packet { =20 /* Misc */ size8u_t num_rops:4; /* Num risc ops in the packet */ + size8u_t pkt_has_vtcm_access:1; /* Is a vmem access going to VTCM */ size8u_t pkt_access_count:2; /* Is a vmem access going to VTCM */ size8u_t pkt_ldaccess_l2:2; /* vmem ld access to l2 */ size8u_t pkt_ldaccess_vtcm:2; /* vmem ld access to vtcm */ =20 + /* Count the types of HVX instructions */ + size8u_t pkt_hvx_va:4; + size8u_t pkt_hvx_vx:4; + size8u_t pkt_hvx_vp:4; + size8u_t pkt_hvx_vs:4; + size8u_t pkt_hvx_all:4; + size8u_t pkt_hvx_none:4; + + size8u_t pkt_has_hvx:1; + size8u_t pkt_has_extension:1; + insn_t insn[INSTRUCTIONS_MAX]; }; =20 diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index 092dedc..4ff7020 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -39,6 +39,8 @@ extern int hexagon_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); extern int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg= ); =20 +extern void hexagon_debug_vreg(CPUHexagonState *env, int regnum); +extern void hexagon_debug_qreg(CPUHexagonState *env, int regnum); extern void hexagon_debug(CPUHexagonState *env); =20 #if COUNT_HEX_HELPERS diff --git a/target/hexagon/mmvec/mmvec.h b/target/hexagon/mmvec/mmvec.h new file mode 100644 index 0000000..145af15 --- /dev/null +++ b/target/hexagon/mmvec/mmvec.h @@ -0,0 +1,87 @@ +/* + * Copyright(c) 2019-2020 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef HEXAGON_MMVEC_H +#define HEXAGON_MMVEC_H + +#define MAX_VEC_SIZE_LOGBYTES 7 +#define MAX_VEC_SIZE_BYTES (1 << MAX_VEC_SIZE_LOGBYTES) + +#define NUM_VREGS 32 +#define NUM_QREGS 4 + +typedef uint32_t VRegMask; /* at least NUM_VREGS bits */ +typedef uint32_t QRegMask; /* at least NUM_QREGS bits */ + +#define VECTOR_SIZE_BYTE (fVECSIZE()) + +typedef union { + uint64_t ud[MAX_VEC_SIZE_BYTES / 8]; + int64_t d[MAX_VEC_SIZE_BYTES / 8]; + uint32_t uw[MAX_VEC_SIZE_BYTES / 4]; + int32_t w[MAX_VEC_SIZE_BYTES / 4]; + uint16_t uh[MAX_VEC_SIZE_BYTES / 2]; + int16_t h[MAX_VEC_SIZE_BYTES / 2]; + uint8_t ub[MAX_VEC_SIZE_BYTES / 1]; + int8_t b[MAX_VEC_SIZE_BYTES / 1]; +} mmvector_t; + +typedef union { + uint64_t ud[2 * MAX_VEC_SIZE_BYTES / 8]; + int64_t d[2 * MAX_VEC_SIZE_BYTES / 8]; + uint32_t uw[2 * MAX_VEC_SIZE_BYTES / 4]; + int32_t w[2 * MAX_VEC_SIZE_BYTES / 4]; + uint16_t uh[2 * MAX_VEC_SIZE_BYTES / 2]; + int16_t h[2 * MAX_VEC_SIZE_BYTES / 2]; + uint8_t ub[2 * MAX_VEC_SIZE_BYTES / 1]; + int8_t b[2 * MAX_VEC_SIZE_BYTES / 1]; + mmvector_t v[2]; +} mmvector_pair_t; + +typedef union { + uint64_t ud[MAX_VEC_SIZE_BYTES / 8 / 8]; + int64_t d[MAX_VEC_SIZE_BYTES / 8 / 8]; + uint32_t uw[MAX_VEC_SIZE_BYTES / 4 / 8]; + int32_t w[MAX_VEC_SIZE_BYTES / 4 / 8]; + uint16_t uh[MAX_VEC_SIZE_BYTES / 2 / 8]; + int16_t h[MAX_VEC_SIZE_BYTES / 2 / 8]; + uint8_t ub[MAX_VEC_SIZE_BYTES / 1 / 8]; + int8_t b[MAX_VEC_SIZE_BYTES / 1 / 8]; +} mmqreg_t; + +typedef struct { + mmvector_t data; + mmvector_t mask; + mmvector_pair_t offsets; + int size; + target_ulong va_base; + target_ulong va[MAX_VEC_SIZE_BYTES]; + int oob_access; + int op; + int op_size; +} vtcm_storelog_t; + + +/* Types of vector register assignment */ +typedef enum { + EXT_DFL, /* Default */ + EXT_NEW, /* New - value used in the same packet */ + EXT_TMP /* Temp - value used but not stored to register */ +} vector_dst_type_t; + +#endif + diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index 576c566..ccbc113 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -122,6 +122,39 @@ static void print_reg(FILE *f, CPUHexagonState *env, i= nt regnum) fprintf(f, " %s =3D 0x" TARGET_FMT_lx "\n", hexagon_regnames[regnum],= value); } =20 +static void print_vreg(FILE *f, CPUHexagonState *env, int regnum) +{ + int i; + fprintf(f, " v%d =3D (", regnum); + fprintf(f, "0x%02x", env->VRegs[regnum].ub[MAX_VEC_SIZE_BYTES - 1]); + for (i =3D MAX_VEC_SIZE_BYTES - 2; i >=3D 0; i--) { + fprintf(f, ", 0x%02x", env->VRegs[regnum].ub[i]); + } + fprintf(f, ")\n"); +} + +void hexagon_debug_vreg(CPUHexagonState *env, int regnum) +{ + print_vreg(stdout, env, regnum); +} + +static void print_qreg(FILE *f, CPUHexagonState *env, int regnum) +{ + int i; + fprintf(f, " q%d =3D (", regnum); + fprintf(f, ", 0x%02x", + env->QRegs[regnum].ub[MAX_VEC_SIZE_BYTES / 8 - 1]); + for (i =3D MAX_VEC_SIZE_BYTES / 8 - 2; i >=3D 0; i--) { + fprintf(f, ", 0x%02x", env->QRegs[regnum].ub[i]); + } + fprintf(f, ")\n"); +} + +void hexagon_debug_qreg(CPUHexagonState *env, int regnum) +{ + print_qreg(stdout, env, regnum); +} + static void hexagon_dump(CPUHexagonState *env, FILE *f) { static target_ulong last_pc; @@ -166,6 +199,22 @@ static void hexagon_dump(CPUHexagonState *env, FILE *f) print_reg(f, env, HEX_REG_CS1); #endif fprintf(f, "}\n"); + +/* + * The HVX register dump takes up a ton of space in the log + * Don't print it unless it is needed + */ +#define DUMP_HVX 0 +#if DUMP_HVX + fprintf(f, "Vector Registers =3D {\n"); + for (i =3D 0; i < NUM_VREGS; i++) { + print_vreg(f, env, i); + } + for (i =3D 0; i < NUM_QREGS; i++) { + print_qreg(f, env, i); + } + fprintf(f, "}\n"); +#endif } =20 static void hexagon_dump_state(CPUState *cs, FILE *f, int flags) @@ -291,7 +340,7 @@ static void hexagon_cpu_class_init(ObjectClass *c, void= *data) cc->gdb_core_xml_file =3D "hexagon-core.xml"; cc->gdb_read_register =3D hexagon_gdb_read_register; cc->gdb_write_register =3D hexagon_gdb_write_register; - cc->gdb_num_core_regs =3D TOTAL_PER_THREAD_REGS; + cc->gdb_num_core_regs =3D TOTAL_PER_THREAD_REGS + NUM_VREGS + NUM_QREG= S; cc->gdb_stop_before_watchpoint =3D true; cc->disas_set_info =3D hexagon_cpu_disas_set_info; #ifdef CONFIG_TCG --=20 2.7.4