From nobody Thu Nov 13 20:39:58 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582551786; cv=none; d=zohomail.com; s=zohoarc; b=Y7oWGoPXtDWiic8OBo569ZrRA8QrIo2eus2PfrHuADFzMQR7s/FF7FziqdP5CdXibd3M9NMbhxeiTx0vcNelwm7ZfCsqDBTSyp3adNWNu9OWu6FLon9K83yK7EonDXx6yb2jQ1xh/dK+tiwoiMSfw4aR22zgWfacWkNNfo0VOYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582551786; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=9G7GqsVBmIkQM+dcv8dG3CzT4k7w3scNqDwrrmksuiw=; b=TZbdTqM7cYQZWmw4jD46P8V05WttD4+y1zE702rMY6m9VZiSo7i22TcW5AUFIrROJ82uIXA65joV9za7GADcJAjyT1vjNpeMV/Z7X2lRyRivJFo4hpnRrjx789WEur9BnVEJ9cVWYBIbEdWCmyQrTDDtnE/qWKhQ5mt9x+A5jUE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582551786974384.5368433502596; Mon, 24 Feb 2020 05:43:06 -0800 (PST) Received: from localhost ([::1]:36598 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6E0o-0006fl-0H for importer@patchew.org; Mon, 24 Feb 2020 08:43:06 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42276) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j6Dxw-0001pn-6s for qemu-devel@nongnu.org; Mon, 24 Feb 2020 08:40:11 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j6Dxs-0004Iw-Hg for qemu-devel@nongnu.org; Mon, 24 Feb 2020 08:40:08 -0500 Received: from mga04.intel.com ([192.55.52.120]:21084) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j6Dxs-0004HT-9s for qemu-devel@nongnu.org; Mon, 24 Feb 2020 08:40:04 -0500 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 24 Feb 2020 05:40:01 -0800 Received: from snr.bj.intel.com ([10.240.193.90]) by FMSMGA003.fm.intel.com with ESMTP; 24 Feb 2020 05:39:59 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,480,1574150400"; d="scan'208";a="284354737" From: Luwei Kang To: pbonzini@redhat.com, rth@twiddle.net, ehabkost@redhat.com Subject: [PATCH v1 2/3] i386: Remove the CPUID limitation of Intel PT Date: Tue, 25 Feb 2020 05:38:31 +0800 Message-Id: <1582580312-19864-3-git-send-email-luwei.kang@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1582580312-19864-1-git-send-email-luwei.kang@intel.com> References: <1582580312-19864-1-git-send-email-luwei.kang@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Luwei Kang , qemu-devel@nongnu.org, beeman.strong@intel.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" To make Intel PT live migration safe and get same CPUID information with same CPU model on diffrent host. CPUID[14] is set to constant value in "e37a5c7 i386: Add Intel Processor Trace feature support". But it will block the new features of Intel PT. This patch will remove this limitation and expose all the capabilities to guest. Signed-off-by: Luwei Kang --- target/i386/cpu.c | 65 ++++-----------------------------------------------= ---- 1 file changed, 4 insertions(+), 61 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 8c0d1e4..4d9e203 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -667,33 +667,6 @@ static CPUCacheInfo legacy_l3_cache =3D { #define L2_ITLB_4K_ASSOC 4 #define L2_ITLB_4K_ENTRIES 512 =20 -/* CPUID Leaf 0x14 constants: */ -#define INTEL_PT_MAX_SUBLEAF 0x1 -/* - * bit[00]: IA32_RTIT_CTL.CR3 filter can be set to 1 and IA32_RTIT_CR3_MAT= CH - * MSR can be accessed; - * bit[01]: Support Configurable PSB and Cycle-Accurate Mode; - * bit[02]: Support IP Filtering, TraceStop filtering, and preservation - * of Intel PT MSRs across warm reset; - * bit[03]: Support MTC timing packet and suppression of COFI-based packet= s; - */ -#define INTEL_PT_MINIMAL_EBX 0xf -/* - * bit[00]: Tracing can be enabled with IA32_RTIT_CTL.ToPA =3D 1 and - * IA32_RTIT_OUTPUT_BASE and IA32_RTIT_OUTPUT_MASK_PTRS MSRs can = be - * accessed; - * bit[01]: ToPA tables can hold any number of output entries, up to the - * maximum allowed by the MaskOrTableOffset field of - * IA32_RTIT_OUTPUT_MASK_PTRS; - * bit[02]: Support Single-Range Output scheme; - */ -#define INTEL_PT_MINIMAL_ECX 0x7 -#define INTEL_PT_ADDR_RANGES_NUM 0x2 /* Number of configurable address ran= ges */ -#define INTEL_PT_ADDR_RANGES_NUM_MASK 0x3 -#define INTEL_PT_MTC_BITMAP (0x0249 << 16) /* Support ART(0,3,6,9) */ -#define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ -#define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ - static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3) { @@ -5538,14 +5511,10 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, break; } =20 - if (count =3D=3D 0) { - *eax =3D INTEL_PT_MAX_SUBLEAF; - *ebx =3D INTEL_PT_MINIMAL_EBX; - *ecx =3D INTEL_PT_MINIMAL_ECX; - } else if (count =3D=3D 1) { - *eax =3D INTEL_PT_MTC_BITMAP | INTEL_PT_ADDR_RANGES_NUM; - *ebx =3D INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP; - } + *eax =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x14, count, = R_EAX); + *ebx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x14, count, = R_EBX); + *ecx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x14, count, = R_ECX); + *edx =3D kvm_arch_get_supported_cpuid(cs->kvm_state, 0x14, count, = R_EDX); break; } case 0x40000000: @@ -6262,32 +6231,6 @@ static void x86_cpu_filter_features(X86CPU *cpu, boo= l verbose) uint64_t unavailable_features =3D requested_features & ~host_feat; mark_unavailable_features(cpu, w, unavailable_features, prefix); } - - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && - kvm_enabled()) { - KVMState *s =3D CPU(cpu)->kvm_state; - uint32_t eax_0 =3D kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EAX); - uint32_t ebx_0 =3D kvm_arch_get_supported_cpuid(s, 0x14, 0, R_EBX); - uint32_t ecx_0 =3D kvm_arch_get_supported_cpuid(s, 0x14, 0, R_ECX); - uint32_t eax_1 =3D kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EAX); - uint32_t ebx_1 =3D kvm_arch_get_supported_cpuid(s, 0x14, 1, R_EBX); - - if (!eax_0 || - ((ebx_0 & INTEL_PT_MINIMAL_EBX) !=3D INTEL_PT_MINIMAL_EBX) || - ((ecx_0 & INTEL_PT_MINIMAL_ECX) !=3D INTEL_PT_MINIMAL_ECX) || - ((eax_1 & INTEL_PT_MTC_BITMAP) !=3D INTEL_PT_MTC_BITMAP) || - ((eax_1 & INTEL_PT_ADDR_RANGES_NUM_MASK) < - INTEL_PT_ADDR_RANGES_NUM) || - ((ebx_1 & (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP)) !=3D - (INTEL_PT_PSB_BITMAP | INTEL_PT_CYCLE_BITMAP))) { - /* - * Processor Trace capabilities aren't configurable, so if the - * host can't emulate the capabilities we report on - * cpu_x86_cpuid(), intel-pt can't be enabled on the current h= ost. - */ - mark_unavailable_features(cpu, FEAT_7_0_EBX, CPUID_7_0_EBX_INT= EL_PT, prefix); - } - } } =20 static void x86_cpu_realizefn(DeviceState *dev, Error **errp) --=20 1.8.3.1