From nobody Mon Oct 13 23:16:44 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1582358748; cv=none; d=zohomail.com; s=zohoarc; b=GrH14BtVQlFneANY3rUXi302oQWGQPyCo7QvlEnYxrJ1UMEW5HnWFHAYxcr+X5W7/6JOAgStA/clQ0UxVK511wF/3fInpTRF/WzRMpaI9Cb1zCXsx59HZeyoy9wIrVy+JCDpPL8C1muTsuq1f+ZzINd+kx2GsDBAGLG2uiEmc0I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1582358748; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=1l4Pv0Rp0EqqSYVjXnr6dFR810kVASgE/zc5sPvXESA=; b=YEL4BPPR51z5VKUe7SLfFJrD9zRDoayZdjYj4YhQqxNCv3mpf39yWYem54k0Z3ioq0d6xt7PyZhYTmM059IxI1TUrU4tQ02yo1LP3bjA6Im2P3hFvQ9WWQWv8K+mbNW5gErTgZrxdC8MBFuGz0oczvdYGu7dbQTrJLdvbFzbGvA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1582358748545713.7217739135159; Sat, 22 Feb 2020 00:05:48 -0800 (PST) Received: from localhost ([::1]:39932 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5PnH-0007OT-IP for importer@patchew.org; Sat, 22 Feb 2020 03:05:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:57676) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j5Pjy-0002Sn-UL for qemu-devel@nongnu.org; Sat, 22 Feb 2020 03:02:24 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j5Pjw-0008CU-P0 for qemu-devel@nongnu.org; Sat, 22 Feb 2020 03:02:22 -0500 Received: from mga12.intel.com ([192.55.52.136]:36228) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j5Pju-0007zv-Vs for qemu-devel@nongnu.org; Sat, 22 Feb 2020 03:02:20 -0500 Received: from orsmga006.jf.intel.com ([10.7.209.51]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Feb 2020 00:01:58 -0800 Received: from jacob-builder.jf.intel.com ([10.7.199.155]) by orsmga006.jf.intel.com with ESMTP; 22 Feb 2020 00:01:57 -0800 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.70,471,1574150400"; d="scan'208";a="240547699" From: Liu Yi L To: qemu-devel@nongnu.org, alex.williamson@redhat.com, peterx@redhat.com Subject: [RFC v3.1 16/22] intel_iommu: replay pasid binds after context cache invalidation Date: Sat, 22 Feb 2020 00:07:17 -0800 Message-Id: <1582358843-51931-17-git-send-email-yi.l.liu@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1582358843-51931-1-git-send-email-yi.l.liu@intel.com> References: <1582358843-51931-1-git-send-email-yi.l.liu@intel.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 192.55.52.136 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kevin.tian@intel.com, yi.l.liu@intel.com, Yi Sun , Eduardo Habkost , kvm@vger.kernel.org, mst@redhat.com, jun.j.tian@intel.com, eric.auger@redhat.com, yi.y.sun@intel.com, Jacob Pan , pbonzini@redhat.com, Richard Henderson , david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" This patch replays guest pasid bindings after context cache invalidation. This is a behavior to ensure safety. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing a context cache invalidation. Cc: Kevin Tian Cc: Jacob Pan Cc: Peter Xu Cc: Yi Sun Cc: Paolo Bonzini Cc: Richard Henderson Cc: Eduardo Habkost Signed-off-by: Liu Yi L --- hw/i386/intel_iommu.c | 67 ++++++++++++++++++++++++++++++++++++++= ++++ hw/i386/intel_iommu_internal.h | 6 +++- hw/i386/trace-events | 1 + 3 files changed, 73 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e7c9677..b85aad3 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -70,6 +70,10 @@ static void vtd_address_space_unmap(VTDAddressSpace *as,= IOMMUNotifier *n); static void vtd_pasid_cache_reset(IntelIOMMUState *s); static int vtd_update_pe_cache_for_dev(IntelIOMMUState *s, VTDBus *vtd_bus, int devfn, int pasid, VTDPASIDEntry *pe); +static void vtd_replay_guest_pasid_bindings(IntelIOMMUState *s, + uint16_t *did, bool is_dsi); +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + VTDBus *vtd_bus, uint16_t devfn); =20 static void vtd_panic_require_caching_mode(void) { @@ -1865,6 +1869,8 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + + vtd_replay_guest_pasid_bindings(s, NULL, false); } =20 static int vtd_bind_guest_pasid(IntelIOMMUState *s, VTDBus *vtd_bus, @@ -1991,6 +1997,22 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_sync_shadow_page_table(vtd_as); + /* + * Per spec, context flush should also followed with PASID + * cache and iotlb flush. Regards to a device selective + * context cache invalidation: + * if (emaulted_device) + * modify the pasid cache gen and pasid-based iotlb gen + * value (will be added in following patches) + * else if (assigned_device) + * check if the device has been bound to any pasid + * invoke pasid_unbind regards to each bound pasid + * Here, we have vtd_pasid_cache_devsi() to invalidate pas= id + * caches, while for piotlb in QEMU, we don't have it yet,= so + * no handling. For assigned device, host iommu driver wou= ld + * flush piotlb when a pasid unbind is pass down to it. + */ + vtd_pasid_cache_devsi(s, vtd_bus, devfn_it); } } } @@ -2586,6 +2608,12 @@ static gboolean vtd_flush_pasid(gpointer key, gpoint= er value, /* Fall through */ case VTD_PASID_CACHE_GLOBAL: break; + case VTD_PASID_CACHE_DEVSI: + if (pc_info->vtd_bus !=3D vtd_bus || + pc_info->devfn =3D=3D devfn) { + return false; + } + break; default: error_report("invalid pc_info->flags"); abort(); @@ -2995,6 +3023,45 @@ static int vtd_pasid_cache_psi(IntelIOMMUState *s, return 0; } =20 +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + VTDBus *vtd_bus, uint16_t devfn) +{ + VTDPASIDCacheInfo pc_info; + VTDContextEntry ce; + PCIDevice *dev; + vtd_pasid_table_walk_info info; + + trace_vtd_pasid_cache_devsi(devfn); + + pc_info.flags =3D VTD_PASID_CACHE_DEVSI; + pc_info.vtd_bus =3D vtd_bus; + pc_info.devfn =3D devfn; + + vtd_iommu_lock(s); + g_hash_table_foreach_remove(s->vtd_pasid_as, vtd_flush_pasid, &pc_info= ); + vtd_iommu_unlock(s); + + /* + * To be safe, after invalidating the pasid caches, + * emulator needs to replay the pasid bindings by + * walking guest pasid dir and pasid table. + */ + dev =3D vtd_bus->bus->devices[devfn]; + if (pci_device_host_iommu_context(dev) && + !vtd_dev_to_context_entry(s, pci_bus_num(vtd_bus->bus), + devfn, &ce)) { + info.flags =3D 0x0; + info.did =3D 0; + info.vtd_bus =3D vtd_bus; + info.devfn =3D devfn; + vtd_sm_pasid_table_walk(s, + VTD_CE_GET_PASID_DIR_TABLE(&ce), + 0, + VTD_MAX_HPASID, + &info); + } +} + /** * Caller of this function should hold iommu_lock */ diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 46cec5c..d427895 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -500,13 +500,17 @@ struct VTDPASIDCacheInfo { #define VTD_PASID_CACHE_GLOBAL (1ULL << 0) #define VTD_PASID_CACHE_DOMSI (1ULL << 1) #define VTD_PASID_CACHE_PASIDSI (1ULL << 2) +#define VTD_PASID_CACHE_DEVSI (1ULL << 3) uint32_t flags; uint16_t domain_id; uint32_t pasid; + VTDBus *vtd_bus; + uint16_t devfn; }; #define VTD_PASID_CACHE_INFO_MASK (VTD_PASID_CACHE_GLOBAL | \ VTD_PASID_CACHE_DOMSI | \ - VTD_PASID_CACHE_PASIDSI) + VTD_PASID_CACHE_PASIDSI | \ + VTD_PASID_CACHE_DEVSI) typedef struct VTDPASIDCacheInfo VTDPASIDCacheInfo; =20 /* Masks for struct VTDRootEntry */ diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 87364a3..34bab09 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -26,6 +26,7 @@ vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domian slective PC invalidation doma= in 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID slective PC in= validation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint16_t devfn) "Dev selective PC invalidation dev: = 0x%"PRIx16 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.7.4