From nobody Tue Feb 10 02:42:41 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925767477572.8221972447736; Sun, 16 Feb 2020 23:49:27 -0800 (PST) Received: from localhost ([::1]:41544 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b9h-0008Ej-UJ for importer@patchew.org; Mon, 17 Feb 2020 02:49:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39541) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b34-0004XH-Ei for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:38 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b30-0000dc-Gr for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:34 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3226 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2q-0000J9-FC; Mon, 17 Feb 2020 02:42:21 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 58A696934A672177F717; Mon, 17 Feb 2020 15:42:14 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:04 +0800 From: Xu Yandong To: Subject: [PATCH RFC 03/16] hw/arm: move shared memmap member to ArmMachine Date: Mon, 17 Feb 2020 02:51:15 -0500 Message-ID: <1581925888-103620-4-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, "Michael S. Tsirkin" , Xu Yandong , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Igor Mammedov , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move memmap member from VirtMachineState to ArmMachineState. Cc: Michael S. Tsirkin Cc: Igor Mammedov Cc: Shannon Zhao Signed-off-by: Xu Yandong --- hw/arm/virt-acpi-build.c | 21 +++-- hw/arm/virt.c | 178 ++++++++++++++++++++------------------- include/hw/arm/arm.h | 1 + include/hw/arm/virt.h | 4 +- 4 files changed, 110 insertions(+), 94 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bd5f771e9b..ef61a651c1 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -43,6 +43,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" +#include "hw/arm/arm.h" #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "sysemu/reset.h" @@ -383,6 +384,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) AcpiIortSmmu3 *smmu; size_t node_size, iort_node_offset, iort_length, smmu_offset =3D 0; AcpiIortRC *rc; + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 iort =3D acpi_data_push(table_data, sizeof(*iort)); =20 @@ -424,7 +426,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) smmu->length =3D cpu_to_le16(node_size); smmu->mapping_count =3D cpu_to_le32(1); smmu->mapping_offset =3D cpu_to_le32(sizeof(*smmu)); - smmu->base_address =3D cpu_to_le64(vms->memmap[VIRT_SMMU].base); + smmu->base_address =3D cpu_to_le64(ams->memmap[VIRT_SMMU].base); smmu->flags =3D cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); smmu->event_gsiv =3D cpu_to_le32(irq); smmu->pri_gsiv =3D cpu_to_le32(irq + 1); @@ -484,7 +486,8 @@ static void build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { AcpiSerialPortConsoleRedirection *spcr; - const MemMapEntry *uart_memmap =3D &vms->memmap[VIRT_UART]; + ArmMachineState *ams =3D ARM_MACHINE(vms); + const MemMapEntry *uart_memmap =3D &ams->memmap[VIRT_UART]; int irq =3D vms->irqmap[VIRT_UART] + ARM_SPI_BASE; int spcr_start =3D table_data->len; =20 @@ -524,6 +527,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) uint64_t mem_base; MachineClass *mc =3D MACHINE_GET_CLASS(vms); MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); const CPUArchIdList *cpu_list =3D mc->possible_cpu_arch_ids(ms); =20 srat_start =3D table_data->len; @@ -539,7 +543,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) core->flags =3D cpu_to_le32(1); } =20 - mem_base =3D vms->memmap[VIRT_MEM].base; + mem_base =3D ams->memmap[VIRT_MEM].base; for (i =3D 0; i < ms->numa_state->num_nodes; ++i) { if (ms->numa_state->nodes[i].node_mem > 0) { numamem =3D acpi_data_push(table_data, sizeof(*numamem)); @@ -602,8 +606,9 @@ static void build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); int madt_start =3D table_data->len; - const MemMapEntry *memmap =3D vms->memmap; + const MemMapEntry *memmap =3D ams->memmap; const int *irqmap =3D vms->irqmap; AcpiMultipleApicTable *madt; AcpiMadtGenericDistributor *gicd; @@ -723,7 +728,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) { Aml *scope, *dsdt; MachineState *ms =3D MACHINE(vms); - const MemMapEntry *memmap =3D vms->memmap; + ArmMachineState *ams =3D ARM_MACHINE(vms); + const MemMapEntry *memmap =3D ams->memmap; const int *irqmap =3D vms->irqmap; =20 dsdt =3D init_aml_allocator(); @@ -796,6 +802,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) unsigned dsdt, xsdt; GArray *tables_blob =3D tables->table_data; MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 table_offsets =3D g_array_new(false, true /* clear */, sizeof(uint32_t)); @@ -821,8 +828,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { - .base =3D vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, - .size =3D vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, + .base =3D ams->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, + .size =3D ams->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, }; build_mcfg(tables_blob, tables->linker, &mcfg); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 41b2076ce1..1dea640719 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -395,14 +395,14 @@ static void fdt_add_its_gic_node(VirtMachineState *vm= s) =20 vms->msi_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); nodename =3D g_strdup_printf("/intc/its@%" PRIx64, - vms->memmap[VIRT_GIC_ITS].base); + ams->memmap[VIRT_GIC_ITS].base); qemu_fdt_add_subnode(ams->fdt, nodename); qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v3-its"); qemu_fdt_setprop(ams->fdt, nodename, "msi-controller", NULL, 0); qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_ITS].base, - 2, vms->memmap[VIRT_GIC_ITS].size); + 2, ams->memmap[VIRT_GIC_ITS].base, + 2, ams->memmap[VIRT_GIC_ITS].size); qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->msi_phandle); g_free(nodename); } @@ -413,15 +413,15 @@ static void fdt_add_v2m_gic_node(VirtMachineState *vm= s) ArmMachineState *ams =3D ARM_MACHINE(vms); =20 nodename =3D g_strdup_printf("/intc/v2m@%" PRIx64, - vms->memmap[VIRT_GIC_V2M].base); + ams->memmap[VIRT_GIC_V2M].base); vms->msi_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); qemu_fdt_add_subnode(ams->fdt, nodename); qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v2m-frame"); qemu_fdt_setprop(ams->fdt, nodename, "msi-controller", NULL, 0); qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_V2M].base, - 2, vms->memmap[VIRT_GIC_V2M].size); + 2, ams->memmap[VIRT_GIC_V2M].base, + 2, ams->memmap[VIRT_GIC_V2M].size); qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->msi_phandle); g_free(nodename); } @@ -435,7 +435,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) qemu_fdt_setprop_cell(ams->fdt, "/", "interrupt-parent", vms->gic_phan= dle); =20 nodename =3D g_strdup_printf("/intc@%" PRIx64, - vms->memmap[VIRT_GIC_DIST].base); + ams->memmap[VIRT_GIC_DIST].base); qemu_fdt_add_subnode(ams->fdt, nodename); qemu_fdt_setprop_cell(ams->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop(ams->fdt, nodename, "interrupt-controller", NULL, 0); @@ -453,18 +453,18 @@ static void fdt_add_gic_node(VirtMachineState *vms) =20 if (nb_redist_regions =3D=3D 1) { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].bas= e, - 2, vms->memmap[VIRT_GIC_DIST].siz= e, - 2, vms->memmap[VIRT_GIC_REDIST].b= ase, - 2, vms->memmap[VIRT_GIC_REDIST].s= ize); + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_REDIST].b= ase, + 2, ams->memmap[VIRT_GIC_REDIST].s= ize); } else { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].base, - 2, vms->memmap[VIRT_GIC_DIST].size, - 2, vms->memmap[VIRT_GIC_REDIST].base, - 2, vms->memmap[VIRT_GIC_REDIST].size, - 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, - 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); + 2, ams->memmap[VIRT_GIC_DIST].base, + 2, ams->memmap[VIRT_GIC_DIST].size, + 2, ams->memmap[VIRT_GIC_REDIST].base, + 2, ams->memmap[VIRT_GIC_REDIST].size, + 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, + 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); } =20 if (vms->virt) { @@ -478,20 +478,20 @@ static void fdt_add_gic_node(VirtMachineState *vms) "arm,cortex-a15-gic"); if (!vms->virt) { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].bas= e, - 2, vms->memmap[VIRT_GIC_DIST].siz= e, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size= ); + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_CPU].base, + 2, ams->memmap[VIRT_GIC_CPU].size= ); } else { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].bas= e, - 2, vms->memmap[VIRT_GIC_DIST].siz= e, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size, - 2, vms->memmap[VIRT_GIC_HYP].base, - 2, vms->memmap[VIRT_GIC_HYP].size, - 2, vms->memmap[VIRT_GIC_VCPU].bas= e, - 2, vms->memmap[VIRT_GIC_VCPU].siz= e); + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_CPU].base, + 2, ams->memmap[VIRT_GIC_CPU].size, + 2, ams->memmap[VIRT_GIC_HYP].base, + 2, ams->memmap[VIRT_GIC_HYP].size, + 2, ams->memmap[VIRT_GIC_VCPU].bas= e, + 2, ams->memmap[VIRT_GIC_VCPU].siz= e); qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, GIC_FDT_IRQ_FLAGS_LEVEL_HI); @@ -543,6 +543,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) { DeviceState *dev; MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); int irq =3D vms->irqmap[VIRT_ACPI_GED]; uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; =20 @@ -553,8 +554,8 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) dev =3D qdev_create(NULL, TYPE_ACPI_GED); qdev_prop_set_uint32(dev, "ged-event", event); =20 - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].bas= e); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].= base); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_ACPI_GED].bas= e); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, ams->memmap[VIRT_PCDIMM_ACPI].= base); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, = irq)); =20 qdev_init_nofail(dev); @@ -564,6 +565,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) =20 static void create_its(VirtMachineState *vms) { + ArmMachineState *ams =3D ARM_MACHINE(vms); const char *itsclass =3D its_class_name(); DeviceState *dev; =20 @@ -577,7 +579,7 @@ static void create_its(VirtMachineState *vms) object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", &error_abort); qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base= ); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_GIC_ITS].base= ); =20 fdt_add_its_gic_node(vms); } @@ -585,11 +587,12 @@ static void create_its(VirtMachineState *vms) static void create_v2m(VirtMachineState *vms) { int i; + ArmMachineState *ams =3D ARM_MACHINE(vms); int irq =3D vms->irqmap[VIRT_GIC_V2M]; DeviceState *dev; =20 dev =3D qdev_create(NULL, "arm-gicv2m"); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base= ); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_GIC_V2M].base= ); qdev_prop_set_uint32(dev, "base-spi", irq); qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); qdev_init_nofail(dev); @@ -605,6 +608,7 @@ static void create_v2m(VirtMachineState *vms) static void create_gic(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); /* We create a standalone GIC */ SysBusDevice *gicbusdev; const char *gictype; @@ -627,7 +631,7 @@ static void create_gic(VirtMachineState *vms) =20 if (type =3D=3D 3) { uint32_t redist0_capacity =3D - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); =20 nb_redist_regions =3D virt_gicv3_redist_region_count(vms); @@ -638,7 +642,7 @@ static void create_gic(VirtMachineState *vms) =20 if (nb_redist_regions =3D=3D 2) { uint32_t redist1_capacity =3D - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; + ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; =20 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); @@ -651,18 +655,18 @@ static void create_gic(VirtMachineState *vms) } qdev_init_nofail(vms->gic); gicbusdev =3D SYS_BUS_DEVICE(vms->gic); - sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); + sysbus_mmio_map(gicbusdev, 0, ams->memmap[VIRT_GIC_DIST].base); if (type =3D=3D 3) { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); + sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_REDIST].base); if (nb_redist_regions =3D=3D 2) { sysbus_mmio_map(gicbusdev, 2, - vms->memmap[VIRT_HIGH_GIC_REDIST2].base); + ams->memmap[VIRT_HIGH_GIC_REDIST2].base); } } else { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_CPU].base); if (vms->virt) { - sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); - sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + sysbus_mmio_map(gicbusdev, 2, ams->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, ams->memmap[VIRT_GIC_VCPU].base); } } =20 @@ -728,8 +732,8 @@ static void create_uart(const VirtMachineState *vms, in= t uart, { char *nodename; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[uart].base; - hwaddr size =3D vms->memmap[uart].size; + hwaddr base =3D ams->memmap[uart].base; + hwaddr size =3D ams->memmap[uart].size; int irq =3D vms->irqmap[uart]; const char compat[] =3D "arm,pl011\0arm,primecell"; const char clocknames[] =3D "uartclk\0apb_pclk"; @@ -776,8 +780,8 @@ static void create_rtc(const VirtMachineState *vms) { char *nodename; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_RTC].base; - hwaddr size =3D vms->memmap[VIRT_RTC].size; + hwaddr base =3D ams->memmap[VIRT_RTC].base; + hwaddr size =3D ams->memmap[VIRT_RTC].size; int irq =3D vms->irqmap[VIRT_RTC]; const char compat[] =3D "arm,pl031\0arm,primecell"; =20 @@ -814,8 +818,8 @@ static void create_gpio(const VirtMachineState *vms) char *nodename; DeviceState *pl061_dev; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_GPIO].base; - hwaddr size =3D vms->memmap[VIRT_GPIO].size; + hwaddr base =3D ams->memmap[VIRT_GPIO].base; + hwaddr size =3D ams->memmap[VIRT_GPIO].size; int irq =3D vms->irqmap[VIRT_GPIO]; const char compat[] =3D "arm,pl061\0arm,primecell"; =20 @@ -858,7 +862,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) { int i; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr size =3D vms->memmap[VIRT_MMIO].size; + hwaddr size =3D ams->memmap[VIRT_MMIO].size; =20 /* We create the transports in forwards order. Since qbus_realize() * prepends (not appends) new child buses, the incrementing loop below= will @@ -889,7 +893,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) */ for (i =3D 0; i < NUM_VIRTIO_TRANSPORTS; i++) { int irq =3D vms->irqmap[VIRT_MMIO] + i; - hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; + hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; =20 sysbus_create_simple("virtio-mmio", base, qdev_get_gpio_in(vms->gic, irq)); @@ -905,7 +909,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) for (i =3D NUM_VIRTIO_TRANSPORTS - 1; i >=3D 0; i--) { char *nodename; int irq =3D vms->irqmap[VIRT_MMIO] + i; - hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; + hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; =20 nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); qemu_fdt_add_subnode(ams->fdt, nodename); @@ -975,6 +979,7 @@ static void virt_flash_map(VirtMachineState *vms, MemoryRegion *sysmem, MemoryRegion *secure_sysmem) { + ArmMachineState *ams =3D ARM_MACHINE(vms); /* * Map two flash devices to fill the VIRT_FLASH space in the memmap. * sysmem is the system memory space. secure_sysmem is the secure view @@ -983,8 +988,8 @@ static void virt_flash_map(VirtMachineState *vms, * If sysmem =3D=3D secure_sysmem this means there is no separate Secu= re * address space and both flash devices are generally visible. */ - hwaddr flashsize =3D vms->memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D vms->memmap[VIRT_FLASH].base; + hwaddr flashsize =3D ams->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D ams->memmap[VIRT_FLASH].base; =20 virt_flash_map1(vms->flash[0], flashbase, flashsize, secure_sysmem); @@ -997,8 +1002,8 @@ static void virt_flash_fdt(VirtMachineState *vms, MemoryRegion *secure_sysmem) { ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr flashsize =3D vms->memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D vms->memmap[VIRT_FLASH].base; + hwaddr flashsize =3D ams->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D ams->memmap[VIRT_FLASH].base; char *nodename; =20 if (sysmem =3D=3D secure_sysmem) { @@ -1088,8 +1093,8 @@ static FWCfgState *create_fw_cfg(const VirtMachineSta= te *vms, AddressSpace *as) { MachineState *ms =3D MACHINE(vms); const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_FW_CFG].base; - hwaddr size =3D vms->memmap[VIRT_FW_CFG].size; + hwaddr base =3D ams->memmap[VIRT_FW_CFG].base; + hwaddr size =3D ams->memmap[VIRT_FW_CFG].size; FWCfgState *fw_cfg; char *nodename; =20 @@ -1152,8 +1157,8 @@ static void create_smmu(const VirtMachineState *vms, const char compat[] =3D "arm,smmu-v3"; int irq =3D vms->irqmap[VIRT_SMMU]; int i; - hwaddr base =3D vms->memmap[VIRT_SMMU].base; - hwaddr size =3D vms->memmap[VIRT_SMMU].size; + hwaddr base =3D ams->memmap[VIRT_SMMU].base; + hwaddr size =3D ams->memmap[VIRT_SMMU].size; const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; DeviceState *dev; =20 @@ -1199,12 +1204,12 @@ static void create_smmu(const VirtMachineState *vms, static void create_pcie(VirtMachineState *vms) { ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base_mmio =3D vms->memmap[VIRT_PCIE_MMIO].base; - hwaddr size_mmio =3D vms->memmap[VIRT_PCIE_MMIO].size; - hwaddr base_mmio_high =3D vms->memmap[VIRT_HIGH_PCIE_MMIO].base; - hwaddr size_mmio_high =3D vms->memmap[VIRT_HIGH_PCIE_MMIO].size; - hwaddr base_pio =3D vms->memmap[VIRT_PCIE_PIO].base; - hwaddr size_pio =3D vms->memmap[VIRT_PCIE_PIO].size; + hwaddr base_mmio =3D ams->memmap[VIRT_PCIE_MMIO].base; + hwaddr size_mmio =3D ams->memmap[VIRT_PCIE_MMIO].size; + hwaddr base_mmio_high =3D ams->memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D ams->memmap[VIRT_HIGH_PCIE_MMIO].size; + hwaddr base_pio =3D ams->memmap[VIRT_PCIE_PIO].base; + hwaddr size_pio =3D ams->memmap[VIRT_PCIE_PIO].size; hwaddr base_ecam, size_ecam; hwaddr base =3D base_mmio; int nr_pcie_buses; @@ -1222,8 +1227,8 @@ static void create_pcie(VirtMachineState *vms) qdev_init_nofail(dev); =20 ecam_id =3D VIRT_ECAM_ID(vms->highmem_ecam); - base_ecam =3D vms->memmap[ecam_id].base; - size_ecam =3D vms->memmap[ecam_id].size; + base_ecam =3D ams->memmap[ecam_id].base; + size_ecam =3D ams->memmap[ecam_id].size; nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; /* Map only the first size_ecam bytes of ECAM space */ ecam_alias =3D g_new0(MemoryRegion, 1); @@ -1333,11 +1338,12 @@ static void create_platform_bus(VirtMachineState *v= ms) SysBusDevice *s; int i; MemoryRegion *sysmem =3D get_system_memory(); + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 dev =3D qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); dev->id =3D TYPE_PLATFORM_BUS_DEVICE; qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); - qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].= size); + qdev_prop_set_uint32(dev, "mmio_size", ams->memmap[VIRT_PLATFORM_BUS].= size); qdev_init_nofail(dev); vms->platform_bus_dev =3D dev; =20 @@ -1348,7 +1354,7 @@ static void create_platform_bus(VirtMachineState *vms) } =20 memory_region_add_subregion(sysmem, - vms->memmap[VIRT_PLATFORM_BUS].base, + ams->memmap[VIRT_PLATFORM_BUS].base, sysbus_mmio_get_region(s, 0)); } =20 @@ -1358,8 +1364,8 @@ static void create_secure_ram(VirtMachineState *vms, MemoryRegion *secram =3D g_new(MemoryRegion, 1); char *nodename; ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_SECURE_MEM].base; - hwaddr size =3D vms->memmap[VIRT_SECURE_MEM].size; + hwaddr base =3D ams->memmap[VIRT_SECURE_MEM].base; + hwaddr size =3D ams->memmap[VIRT_SECURE_MEM].size; =20 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); @@ -1432,8 +1438,8 @@ void virt_machine_done(Notifier *notifier, void *data) */ if (info->dtb_filename =3D=3D NULL) { platform_bus_add_all_fdt_nodes(ams->fdt, "/intc", - vms->memmap[VIRT_PLATFORM_BUS].base, - vms->memmap[VIRT_PLATFORM_BUS].size, + ams->memmap[VIRT_PLATFORM_BUS].base, + ams->memmap[VIRT_PLATFORM_BUS].size, vms->irqmap[VIRT_PLATFORM_BUS]); } if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { @@ -1470,13 +1476,14 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineSta= te *vms, int idx) static void virt_set_memmap(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base, device_memory_base, device_memory_size; int i; =20 - vms->memmap =3D extended_memmap; + ams->memmap =3D extended_memmap; =20 for (i =3D 0; i < ARRAY_SIZE(base_memmap); i++) { - vms->memmap[i] =3D base_memmap[i]; + ams->memmap[i] =3D base_memmap[i]; } =20 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { @@ -1493,7 +1500,7 @@ static void virt_set_memmap(VirtMachineState *vms) * The device region size assumes 1GiB page max alignment per slot. */ device_memory_base =3D - ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); + ROUND_UP(ams->memmap[VIRT_MEM].base + ms->ram_size, GiB); device_memory_size =3D ms->maxram_size - ms->ram_size + ms->ram_slots = * GiB; =20 /* Base address of the high IO region */ @@ -1502,16 +1509,16 @@ static void virt_set_memmap(VirtMachineState *vms) error_report("maxmem/slots too huge"); exit(EXIT_FAILURE); } - if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { - base =3D vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; + if (base < ams->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { + base =3D ams->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; } =20 for (i =3D VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { hwaddr size =3D extended_memmap[i].size; =20 base =3D ROUND_UP(base, size); - vms->memmap[i].base =3D base; - vms->memmap[i].size =3D size; + ams->memmap[i].base =3D base; + ams->memmap[i].size =3D size; base +=3D size; } vms->highest_gpa =3D base - 1; @@ -1526,6 +1533,7 @@ static void virt_set_memmap(VirtMachineState *vms) static void machvirt_init(MachineState *machine) { VirtMachineState *vms =3D VIRT_MACHINE(machine); + ArmMachineState *ams =3D ARM_MACHINE(vms); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(machine); MachineClass *mc =3D MACHINE_GET_CLASS(machine); const CPUArchIdList *possible_cpus; @@ -1543,7 +1551,7 @@ static void machvirt_init(MachineState *machine) * In accelerated mode, the memory map is computed earlier in kvm_type= () * to create a VM with the right number of IPA bits. */ - if (!vms->memmap) { + if (!ams->memmap) { virt_set_memmap(vms); } =20 @@ -1619,9 +1627,9 @@ static void machvirt_init(MachineState *machine) */ if (vms->gic_version =3D=3D 3) { virt_max_cpus =3D - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; virt_max_cpus +=3D - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; } else { virt_max_cpus =3D GIC_NCPU; } @@ -1693,7 +1701,7 @@ static void machvirt_init(MachineState *machine) } =20 if (object_property_find(cpuobj, "reset-cbar", NULL)) { - object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].b= ase, + object_property_set_int(cpuobj, ams->memmap[VIRT_CPUPERIPHS].b= ase, "reset-cbar", &error_abort); } =20 @@ -1728,7 +1736,7 @@ static void machvirt_init(MachineState *machine) =20 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", machine->ram_size); - memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); + memory_region_add_subregion(sysmem, ams->memmap[VIRT_MEM].base, ram); if (machine->device_memory) { memory_region_add_subregion(sysmem, machine->device_memory->base, &machine->device_memory->mr); @@ -1777,7 +1785,7 @@ static void machvirt_init(MachineState *machine) vms->bootinfo.ram_size =3D machine->ram_size; vms->bootinfo.nb_cpus =3D smp_cpus; vms->bootinfo.board_id =3D -1; - vms->bootinfo.loader_start =3D vms->memmap[VIRT_MEM].base; + vms->bootinfo.loader_start =3D ams->memmap[VIRT_MEM].base; vms->bootinfo.get_dtb =3D machvirt_dtb; vms->bootinfo.skip_dtb_autoload =3D true; vms->bootinfo.firmware_loaded =3D firmware_loaded; diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index b3b3daa95a..f269668d41 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -87,6 +87,7 @@ typedef struct { =20 typedef struct { MachineState parent; + MemMapEntry *memmap; void *fdt; int fdt_size; } ArmMachineState; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ad353bad92..1b460d8d31 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -71,7 +71,6 @@ typedef struct { int32_t gic_version; VirtIOMMUType iommu; struct arm_boot_info bootinfo; - MemMapEntry *memmap; const int *irqmap; int smp_cpus; uint32_t clock_phandle; @@ -100,8 +99,9 @@ void virt_acpi_setup(VirtMachineState *vms); /* Return the number of used redistributor regions */ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) { + ArmMachineState *ams =3D ARM_MACHINE(vms); uint32_t redist0_capacity =3D - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; =20 assert(vms->gic_version =3D=3D 3); =20 --=20 2.18.1