From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925761097421.5872208561626; Sun, 16 Feb 2020 23:49:21 -0800 (PST) Received: from localhost ([::1]:41540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b9b-0007xf-J4 for importer@patchew.org; Mon, 17 Feb 2020 02:49:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39447) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b30-0004Mn-3w for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:32 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2x-0000Zq-6j for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:30 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:36472 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2q-0000JB-FC; Mon, 17 Feb 2020 02:42:21 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id EFF76E45A823E766DEB0; Mon, 17 Feb 2020 15:42:13 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:03 +0800 From: Xu Yandong To: Subject: [PATCH RFC 01/16] hw/arm/arm: Introduce ArmMachineState and ArmMachineClass Date: Mon, 17 Feb 2020 02:51:13 -0500 Message-ID: <1581925888-103620-2-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In the following patches, VirtMachineState and VirtMachineClass will splited to and deriving ArmMachineState and ArmMachineClass. This allows sharing code with other arm machine types. Signed-off-by: Xu Yandong --- hw/arm/Makefile.objs | 2 +- hw/arm/arm.c | 77 ++++++++++++++++++++++++++++++++ hw/arm/virt.c | 11 +---- include/hw/arm/arm.h | 100 ++++++++++++++++++++++++++++++++++++++++++ include/hw/arm/virt.h | 61 ++------------------------ 5 files changed, 183 insertions(+), 68 deletions(-) create mode 100644 hw/arm/arm.c create mode 100644 include/hw/arm/arm.h diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 336f6dd374..51fcee2ac8 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -1,6 +1,6 @@ obj-y +=3D boot.o obj-$(CONFIG_PLATFORM_BUS) +=3D sysbus-fdt.o -obj-$(CONFIG_ARM_VIRT) +=3D virt.o +obj-$(CONFIG_ARM_VIRT) +=3D arm.o virt.o obj-$(CONFIG_ACPI) +=3D virt-acpi-build.o obj-$(CONFIG_DIGIC) +=3D digic_boards.o obj-$(CONFIG_EXYNOS4) +=3D exynos4_boards.o diff --git a/hw/arm/arm.c b/hw/arm/arm.c new file mode 100644 index 0000000000..4261d56832 --- /dev/null +++ b/hw/arm/arm.c @@ -0,0 +1,77 @@ +/* + * ARM mach-virt emulation + * Copyright (c) 2013 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + * + * Emulate a virtual board which works by passing Linux all the information + * it needs about what devices are present via the device tree. + * There are some restrictions about what we can do here: + * + we can only present devices whose Linux drivers will work based + * purely on the device tree with no platform data at all + * This is essentially the same approach kvmtool uses. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/arm/arm.h" +#include "sysemu/device_tree.h" +#include "sysemu/numa.h" +#include "hw/loader.h" +#include "exec/address-spaces.h" +#include "qemu/bitops.h" +#include "qemu/error-report.h" +#include "qemu/module.h" +#include "hw/arm/sysbus-fdt.h" +#include "hw/platform-bus.h" +#include "hw/qdev-properties.h" +#include "hw/arm/fdt.h" +#include "hw/intc/arm_gic.h" +#include "kvm_arm.h" + +static void arm_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->block_default_type =3D IF_VIRTIO; + mc->no_cdrom =3D 1; + mc->pci_allow_0_address =3D true; + /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ + mc->minimum_page_bits =3D 12; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); + mc->numa_mem_supported =3D true; + mc->auto_enable_numa_with_memhp =3D true; +} + +static void arm_instance_init(Object *obj) +{ +} + +static const TypeInfo arm_machine_info =3D { + .name =3D TYPE_ARM_MACHINE, + .parent =3D TYPE_MACHINE, + .abstract =3D true, + .instance_size =3D sizeof(ArmMachineState), + .class_size =3D sizeof(ArmMachineClass), + .class_init =3D arm_machine_class_init, + .instance_init =3D arm_instance_init, + .interfaces =3D (InterfaceInfo[]) { + { } + }, +}; + +static void macharm_machine_init(void) +{ + type_register_static(&arm_machine_info); +} +type_init(macharm_machine_init); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f788fe27d6..355007fd32 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -37,6 +37,7 @@ #include "hw/boards.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/arm/arm.h" #include "hw/arm/virt.h" #include "hw/block/flash.h" #include "hw/vfio/vfio-calxeda-xgmac.h" @@ -2041,14 +2042,8 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); - mc->block_default_type =3D IF_VIRTIO; - mc->no_cdrom =3D 1; - mc->pci_allow_0_address =3D true; - /* We know we will never create a pre-ARMv7 CPU which needs 1K pages */ - mc->minimum_page_bits =3D 12; mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; mc->cpu_index_to_instance_props =3D virt_cpu_index_to_props; - mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; assert(!mc->get_hotplug_handler); @@ -2056,8 +2051,6 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) hc->pre_plug =3D virt_machine_device_pre_plug_cb; hc->plug =3D virt_machine_device_plug_cb; hc->unplug_request =3D virt_machine_device_unplug_request_cb; - mc->numa_mem_supported =3D true; - mc->auto_enable_numa_with_memhp =3D true; } =20 static void virt_instance_init(Object *obj) @@ -2133,7 +2126,7 @@ static void virt_instance_init(Object *obj) =20 static const TypeInfo virt_machine_info =3D { .name =3D TYPE_VIRT_MACHINE, - .parent =3D TYPE_MACHINE, + .parent =3D TYPE_ARM_MACHINE, .abstract =3D true, .instance_size =3D sizeof(VirtMachineState), .class_size =3D sizeof(VirtMachineClass), diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h new file mode 100644 index 0000000000..2aa9ee3d05 --- /dev/null +++ b/include/hw/arm/arm.h @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2015 Linaro Limited + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see .* + */ + +#ifndef QEMU_ARM_ARM_H +#define QEMU_ARM_ARM_H + +#include "exec/hwaddr.h" +#include "hw/boards.h" +#include "hw/arm/boot.h" +#include "hw/intc/arm_gicv3_common.h" + +#define NUM_GICV2M_SPIS 64 +#define NUM_VIRTIO_TRANSPORTS 32 +#define NUM_SMMU_IRQS 4 + +#define ARCH_GIC_MAINT_IRQ 9 + +#define ARCH_TIMER_VIRT_IRQ 11 +#define ARCH_TIMER_S_EL1_IRQ 13 +#define ARCH_TIMER_NS_EL1_IRQ 14 +#define ARCH_TIMER_NS_EL2_IRQ 10 + +#define VIRTUAL_PMU_IRQ 7 + +#define PPI(irq) ((irq) + 16) + + +enum { + VIRT_FLASH, + VIRT_MEM, + VIRT_CPUPERIPHS, + VIRT_GIC_DIST, + VIRT_GIC_CPU, + VIRT_GIC_V2M, + VIRT_GIC_HYP, + VIRT_GIC_VCPU, + VIRT_GIC_ITS, + VIRT_GIC_REDIST, + VIRT_SMMU, + VIRT_UART, + VIRT_MMIO, + VIRT_RTC, + VIRT_FW_CFG, + VIRT_PCIE, + VIRT_PCIE_MMIO, + VIRT_PCIE_PIO, + VIRT_PCIE_ECAM, + VIRT_PLATFORM_BUS, + VIRT_GPIO, + VIRT_SECURE_UART, + VIRT_SECURE_MEM, + VIRT_PCDIMM_ACPI, + VIRT_ACPI_GED, + VIRT_LOWMEMMAP_LAST, +}; + +/* indices of IO regions located after the RAM */ +enum { + VIRT_HIGH_GIC_REDIST2 =3D VIRT_LOWMEMMAP_LAST, + VIRT_HIGH_PCIE_ECAM, + VIRT_HIGH_PCIE_MMIO, +}; + +/* indices of IO regions located after the RAM */ + +typedef struct MemMapEntry { + hwaddr base; + hwaddr size; +} MemMapEntry; + +typedef struct { + MachineClass parent; +} ArmMachineClass; + +typedef struct { + MachineState parent; +} ArmMachineState; + +#define TYPE_ARM_MACHINE MACHINE_TYPE_NAME("arm") +#define ARM_MACHINE(obj) \ + OBJECT_CHECK(ArmMachineState, (obj), TYPE_ARM_MACHINE) +#define ARM_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(ArmMachineClass, obj, TYPE_ARM_MACHINE) +#define ARM_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(ArmMachineClass, klass, TYPE_ARM_MACHINE) + +#endif /* QEMU_ARM_ARM_H */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 71508bf40c..aa0cc852a5 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -37,57 +37,7 @@ #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "hw/intc/arm_gicv3_common.h" - -#define NUM_GICV2M_SPIS 64 -#define NUM_VIRTIO_TRANSPORTS 32 -#define NUM_SMMU_IRQS 4 - -#define ARCH_GIC_MAINT_IRQ 9 - -#define ARCH_TIMER_VIRT_IRQ 11 -#define ARCH_TIMER_S_EL1_IRQ 13 -#define ARCH_TIMER_NS_EL1_IRQ 14 -#define ARCH_TIMER_NS_EL2_IRQ 10 - -#define VIRTUAL_PMU_IRQ 7 - -#define PPI(irq) ((irq) + 16) - -enum { - VIRT_FLASH, - VIRT_MEM, - VIRT_CPUPERIPHS, - VIRT_GIC_DIST, - VIRT_GIC_CPU, - VIRT_GIC_V2M, - VIRT_GIC_HYP, - VIRT_GIC_VCPU, - VIRT_GIC_ITS, - VIRT_GIC_REDIST, - VIRT_SMMU, - VIRT_UART, - VIRT_MMIO, - VIRT_RTC, - VIRT_FW_CFG, - VIRT_PCIE, - VIRT_PCIE_MMIO, - VIRT_PCIE_PIO, - VIRT_PCIE_ECAM, - VIRT_PLATFORM_BUS, - VIRT_GPIO, - VIRT_SECURE_UART, - VIRT_SECURE_MEM, - VIRT_PCDIMM_ACPI, - VIRT_ACPI_GED, - VIRT_LOWMEMMAP_LAST, -}; - -/* indices of IO regions located after the RAM */ -enum { - VIRT_HIGH_GIC_REDIST2 =3D VIRT_LOWMEMMAP_LAST, - VIRT_HIGH_PCIE_ECAM, - VIRT_HIGH_PCIE_MMIO, -}; +#include "hw/arm/arm.h" =20 typedef enum VirtIOMMUType { VIRT_IOMMU_NONE, @@ -95,13 +45,8 @@ typedef enum VirtIOMMUType { VIRT_IOMMU_VIRTIO, } VirtIOMMUType; =20 -typedef struct MemMapEntry { - hwaddr base; - hwaddr size; -} MemMapEntry; - typedef struct { - MachineClass parent; + ArmMachineClass parent; bool disallow_affinity_adjustment; bool no_its; bool no_pmu; @@ -113,7 +58,7 @@ typedef struct { } VirtMachineClass; =20 typedef struct { - MachineState parent; + ArmMachineState parent; Notifier machine_done; DeviceState *platform_bus_dev; FWCfgState *fw_cfg; --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925819436272.3901196989002; Sun, 16 Feb 2020 23:50:19 -0800 (PST) Received: from localhost ([::1]:41548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3bAY-0001BZ-1x for importer@patchew.org; Mon, 17 Feb 2020 02:50:18 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39554) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b35-0004ZM-7h for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:39 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b30-0000dr-NJ for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:35 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2791 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2q-0000Ij-F5; Mon, 17 Feb 2020 02:42:21 -0500 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id B16FA629FD86864EA7EF; Mon, 17 Feb 2020 15:42:13 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:04 +0800 From: Xu Yandong To: Subject: [PATCH RFC 02/16] hw/arm: move shared fdt member to ArmMachine Date: Mon, 17 Feb 2020 02:51:14 -0500 Message-ID: <1581925888-103620-3-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move fdt and fdt_size member from VirtMachineState to ArmMachineState. Signed-off-by: Xu Yandong --- hw/arm/virt.c | 303 ++++++++++++++++++++++-------------------- include/hw/arm/arm.h | 2 + include/hw/arm/virt.h | 2 - 3 files changed, 163 insertions(+), 144 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 355007fd32..41b2076ce1 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -211,15 +211,16 @@ static bool cpu_type_valid(const char *cpu) static void create_fdt(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); int nb_numa_nodes =3D ms->numa_state->num_nodes; - void *fdt =3D create_device_tree(&vms->fdt_size); + void *fdt =3D create_device_tree(&ams->fdt_size); =20 if (!fdt) { error_report("create_device_tree() failed"); exit(1); } =20 - vms->fdt =3D fdt; + ams->fdt =3D fdt; =20 /* Header */ qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); @@ -288,6 +289,7 @@ static void fdt_add_timer_nodes(const VirtMachineState = *vms) * the correct information. */ ARMCPU *armcpu; + ArmMachineState *ams =3D ARM_MACHINE(vms); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); uint32_t irqflags =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; =20 @@ -301,19 +303,19 @@ static void fdt_add_timer_nodes(const VirtMachineStat= e *vms) (1 << vms->smp_cpus) - 1); } =20 - qemu_fdt_add_subnode(vms->fdt, "/timer"); + qemu_fdt_add_subnode(ams->fdt, "/timer"); =20 armcpu =3D ARM_CPU(qemu_get_cpu(0)); if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { const char compat[] =3D "arm,armv8-timer\0arm,armv7-timer"; - qemu_fdt_setprop(vms->fdt, "/timer", "compatible", + qemu_fdt_setprop(ams->fdt, "/timer", "compatible", compat, sizeof(compat)); } else { - qemu_fdt_setprop_string(vms->fdt, "/timer", "compatible", + qemu_fdt_setprop_string(ams->fdt, "/timer", "compatible", "arm,armv7-timer"); } - qemu_fdt_setprop(vms->fdt, "/timer", "always-on", NULL, 0); - qemu_fdt_setprop_cells(vms->fdt, "/timer", "interrupts", + qemu_fdt_setprop(ams->fdt, "/timer", "always-on", NULL, 0); + qemu_fdt_setprop_cells(ams->fdt, "/timer", "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflag= s, GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqfla= gs, GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, @@ -325,6 +327,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) int cpu; int addr_cells =3D 1; const MachineState *ms =3D MACHINE(vms); + const ArmMachineState *ams =3D ARM_MACHINE(vms); =20 /* * From Documentation/devicetree/bindings/arm/cpus.txt @@ -348,36 +351,36 @@ static void fdt_add_cpu_nodes(const VirtMachineState = *vms) } } =20 - qemu_fdt_add_subnode(vms->fdt, "/cpus"); - qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#address-cells", addr_cells); - qemu_fdt_setprop_cell(vms->fdt, "/cpus", "#size-cells", 0x0); + qemu_fdt_add_subnode(ams->fdt, "/cpus"); + qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#address-cells", addr_cells); + qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#size-cells", 0x0); =20 for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); CPUState *cs =3D CPU(armcpu); =20 - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "cpu"); - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", armcpu->dtb_compatible); =20 if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED && vms->smp_cpus > 1) { - qemu_fdt_setprop_string(vms->fdt, nodename, + qemu_fdt_setprop_string(ams->fdt, nodename, "enable-method", "psci"); } =20 if (addr_cells =3D=3D 2) { - qemu_fdt_setprop_u64(vms->fdt, nodename, "reg", + qemu_fdt_setprop_u64(ams->fdt, nodename, "reg", armcpu->mp_affinity); } else { - qemu_fdt_setprop_cell(vms->fdt, nodename, "reg", + qemu_fdt_setprop_cell(ams->fdt, nodename, "reg", armcpu->mp_affinity); } =20 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { - qemu_fdt_setprop_cell(vms->fdt, nodename, "numa-node-id", + qemu_fdt_setprop_cell(ams->fdt, nodename, "numa-node-id", ms->possible_cpus->cpus[cs->cpu_index].props.node_id); } =20 @@ -388,71 +391,74 @@ static void fdt_add_cpu_nodes(const VirtMachineState = *vms) static void fdt_add_its_gic_node(VirtMachineState *vms) { char *nodename; + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 - vms->msi_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); + vms->msi_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); nodename =3D g_strdup_printf("/intc/its@%" PRIx64, vms->memmap[VIRT_GIC_ITS].base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v3-its"); - qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop(ams->fdt, nodename, "msi-controller", NULL, 0); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, vms->memmap[VIRT_GIC_ITS].base, 2, vms->memmap[VIRT_GIC_ITS].size); - qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); + qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->msi_phandle); g_free(nodename); } =20 static void fdt_add_v2m_gic_node(VirtMachineState *vms) { char *nodename; + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 nodename =3D g_strdup_printf("/intc/v2m@%" PRIx64, vms->memmap[VIRT_GIC_V2M].base); - vms->msi_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", + vms->msi_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v2m-frame"); - qemu_fdt_setprop(vms->fdt, nodename, "msi-controller", NULL, 0); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop(ams->fdt, nodename, "msi-controller", NULL, 0); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, vms->memmap[VIRT_GIC_V2M].base, 2, vms->memmap[VIRT_GIC_V2M].size); - qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->msi_phandle); + qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->msi_phandle); g_free(nodename); } =20 static void fdt_add_gic_node(VirtMachineState *vms) { char *nodename; + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 - vms->gic_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); - qemu_fdt_setprop_cell(vms->fdt, "/", "interrupt-parent", vms->gic_phan= dle); + vms->gic_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); + qemu_fdt_setprop_cell(ams->fdt, "/", "interrupt-parent", vms->gic_phan= dle); =20 nodename =3D g_strdup_printf("/intc@%" PRIx64, vms->memmap[VIRT_GIC_DIST].base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 3); - qemu_fdt_setprop(vms->fdt, nodename, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 0x2); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 0x2); - qemu_fdt_setprop(vms->fdt, nodename, "ranges", NULL, 0); + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#interrupt-cells", 3); + qemu_fdt_setprop(ams->fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#address-cells", 0x2); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop(ams->fdt, nodename, "ranges", NULL, 0); if (vms->gic_version =3D=3D 3) { int nb_redist_regions =3D virt_gicv3_redist_region_count(vms); =20 - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v3"); =20 - qemu_fdt_setprop_cell(vms->fdt, nodename, + qemu_fdt_setprop_cell(ams->fdt, nodename, "#redistributor-regions", nb_redist_regions); =20 if (nb_redist_regions =3D=3D 1) { - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, vms->memmap[VIRT_GIC_DIST].bas= e, 2, vms->memmap[VIRT_GIC_DIST].siz= e, 2, vms->memmap[VIRT_GIC_REDIST].b= ase, 2, vms->memmap[VIRT_GIC_REDIST].s= ize); } else { - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, vms->memmap[VIRT_GIC_DIST].base, 2, vms->memmap[VIRT_GIC_DIST].size, 2, vms->memmap[VIRT_GIC_REDIST].base, @@ -462,22 +468,22 @@ static void fdt_add_gic_node(VirtMachineState *vms) } =20 if (vms->virt) { - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, GIC_FDT_IRQ_FLAGS_LEVEL_HI); } } else { /* 'cortex-a15-gic' means 'GIC v2' */ - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,cortex-a15-gic"); if (!vms->virt) { - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, vms->memmap[VIRT_GIC_DIST].bas= e, 2, vms->memmap[VIRT_GIC_DIST].siz= e, 2, vms->memmap[VIRT_GIC_CPU].base, 2, vms->memmap[VIRT_GIC_CPU].size= ); } else { - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, vms->memmap[VIRT_GIC_DIST].bas= e, 2, vms->memmap[VIRT_GIC_DIST].siz= e, 2, vms->memmap[VIRT_GIC_CPU].base, @@ -486,13 +492,13 @@ static void fdt_add_gic_node(VirtMachineState *vms) 2, vms->memmap[VIRT_GIC_HYP].size, 2, vms->memmap[VIRT_GIC_VCPU].bas= e, 2, vms->memmap[VIRT_GIC_VCPU].siz= e); - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, GIC_FDT_IRQ_FLAGS_LEVEL_HI); } } =20 - qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle); + qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->gic_phandle); g_free(nodename); } =20 @@ -500,6 +506,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *v= ms) { CPUState *cpu; ARMCPU *armcpu; + const ArmMachineState *ams =3D ARM_MACHINE(vms); uint32_t irqflags =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; =20 CPU_FOREACH(cpu) { @@ -522,12 +529,12 @@ static void fdt_add_pmu_nodes(const VirtMachineState = *vms) } =20 armcpu =3D ARM_CPU(qemu_get_cpu(0)); - qemu_fdt_add_subnode(vms->fdt, "/pmu"); + qemu_fdt_add_subnode(ams->fdt, "/pmu"); if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { const char compat[] =3D "arm,armv8-pmuv3"; - qemu_fdt_setprop(vms->fdt, "/pmu", "compatible", + qemu_fdt_setprop(ams->fdt, "/pmu", "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_cells(vms->fdt, "/pmu", "interrupts", + qemu_fdt_setprop_cells(ams->fdt, "/pmu", "interrupts", GIC_FDT_IRQ_TYPE_PPI, VIRTUAL_PMU_IRQ, irqf= lags); } } @@ -720,6 +727,7 @@ static void create_uart(const VirtMachineState *vms, in= t uart, MemoryRegion *mem, Chardev *chr) { char *nodename; + const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D vms->memmap[uart].base; hwaddr size =3D vms->memmap[uart].size; int irq =3D vms->irqmap[uart]; @@ -735,29 +743,29 @@ static void create_uart(const VirtMachineState *vms, = int uart, sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); =20 nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); + qemu_fdt_add_subnode(ams->fdt, nodename); /* Note that we can't use setprop_string because of the embedded NUL */ - qemu_fdt_setprop(vms->fdt, nodename, "compatible", + qemu_fdt_setprop(ams->fdt, nodename, "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cells(vms->fdt, nodename, "clocks", + qemu_fdt_setprop_cells(ams->fdt, nodename, "clocks", vms->clock_phandle, vms->clock_phandle); - qemu_fdt_setprop(vms->fdt, nodename, "clock-names", + qemu_fdt_setprop(ams->fdt, nodename, "clock-names", clocknames, sizeof(clocknames)); =20 if (uart =3D=3D VIRT_UART) { - qemu_fdt_setprop_string(vms->fdt, "/chosen", "stdout-path", nodena= me); + qemu_fdt_setprop_string(ams->fdt, "/chosen", "stdout-path", nodena= me); } else { /* Mark as not usable by the normal world */ - qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); - qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay= "); + qemu_fdt_setprop_string(ams->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(ams->fdt, nodename, "secure-status", "okay= "); =20 - qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); - qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", + qemu_fdt_add_subnode(ams->fdt, "/secure-chosen"); + qemu_fdt_setprop_string(ams->fdt, "/secure-chosen", "stdout-path", nodename); } =20 @@ -767,6 +775,7 @@ static void create_uart(const VirtMachineState *vms, in= t uart, static void create_rtc(const VirtMachineState *vms) { char *nodename; + const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D vms->memmap[VIRT_RTC].base; hwaddr size =3D vms->memmap[VIRT_RTC].size; int irq =3D vms->irqmap[VIRT_RTC]; @@ -775,15 +784,15 @@ static void create_rtc(const VirtMachineState *vms) sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); =20 nodename =3D g_strdup_printf("/pl031@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(comp= at)); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop(ams->fdt, nodename, "compatible", compat, sizeof(comp= at)); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle= ); - qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); + qemu_fdt_setprop_cell(ams->fdt, nodename, "clocks", vms->clock_phandle= ); + qemu_fdt_setprop_string(ams->fdt, nodename, "clock-names", "apb_pclk"); g_free(nodename); } =20 @@ -804,6 +813,7 @@ static void create_gpio(const VirtMachineState *vms) { char *nodename; DeviceState *pl061_dev; + const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D vms->memmap[VIRT_GPIO].base; hwaddr size =3D vms->memmap[VIRT_GPIO].size; int irq =3D vms->irqmap[VIRT_GPIO]; @@ -812,34 +822,34 @@ static void create_gpio(const VirtMachineState *vms) pl061_dev =3D sysbus_create_simple("pl061", base, qdev_get_gpio_in(vms->gic, irq)); =20 - uint32_t phandle =3D qemu_fdt_alloc_phandle(vms->fdt); + uint32_t phandle =3D qemu_fdt_alloc_phandle(ams->fdt); nodename =3D g_strdup_printf("/pl061@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(vms->fdt, nodename, "compatible", compat, sizeof(comp= at)); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#gpio-cells", 2); - qemu_fdt_setprop(vms->fdt, nodename, "gpio-controller", NULL, 0); - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + qemu_fdt_setprop(ams->fdt, nodename, "compatible", compat, sizeof(comp= at)); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#gpio-cells", 2); + qemu_fdt_setprop(ams->fdt, nodename, "gpio-controller", NULL, 0); + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cell(vms->fdt, nodename, "clocks", vms->clock_phandle= ); - qemu_fdt_setprop_string(vms->fdt, nodename, "clock-names", "apb_pclk"); - qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", phandle); + qemu_fdt_setprop_cell(ams->fdt, nodename, "clocks", vms->clock_phandle= ); + qemu_fdt_setprop_string(ams->fdt, nodename, "clock-names", "apb_pclk"); + qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", phandle); =20 gpio_key_dev =3D sysbus_create_simple("gpio-key", -1, qdev_get_gpio_in(pl061_dev, 3)); - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys", "compatible", "gpio-ke= ys"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#size-cells", 0); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys", "#address-cells", 1); + qemu_fdt_add_subnode(ams->fdt, "/gpio-keys"); + qemu_fdt_setprop_string(ams->fdt, "/gpio-keys", "compatible", "gpio-ke= ys"); + qemu_fdt_setprop_cell(ams->fdt, "/gpio-keys", "#size-cells", 0); + qemu_fdt_setprop_cell(ams->fdt, "/gpio-keys", "#address-cells", 1); =20 - qemu_fdt_add_subnode(vms->fdt, "/gpio-keys/poweroff"); - qemu_fdt_setprop_string(vms->fdt, "/gpio-keys/poweroff", + qemu_fdt_add_subnode(ams->fdt, "/gpio-keys/poweroff"); + qemu_fdt_setprop_string(ams->fdt, "/gpio-keys/poweroff", "label", "GPIO Key Poweroff"); - qemu_fdt_setprop_cell(vms->fdt, "/gpio-keys/poweroff", "linux,code", + qemu_fdt_setprop_cell(ams->fdt, "/gpio-keys/poweroff", "linux,code", KEY_POWER); - qemu_fdt_setprop_cells(vms->fdt, "/gpio-keys/poweroff", + qemu_fdt_setprop_cells(ams->fdt, "/gpio-keys/poweroff", "gpios", phandle, 3, 0); g_free(nodename); } @@ -847,6 +857,7 @@ static void create_gpio(const VirtMachineState *vms) static void create_virtio_devices(const VirtMachineState *vms) { int i; + const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr size =3D vms->memmap[VIRT_MMIO].size; =20 /* We create the transports in forwards order. Since qbus_realize() @@ -897,15 +908,15 @@ static void create_virtio_devices(const VirtMachineSt= ate *vms) hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; =20 nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "virtio,mmio"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts", + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); - qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ams->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); } } @@ -985,6 +996,7 @@ static void virt_flash_fdt(VirtMachineState *vms, MemoryRegion *sysmem, MemoryRegion *secure_sysmem) { + ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr flashsize =3D vms->memmap[VIRT_FLASH].size / 2; hwaddr flashbase =3D vms->memmap[VIRT_FLASH].base; char *nodename; @@ -992,12 +1004,12 @@ static void virt_flash_fdt(VirtMachineState *vms, if (sysmem =3D=3D secure_sysmem) { /* Report both flash devices as a single node in the DT */ nodename =3D g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-fla= sh"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "cfi-fla= sh"); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, flashbase, 2, flashsize, 2, flashbase + flashsize, 2, flashsiz= e); - qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); + qemu_fdt_setprop_cell(ams->fdt, nodename, "bank-width", 4); g_free(nodename); } else { /* @@ -1005,21 +1017,21 @@ static void virt_flash_fdt(VirtMachineState *vms, * only visible to the secure world. */ nodename =3D g_strdup_printf("/secflash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-fla= sh"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "cfi-fla= sh"); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, flashbase, 2, flashsize); - qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); - qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); - qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay= "); + qemu_fdt_setprop_cell(ams->fdt, nodename, "bank-width", 4); + qemu_fdt_setprop_string(ams->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(ams->fdt, nodename, "secure-status", "okay= "); g_free(nodename); =20 nodename =3D g_strdup_printf("/flash@%" PRIx64, flashbase); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "compatible", "cfi-fla= sh"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "cfi-fla= sh"); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, flashbase + flashsize, 2, flashsiz= e); - qemu_fdt_setprop_cell(vms->fdt, nodename, "bank-width", 4); + qemu_fdt_setprop_cell(ams->fdt, nodename, "bank-width", 4); g_free(nodename); } } @@ -1075,6 +1087,7 @@ static bool virt_firmware_init(VirtMachineState *vms, static FWCfgState *create_fw_cfg(const VirtMachineState *vms, AddressSpace= *as) { MachineState *ms =3D MACHINE(vms); + const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D vms->memmap[VIRT_FW_CFG].base; hwaddr size =3D vms->memmap[VIRT_FW_CFG].size; FWCfgState *fw_cfg; @@ -1084,12 +1097,12 @@ static FWCfgState *create_fw_cfg(const VirtMachineS= tate *vms, AddressSpace *as) fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)ms->smp.cpus); =20 nodename =3D g_strdup_printf("/fw-cfg@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "qemu,fw-cfg-mmio"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, base, 2, size); - qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ams->fdt, nodename, "dma-coherent", NULL, 0); g_free(nodename); return fw_cfg; } @@ -1101,6 +1114,7 @@ static void create_pcie_irq_map(const VirtMachineStat= e *vms, int devfn, pin; uint32_t full_irq_map[4 * 4 * 10] =3D { 0 }; uint32_t *irq_map =3D full_irq_map; + const ArmMachineState *ams =3D ARM_MACHINE(vms); =20 for (devfn =3D 0; devfn <=3D 0x18; devfn +=3D 0x8) { for (pin =3D 0; pin < 4; pin++) { @@ -1122,10 +1136,10 @@ static void create_pcie_irq_map(const VirtMachineSt= ate *vms, } } =20 - qemu_fdt_setprop(vms->fdt, nodename, "interrupt-map", + qemu_fdt_setprop(ams->fdt, nodename, "interrupt-map", full_irq_map, sizeof(full_irq_map)); =20 - qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupt-map-mask", + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupt-map-mask", 0x1800, 0, 0, /* devfn (PCI_SLOT(3)) */ 0x7 /* PCI irq */); } @@ -1134,6 +1148,7 @@ static void create_smmu(const VirtMachineState *vms, PCIBus *bus) { char *node; + const ArmMachineState *ams =3D ARM_MACHINE(vms); const char compat[] =3D "arm,smmu-v3"; int irq =3D vms->irqmap[VIRT_SMMU]; int i; @@ -1158,31 +1173,32 @@ static void create_smmu(const VirtMachineState *vms, } =20 node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, node); - qemu_fdt_setprop(vms->fdt, node, "compatible", compat, sizeof(compat)); - qemu_fdt_setprop_sized_cells(vms->fdt, node, "reg", 2, base, 2, size); + qemu_fdt_add_subnode(ams->fdt, node); + qemu_fdt_setprop(ams->fdt, node, "compatible", compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(ams->fdt, node, "reg", 2, base, 2, size); =20 - qemu_fdt_setprop_cells(vms->fdt, node, "interrupts", + qemu_fdt_setprop_cells(ams->fdt, node, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irq , GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, GIC_FDT_IRQ_TYPE_SPI, irq + 1, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, GIC_FDT_IRQ_TYPE_SPI, irq + 2, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI, GIC_FDT_IRQ_TYPE_SPI, irq + 3, GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); =20 - qemu_fdt_setprop(vms->fdt, node, "interrupt-names", irq_names, + qemu_fdt_setprop(ams->fdt, node, "interrupt-names", irq_names, sizeof(irq_names)); =20 - qemu_fdt_setprop_cell(vms->fdt, node, "clocks", vms->clock_phandle); - qemu_fdt_setprop_string(vms->fdt, node, "clock-names", "apb_pclk"); - qemu_fdt_setprop(vms->fdt, node, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cell(ams->fdt, node, "clocks", vms->clock_phandle); + qemu_fdt_setprop_string(ams->fdt, node, "clock-names", "apb_pclk"); + qemu_fdt_setprop(ams->fdt, node, "dma-coherent", NULL, 0); =20 - qemu_fdt_setprop_cell(vms->fdt, node, "#iommu-cells", 1); + qemu_fdt_setprop_cell(ams->fdt, node, "#iommu-cells", 1); =20 - qemu_fdt_setprop_cell(vms->fdt, node, "phandle", vms->iommu_phandle); + qemu_fdt_setprop_cell(ams->fdt, node, "phandle", vms->iommu_phandle); g_free(node); } =20 static void create_pcie(VirtMachineState *vms) { + ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base_mmio =3D vms->memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio =3D vms->memmap[VIRT_PCIE_MMIO].size; hwaddr base_mmio_high =3D vms->memmap[VIRT_HIGH_PCIE_MMIO].base; @@ -1260,27 +1276,27 @@ static void create_pcie(VirtMachineState *vms) } =20 nodename =3D g_strdup_printf("/pcie@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "pci-host-ecam-generic"); - qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "pci"); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#address-cells", 3); - qemu_fdt_setprop_cell(vms->fdt, nodename, "#size-cells", 2); - qemu_fdt_setprop_cell(vms->fdt, nodename, "linux,pci-domain", 0); - qemu_fdt_setprop_cells(vms->fdt, nodename, "bus-range", 0, + qemu_fdt_setprop_string(ams->fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#address-cells", 3); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#size-cells", 2); + qemu_fdt_setprop_cell(ams->fdt, nodename, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(ams->fdt, nodename, "bus-range", 0, nr_pcie_buses - 1); - qemu_fdt_setprop(vms->fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop(ams->fdt, nodename, "dma-coherent", NULL, 0); =20 if (vms->msi_phandle) { - qemu_fdt_setprop_cells(vms->fdt, nodename, "msi-parent", + qemu_fdt_setprop_cells(ams->fdt, nodename, "msi-parent", vms->msi_phandle); } =20 - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, base_ecam, 2, size_ecam); =20 if (vms->highmem) { - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, base_pio, 2, size_pio, 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, @@ -1289,22 +1305,22 @@ static void create_pcie(VirtMachineState *vms) 2, base_mmio_high, 2, base_mmio_high, 2, size_mmio_high); } else { - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "ranges", + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "ranges", 1, FDT_PCI_RANGE_IOPORT, 2, 0, 2, base_pio, 2, size_pio, 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 2, base_mmio, 2, size_mmio); } =20 - qemu_fdt_setprop_cell(vms->fdt, nodename, "#interrupt-cells", 1); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#interrupt-cells", 1); create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); =20 if (vms->iommu) { - vms->iommu_phandle =3D qemu_fdt_alloc_phandle(vms->fdt); + vms->iommu_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); =20 create_smmu(vms, pci->bus); =20 - qemu_fdt_setprop_cells(vms->fdt, nodename, "iommu-map", + qemu_fdt_setprop_cells(ams->fdt, nodename, "iommu-map", 0x0, vms->iommu_phandle, 0x0, 0x10000); } =20 @@ -1341,6 +1357,7 @@ static void create_secure_ram(VirtMachineState *vms, { MemoryRegion *secram =3D g_new(MemoryRegion, 1); char *nodename; + ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D vms->memmap[VIRT_SECURE_MEM].base; hwaddr size =3D vms->memmap[VIRT_SECURE_MEM].size; =20 @@ -1349,20 +1366,21 @@ static void create_secure_ram(VirtMachineState *vms, memory_region_add_subregion(secure_sysmem, base, secram); =20 nodename =3D g_strdup_printf("/secram@%" PRIx64, base); - qemu_fdt_add_subnode(vms->fdt, nodename); - qemu_fdt_setprop_string(vms->fdt, nodename, "device_type", "memory"); - qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg", 2, base, 2, si= ze); - qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); - qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay"); + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "device_type", "memory"); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", 2, base, 2, si= ze); + qemu_fdt_setprop_string(ams->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(ams->fdt, nodename, "secure-status", "okay"); =20 g_free(nodename); } =20 static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) { - const VirtMachineState *board =3D container_of(binfo, VirtMachineState, + const VirtMachineState *vms =3D container_of(binfo, VirtMachineState, bootinfo); =20 + ArmMachineState *board =3D ARM_MACHINE(vms); *fdt_size =3D board->fdt_size; return board->fdt; } @@ -1400,6 +1418,7 @@ void virt_machine_done(Notifier *notifier, void *data) VirtMachineState *vms =3D container_of(notifier, VirtMachineState, machine_done); MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); ARMCPU *cpu =3D ARM_CPU(first_cpu); struct arm_boot_info *info =3D &vms->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); @@ -1412,7 +1431,7 @@ void virt_machine_done(Notifier *notifier, void *data) * while qemu takes charge of the qom stuff. */ if (info->dtb_filename =3D=3D NULL) { - platform_bus_add_all_fdt_nodes(vms->fdt, "/intc", + platform_bus_add_all_fdt_nodes(ams->fdt, "/intc", vms->memmap[VIRT_PLATFORM_BUS].base, vms->memmap[VIRT_PLATFORM_BUS].size, vms->irqmap[VIRT_PLATFORM_BUS]); diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 2aa9ee3d05..b3b3daa95a 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -87,6 +87,8 @@ typedef struct { =20 typedef struct { MachineState parent; + void *fdt; + int fdt_size; } ArmMachineState; =20 #define TYPE_ARM_MACHINE MACHINE_TYPE_NAME("arm") diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index aa0cc852a5..ad353bad92 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -74,8 +74,6 @@ typedef struct { MemMapEntry *memmap; const int *irqmap; int smp_cpus; - void *fdt; - int fdt_size; uint32_t clock_phandle; uint32_t gic_phandle; uint32_t msi_phandle; --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925767477572.8221972447736; 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Mon, 17 Feb 2020 15:42:04 +0800 From: Xu Yandong To: Subject: [PATCH RFC 03/16] hw/arm: move shared memmap member to ArmMachine Date: Mon, 17 Feb 2020 02:51:15 -0500 Message-ID: <1581925888-103620-4-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, "Michael S. Tsirkin" , Xu Yandong , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Igor Mammedov , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move memmap member from VirtMachineState to ArmMachineState. Cc: Michael S. Tsirkin Cc: Igor Mammedov Cc: Shannon Zhao Signed-off-by: Xu Yandong --- hw/arm/virt-acpi-build.c | 21 +++-- hw/arm/virt.c | 178 ++++++++++++++++++++------------------- include/hw/arm/arm.h | 1 + include/hw/arm/virt.h | 4 +- 4 files changed, 110 insertions(+), 94 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index bd5f771e9b..ef61a651c1 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -43,6 +43,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pci.h" +#include "hw/arm/arm.h" #include "hw/arm/virt.h" #include "sysemu/numa.h" #include "sysemu/reset.h" @@ -383,6 +384,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) AcpiIortSmmu3 *smmu; size_t node_size, iort_node_offset, iort_length, smmu_offset =3D 0; AcpiIortRC *rc; + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 iort =3D acpi_data_push(table_data, sizeof(*iort)); =20 @@ -424,7 +426,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) smmu->length =3D cpu_to_le16(node_size); smmu->mapping_count =3D cpu_to_le32(1); smmu->mapping_offset =3D cpu_to_le32(sizeof(*smmu)); - smmu->base_address =3D cpu_to_le64(vms->memmap[VIRT_SMMU].base); + smmu->base_address =3D cpu_to_le64(ams->memmap[VIRT_SMMU].base); smmu->flags =3D cpu_to_le32(ACPI_IORT_SMMU_V3_COHACC_OVERRIDE); smmu->event_gsiv =3D cpu_to_le32(irq); smmu->pri_gsiv =3D cpu_to_le32(irq + 1); @@ -484,7 +486,8 @@ static void build_spcr(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { AcpiSerialPortConsoleRedirection *spcr; - const MemMapEntry *uart_memmap =3D &vms->memmap[VIRT_UART]; + ArmMachineState *ams =3D ARM_MACHINE(vms); + const MemMapEntry *uart_memmap =3D &ams->memmap[VIRT_UART]; int irq =3D vms->irqmap[VIRT_UART] + ARM_SPI_BASE; int spcr_start =3D table_data->len; =20 @@ -524,6 +527,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) uint64_t mem_base; MachineClass *mc =3D MACHINE_GET_CLASS(vms); MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); const CPUArchIdList *cpu_list =3D mc->possible_cpu_arch_ids(ms); =20 srat_start =3D table_data->len; @@ -539,7 +543,7 @@ build_srat(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) core->flags =3D cpu_to_le32(1); } =20 - mem_base =3D vms->memmap[VIRT_MEM].base; + mem_base =3D ams->memmap[VIRT_MEM].base; for (i =3D 0; i < ms->numa_state->num_nodes; ++i) { if (ms->numa_state->nodes[i].node_mem > 0) { numamem =3D acpi_data_push(table_data, sizeof(*numamem)); @@ -602,8 +606,9 @@ static void build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); int madt_start =3D table_data->len; - const MemMapEntry *memmap =3D vms->memmap; + const MemMapEntry *memmap =3D ams->memmap; const int *irqmap =3D vms->irqmap; AcpiMultipleApicTable *madt; AcpiMadtGenericDistributor *gicd; @@ -723,7 +728,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) { Aml *scope, *dsdt; MachineState *ms =3D MACHINE(vms); - const MemMapEntry *memmap =3D vms->memmap; + ArmMachineState *ams =3D ARM_MACHINE(vms); + const MemMapEntry *memmap =3D ams->memmap; const int *irqmap =3D vms->irqmap; =20 dsdt =3D init_aml_allocator(); @@ -796,6 +802,7 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) unsigned dsdt, xsdt; GArray *tables_blob =3D tables->table_data; MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 table_offsets =3D g_array_new(false, true /* clear */, sizeof(uint32_t)); @@ -821,8 +828,8 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) acpi_add_table(table_offsets, tables_blob); { AcpiMcfgInfo mcfg =3D { - .base =3D vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, - .size =3D vms->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, + .base =3D ams->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].base, + .size =3D ams->memmap[VIRT_ECAM_ID(vms->highmem_ecam)].size, }; build_mcfg(tables_blob, tables->linker, &mcfg); } diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 41b2076ce1..1dea640719 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -395,14 +395,14 @@ static void fdt_add_its_gic_node(VirtMachineState *vm= s) =20 vms->msi_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); nodename =3D g_strdup_printf("/intc/its@%" PRIx64, - vms->memmap[VIRT_GIC_ITS].base); + ams->memmap[VIRT_GIC_ITS].base); qemu_fdt_add_subnode(ams->fdt, nodename); qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v3-its"); qemu_fdt_setprop(ams->fdt, nodename, "msi-controller", NULL, 0); qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_ITS].base, - 2, vms->memmap[VIRT_GIC_ITS].size); + 2, ams->memmap[VIRT_GIC_ITS].base, + 2, ams->memmap[VIRT_GIC_ITS].size); qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->msi_phandle); g_free(nodename); } @@ -413,15 +413,15 @@ static void fdt_add_v2m_gic_node(VirtMachineState *vm= s) ArmMachineState *ams =3D ARM_MACHINE(vms); =20 nodename =3D g_strdup_printf("/intc/v2m@%" PRIx64, - vms->memmap[VIRT_GIC_V2M].base); + ams->memmap[VIRT_GIC_V2M].base); vms->msi_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); qemu_fdt_add_subnode(ams->fdt, nodename); qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v2m-frame"); qemu_fdt_setprop(ams->fdt, nodename, "msi-controller", NULL, 0); qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_V2M].base, - 2, vms->memmap[VIRT_GIC_V2M].size); + 2, ams->memmap[VIRT_GIC_V2M].base, + 2, ams->memmap[VIRT_GIC_V2M].size); qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->msi_phandle); g_free(nodename); } @@ -435,7 +435,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) qemu_fdt_setprop_cell(ams->fdt, "/", "interrupt-parent", vms->gic_phan= dle); =20 nodename =3D g_strdup_printf("/intc@%" PRIx64, - vms->memmap[VIRT_GIC_DIST].base); + ams->memmap[VIRT_GIC_DIST].base); qemu_fdt_add_subnode(ams->fdt, nodename); qemu_fdt_setprop_cell(ams->fdt, nodename, "#interrupt-cells", 3); qemu_fdt_setprop(ams->fdt, nodename, "interrupt-controller", NULL, 0); @@ -453,18 +453,18 @@ static void fdt_add_gic_node(VirtMachineState *vms) =20 if (nb_redist_regions =3D=3D 1) { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].bas= e, - 2, vms->memmap[VIRT_GIC_DIST].siz= e, - 2, vms->memmap[VIRT_GIC_REDIST].b= ase, - 2, vms->memmap[VIRT_GIC_REDIST].s= ize); + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_REDIST].b= ase, + 2, ams->memmap[VIRT_GIC_REDIST].s= ize); } else { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].base, - 2, vms->memmap[VIRT_GIC_DIST].size, - 2, vms->memmap[VIRT_GIC_REDIST].base, - 2, vms->memmap[VIRT_GIC_REDIST].size, - 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, - 2, vms->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); + 2, ams->memmap[VIRT_GIC_DIST].base, + 2, ams->memmap[VIRT_GIC_DIST].size, + 2, ams->memmap[VIRT_GIC_REDIST].base, + 2, ams->memmap[VIRT_GIC_REDIST].size, + 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, + 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); } =20 if (vms->virt) { @@ -478,20 +478,20 @@ static void fdt_add_gic_node(VirtMachineState *vms) "arm,cortex-a15-gic"); if (!vms->virt) { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].bas= e, - 2, vms->memmap[VIRT_GIC_DIST].siz= e, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size= ); + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_CPU].base, + 2, ams->memmap[VIRT_GIC_CPU].size= ); } else { qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, vms->memmap[VIRT_GIC_DIST].bas= e, - 2, vms->memmap[VIRT_GIC_DIST].siz= e, - 2, vms->memmap[VIRT_GIC_CPU].base, - 2, vms->memmap[VIRT_GIC_CPU].size, - 2, vms->memmap[VIRT_GIC_HYP].base, - 2, vms->memmap[VIRT_GIC_HYP].size, - 2, vms->memmap[VIRT_GIC_VCPU].bas= e, - 2, vms->memmap[VIRT_GIC_VCPU].siz= e); + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_CPU].base, + 2, ams->memmap[VIRT_GIC_CPU].size, + 2, ams->memmap[VIRT_GIC_HYP].base, + 2, ams->memmap[VIRT_GIC_HYP].size, + 2, ams->memmap[VIRT_GIC_VCPU].bas= e, + 2, ams->memmap[VIRT_GIC_VCPU].siz= e); qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, GIC_FDT_IRQ_FLAGS_LEVEL_HI); @@ -543,6 +543,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) { DeviceState *dev; MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); int irq =3D vms->irqmap[VIRT_ACPI_GED]; uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; =20 @@ -553,8 +554,8 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) dev =3D qdev_create(NULL, TYPE_ACPI_GED); qdev_prop_set_uint32(dev, "ged-event", event); =20 - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_ACPI_GED].bas= e); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, vms->memmap[VIRT_PCDIMM_ACPI].= base); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_ACPI_GED].bas= e); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, ams->memmap[VIRT_PCDIMM_ACPI].= base); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, = irq)); =20 qdev_init_nofail(dev); @@ -564,6 +565,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) =20 static void create_its(VirtMachineState *vms) { + ArmMachineState *ams =3D ARM_MACHINE(vms); const char *itsclass =3D its_class_name(); DeviceState *dev; =20 @@ -577,7 +579,7 @@ static void create_its(VirtMachineState *vms) object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", &error_abort); qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_ITS].base= ); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_GIC_ITS].base= ); =20 fdt_add_its_gic_node(vms); } @@ -585,11 +587,12 @@ static void create_its(VirtMachineState *vms) static void create_v2m(VirtMachineState *vms) { int i; + ArmMachineState *ams =3D ARM_MACHINE(vms); int irq =3D vms->irqmap[VIRT_GIC_V2M]; DeviceState *dev; =20 dev =3D qdev_create(NULL, "arm-gicv2m"); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, vms->memmap[VIRT_GIC_V2M].base= ); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_GIC_V2M].base= ); qdev_prop_set_uint32(dev, "base-spi", irq); qdev_prop_set_uint32(dev, "num-spi", NUM_GICV2M_SPIS); qdev_init_nofail(dev); @@ -605,6 +608,7 @@ static void create_v2m(VirtMachineState *vms) static void create_gic(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); /* We create a standalone GIC */ SysBusDevice *gicbusdev; const char *gictype; @@ -627,7 +631,7 @@ static void create_gic(VirtMachineState *vms) =20 if (type =3D=3D 3) { uint32_t redist0_capacity =3D - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); =20 nb_redist_regions =3D virt_gicv3_redist_region_count(vms); @@ -638,7 +642,7 @@ static void create_gic(VirtMachineState *vms) =20 if (nb_redist_regions =3D=3D 2) { uint32_t redist1_capacity =3D - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; + ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; =20 qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); @@ -651,18 +655,18 @@ static void create_gic(VirtMachineState *vms) } qdev_init_nofail(vms->gic); gicbusdev =3D SYS_BUS_DEVICE(vms->gic); - sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); + sysbus_mmio_map(gicbusdev, 0, ams->memmap[VIRT_GIC_DIST].base); if (type =3D=3D 3) { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); + sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_REDIST].base); if (nb_redist_regions =3D=3D 2) { sysbus_mmio_map(gicbusdev, 2, - vms->memmap[VIRT_HIGH_GIC_REDIST2].base); + ams->memmap[VIRT_HIGH_GIC_REDIST2].base); } } else { - sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base); + sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_CPU].base); if (vms->virt) { - sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base); - sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base); + sysbus_mmio_map(gicbusdev, 2, ams->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, ams->memmap[VIRT_GIC_VCPU].base); } } =20 @@ -728,8 +732,8 @@ static void create_uart(const VirtMachineState *vms, in= t uart, { char *nodename; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[uart].base; - hwaddr size =3D vms->memmap[uart].size; + hwaddr base =3D ams->memmap[uart].base; + hwaddr size =3D ams->memmap[uart].size; int irq =3D vms->irqmap[uart]; const char compat[] =3D "arm,pl011\0arm,primecell"; const char clocknames[] =3D "uartclk\0apb_pclk"; @@ -776,8 +780,8 @@ static void create_rtc(const VirtMachineState *vms) { char *nodename; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_RTC].base; - hwaddr size =3D vms->memmap[VIRT_RTC].size; + hwaddr base =3D ams->memmap[VIRT_RTC].base; + hwaddr size =3D ams->memmap[VIRT_RTC].size; int irq =3D vms->irqmap[VIRT_RTC]; const char compat[] =3D "arm,pl031\0arm,primecell"; =20 @@ -814,8 +818,8 @@ static void create_gpio(const VirtMachineState *vms) char *nodename; DeviceState *pl061_dev; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_GPIO].base; - hwaddr size =3D vms->memmap[VIRT_GPIO].size; + hwaddr base =3D ams->memmap[VIRT_GPIO].base; + hwaddr size =3D ams->memmap[VIRT_GPIO].size; int irq =3D vms->irqmap[VIRT_GPIO]; const char compat[] =3D "arm,pl061\0arm,primecell"; =20 @@ -858,7 +862,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) { int i; const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr size =3D vms->memmap[VIRT_MMIO].size; + hwaddr size =3D ams->memmap[VIRT_MMIO].size; =20 /* We create the transports in forwards order. Since qbus_realize() * prepends (not appends) new child buses, the incrementing loop below= will @@ -889,7 +893,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) */ for (i =3D 0; i < NUM_VIRTIO_TRANSPORTS; i++) { int irq =3D vms->irqmap[VIRT_MMIO] + i; - hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; + hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; =20 sysbus_create_simple("virtio-mmio", base, qdev_get_gpio_in(vms->gic, irq)); @@ -905,7 +909,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) for (i =3D NUM_VIRTIO_TRANSPORTS - 1; i >=3D 0; i--) { char *nodename; int irq =3D vms->irqmap[VIRT_MMIO] + i; - hwaddr base =3D vms->memmap[VIRT_MMIO].base + i * size; + hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; =20 nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); qemu_fdt_add_subnode(ams->fdt, nodename); @@ -975,6 +979,7 @@ static void virt_flash_map(VirtMachineState *vms, MemoryRegion *sysmem, MemoryRegion *secure_sysmem) { + ArmMachineState *ams =3D ARM_MACHINE(vms); /* * Map two flash devices to fill the VIRT_FLASH space in the memmap. * sysmem is the system memory space. secure_sysmem is the secure view @@ -983,8 +988,8 @@ static void virt_flash_map(VirtMachineState *vms, * If sysmem =3D=3D secure_sysmem this means there is no separate Secu= re * address space and both flash devices are generally visible. */ - hwaddr flashsize =3D vms->memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D vms->memmap[VIRT_FLASH].base; + hwaddr flashsize =3D ams->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D ams->memmap[VIRT_FLASH].base; =20 virt_flash_map1(vms->flash[0], flashbase, flashsize, secure_sysmem); @@ -997,8 +1002,8 @@ static void virt_flash_fdt(VirtMachineState *vms, MemoryRegion *secure_sysmem) { ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr flashsize =3D vms->memmap[VIRT_FLASH].size / 2; - hwaddr flashbase =3D vms->memmap[VIRT_FLASH].base; + hwaddr flashsize =3D ams->memmap[VIRT_FLASH].size / 2; + hwaddr flashbase =3D ams->memmap[VIRT_FLASH].base; char *nodename; =20 if (sysmem =3D=3D secure_sysmem) { @@ -1088,8 +1093,8 @@ static FWCfgState *create_fw_cfg(const VirtMachineSta= te *vms, AddressSpace *as) { MachineState *ms =3D MACHINE(vms); const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_FW_CFG].base; - hwaddr size =3D vms->memmap[VIRT_FW_CFG].size; + hwaddr base =3D ams->memmap[VIRT_FW_CFG].base; + hwaddr size =3D ams->memmap[VIRT_FW_CFG].size; FWCfgState *fw_cfg; char *nodename; =20 @@ -1152,8 +1157,8 @@ static void create_smmu(const VirtMachineState *vms, const char compat[] =3D "arm,smmu-v3"; int irq =3D vms->irqmap[VIRT_SMMU]; int i; - hwaddr base =3D vms->memmap[VIRT_SMMU].base; - hwaddr size =3D vms->memmap[VIRT_SMMU].size; + hwaddr base =3D ams->memmap[VIRT_SMMU].base; + hwaddr size =3D ams->memmap[VIRT_SMMU].size; const char irq_names[] =3D "eventq\0priq\0cmdq-sync\0gerror"; DeviceState *dev; =20 @@ -1199,12 +1204,12 @@ static void create_smmu(const VirtMachineState *vms, static void create_pcie(VirtMachineState *vms) { ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base_mmio =3D vms->memmap[VIRT_PCIE_MMIO].base; - hwaddr size_mmio =3D vms->memmap[VIRT_PCIE_MMIO].size; - hwaddr base_mmio_high =3D vms->memmap[VIRT_HIGH_PCIE_MMIO].base; - hwaddr size_mmio_high =3D vms->memmap[VIRT_HIGH_PCIE_MMIO].size; - hwaddr base_pio =3D vms->memmap[VIRT_PCIE_PIO].base; - hwaddr size_pio =3D vms->memmap[VIRT_PCIE_PIO].size; + hwaddr base_mmio =3D ams->memmap[VIRT_PCIE_MMIO].base; + hwaddr size_mmio =3D ams->memmap[VIRT_PCIE_MMIO].size; + hwaddr base_mmio_high =3D ams->memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D ams->memmap[VIRT_HIGH_PCIE_MMIO].size; + hwaddr base_pio =3D ams->memmap[VIRT_PCIE_PIO].base; + hwaddr size_pio =3D ams->memmap[VIRT_PCIE_PIO].size; hwaddr base_ecam, size_ecam; hwaddr base =3D base_mmio; int nr_pcie_buses; @@ -1222,8 +1227,8 @@ static void create_pcie(VirtMachineState *vms) qdev_init_nofail(dev); =20 ecam_id =3D VIRT_ECAM_ID(vms->highmem_ecam); - base_ecam =3D vms->memmap[ecam_id].base; - size_ecam =3D vms->memmap[ecam_id].size; + base_ecam =3D ams->memmap[ecam_id].base; + size_ecam =3D ams->memmap[ecam_id].size; nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; /* Map only the first size_ecam bytes of ECAM space */ ecam_alias =3D g_new0(MemoryRegion, 1); @@ -1333,11 +1338,12 @@ static void create_platform_bus(VirtMachineState *v= ms) SysBusDevice *s; int i; MemoryRegion *sysmem =3D get_system_memory(); + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 dev =3D qdev_create(NULL, TYPE_PLATFORM_BUS_DEVICE); dev->id =3D TYPE_PLATFORM_BUS_DEVICE; qdev_prop_set_uint32(dev, "num_irqs", PLATFORM_BUS_NUM_IRQS); - qdev_prop_set_uint32(dev, "mmio_size", vms->memmap[VIRT_PLATFORM_BUS].= size); + qdev_prop_set_uint32(dev, "mmio_size", ams->memmap[VIRT_PLATFORM_BUS].= size); qdev_init_nofail(dev); vms->platform_bus_dev =3D dev; =20 @@ -1348,7 +1354,7 @@ static void create_platform_bus(VirtMachineState *vms) } =20 memory_region_add_subregion(sysmem, - vms->memmap[VIRT_PLATFORM_BUS].base, + ams->memmap[VIRT_PLATFORM_BUS].base, sysbus_mmio_get_region(s, 0)); } =20 @@ -1358,8 +1364,8 @@ static void create_secure_ram(VirtMachineState *vms, MemoryRegion *secram =3D g_new(MemoryRegion, 1); char *nodename; ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D vms->memmap[VIRT_SECURE_MEM].base; - hwaddr size =3D vms->memmap[VIRT_SECURE_MEM].size; + hwaddr base =3D ams->memmap[VIRT_SECURE_MEM].base; + hwaddr size =3D ams->memmap[VIRT_SECURE_MEM].size; =20 memory_region_init_ram(secram, NULL, "virt.secure-ram", size, &error_fatal); @@ -1432,8 +1438,8 @@ void virt_machine_done(Notifier *notifier, void *data) */ if (info->dtb_filename =3D=3D NULL) { platform_bus_add_all_fdt_nodes(ams->fdt, "/intc", - vms->memmap[VIRT_PLATFORM_BUS].base, - vms->memmap[VIRT_PLATFORM_BUS].size, + ams->memmap[VIRT_PLATFORM_BUS].base, + ams->memmap[VIRT_PLATFORM_BUS].size, vms->irqmap[VIRT_PLATFORM_BUS]); } if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { @@ -1470,13 +1476,14 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineSta= te *vms, int idx) static void virt_set_memmap(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base, device_memory_base, device_memory_size; int i; =20 - vms->memmap =3D extended_memmap; + ams->memmap =3D extended_memmap; =20 for (i =3D 0; i < ARRAY_SIZE(base_memmap); i++) { - vms->memmap[i] =3D base_memmap[i]; + ams->memmap[i] =3D base_memmap[i]; } =20 if (ms->ram_slots > ACPI_MAX_RAM_SLOTS) { @@ -1493,7 +1500,7 @@ static void virt_set_memmap(VirtMachineState *vms) * The device region size assumes 1GiB page max alignment per slot. */ device_memory_base =3D - ROUND_UP(vms->memmap[VIRT_MEM].base + ms->ram_size, GiB); + ROUND_UP(ams->memmap[VIRT_MEM].base + ms->ram_size, GiB); device_memory_size =3D ms->maxram_size - ms->ram_size + ms->ram_slots = * GiB; =20 /* Base address of the high IO region */ @@ -1502,16 +1509,16 @@ static void virt_set_memmap(VirtMachineState *vms) error_report("maxmem/slots too huge"); exit(EXIT_FAILURE); } - if (base < vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { - base =3D vms->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; + if (base < ams->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES) { + base =3D ams->memmap[VIRT_MEM].base + LEGACY_RAMLIMIT_BYTES; } =20 for (i =3D VIRT_LOWMEMMAP_LAST; i < ARRAY_SIZE(extended_memmap); i++) { hwaddr size =3D extended_memmap[i].size; =20 base =3D ROUND_UP(base, size); - vms->memmap[i].base =3D base; - vms->memmap[i].size =3D size; + ams->memmap[i].base =3D base; + ams->memmap[i].size =3D size; base +=3D size; } vms->highest_gpa =3D base - 1; @@ -1526,6 +1533,7 @@ static void virt_set_memmap(VirtMachineState *vms) static void machvirt_init(MachineState *machine) { VirtMachineState *vms =3D VIRT_MACHINE(machine); + ArmMachineState *ams =3D ARM_MACHINE(vms); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(machine); MachineClass *mc =3D MACHINE_GET_CLASS(machine); const CPUArchIdList *possible_cpus; @@ -1543,7 +1551,7 @@ static void machvirt_init(MachineState *machine) * In accelerated mode, the memory map is computed earlier in kvm_type= () * to create a VM with the right number of IPA bits. */ - if (!vms->memmap) { + if (!ams->memmap) { virt_set_memmap(vms); } =20 @@ -1619,9 +1627,9 @@ static void machvirt_init(MachineState *machine) */ if (vms->gic_version =3D=3D 3) { virt_max_cpus =3D - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; virt_max_cpus +=3D - vms->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; } else { virt_max_cpus =3D GIC_NCPU; } @@ -1693,7 +1701,7 @@ static void machvirt_init(MachineState *machine) } =20 if (object_property_find(cpuobj, "reset-cbar", NULL)) { - object_property_set_int(cpuobj, vms->memmap[VIRT_CPUPERIPHS].b= ase, + object_property_set_int(cpuobj, ams->memmap[VIRT_CPUPERIPHS].b= ase, "reset-cbar", &error_abort); } =20 @@ -1728,7 +1736,7 @@ static void machvirt_init(MachineState *machine) =20 memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", machine->ram_size); - memory_region_add_subregion(sysmem, vms->memmap[VIRT_MEM].base, ram); + memory_region_add_subregion(sysmem, ams->memmap[VIRT_MEM].base, ram); if (machine->device_memory) { memory_region_add_subregion(sysmem, machine->device_memory->base, &machine->device_memory->mr); @@ -1777,7 +1785,7 @@ static void machvirt_init(MachineState *machine) vms->bootinfo.ram_size =3D machine->ram_size; vms->bootinfo.nb_cpus =3D smp_cpus; vms->bootinfo.board_id =3D -1; - vms->bootinfo.loader_start =3D vms->memmap[VIRT_MEM].base; + vms->bootinfo.loader_start =3D ams->memmap[VIRT_MEM].base; vms->bootinfo.get_dtb =3D machvirt_dtb; vms->bootinfo.skip_dtb_autoload =3D true; vms->bootinfo.firmware_loaded =3D firmware_loaded; diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index b3b3daa95a..f269668d41 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -87,6 +87,7 @@ typedef struct { =20 typedef struct { MachineState parent; + MemMapEntry *memmap; void *fdt; int fdt_size; } ArmMachineState; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ad353bad92..1b460d8d31 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -71,7 +71,6 @@ typedef struct { int32_t gic_version; VirtIOMMUType iommu; struct arm_boot_info bootinfo; - MemMapEntry *memmap; const int *irqmap; int smp_cpus; uint32_t clock_phandle; @@ -100,8 +99,9 @@ void virt_acpi_setup(VirtMachineState *vms); /* Return the number of used redistributor regions */ static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) { + ArmMachineState *ams =3D ARM_MACHINE(vms); uint32_t redist0_capacity =3D - vms->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; =20 assert(vms->gic_version =3D=3D 3); =20 --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925493567437.7661505075075; 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Mon, 17 Feb 2020 15:42:05 +0800 From: Xu Yandong To: Subject: [PATCH RFC 04/16] hw/arm: move shared irqmap member to ArmMachine Date: Mon, 17 Feb 2020 02:51:16 -0500 Message-ID: <1581925888-103620-5-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, "Michael S. Tsirkin" , Xu Yandong , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Igor Mammedov , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move irqmap member from VirtMachineState to ArmMachineState. Cc: Michael S. Tsirkin Cc: Igor Mammedov Cc: Shannon Zhao Signed-off-by: Xu Yandong --- hw/arm/virt-acpi-build.c | 8 ++++---- hw/arm/virt.c | 25 +++++++++++++------------ include/hw/arm/arm.h | 1 + include/hw/arm/virt.h | 1 - 4 files changed, 18 insertions(+), 17 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index ef61a651c1..27e6c95eca 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -414,7 +414,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) its->identifiers[0] =3D 0; /* MADT translation_id */ =20 if (vms->iommu =3D=3D VIRT_IOMMU_SMMUV3) { - int irq =3D vms->irqmap[VIRT_SMMU] + ARM_SPI_BASE; + int irq =3D ams->irqmap[VIRT_SMMU] + ARM_SPI_BASE; =20 /* SMMUv3 node */ smmu_offset =3D iort_node_offset + node_size; @@ -488,7 +488,7 @@ build_spcr(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) AcpiSerialPortConsoleRedirection *spcr; ArmMachineState *ams =3D ARM_MACHINE(vms); const MemMapEntry *uart_memmap =3D &ams->memmap[VIRT_UART]; - int irq =3D vms->irqmap[VIRT_UART] + ARM_SPI_BASE; + int irq =3D ams->irqmap[VIRT_UART] + ARM_SPI_BASE; int spcr_start =3D table_data->len; =20 spcr =3D acpi_data_push(table_data, sizeof(*spcr)); @@ -609,7 +609,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) ArmMachineState *ams =3D ARM_MACHINE(vms); int madt_start =3D table_data->len; const MemMapEntry *memmap =3D ams->memmap; - const int *irqmap =3D vms->irqmap; + const int *irqmap =3D ams->irqmap; AcpiMultipleApicTable *madt; AcpiMadtGenericDistributor *gicd; AcpiMadtGenericMsiFrame *gic_msi; @@ -730,7 +730,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) MachineState *ms =3D MACHINE(vms); ArmMachineState *ams =3D ARM_MACHINE(vms); const MemMapEntry *memmap =3D ams->memmap; - const int *irqmap =3D vms->irqmap; + const int *irqmap =3D ams->irqmap; =20 dsdt =3D init_aml_allocator(); /* Reserve space for header */ diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 1dea640719..e7eee13385 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -544,7 +544,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) DeviceState *dev; MachineState *ms =3D MACHINE(vms); ArmMachineState *ams =3D ARM_MACHINE(vms); - int irq =3D vms->irqmap[VIRT_ACPI_GED]; + int irq =3D ams->irqmap[VIRT_ACPI_GED]; uint32_t event =3D ACPI_GED_PWR_DOWN_EVT; =20 if (ms->ram_slots) { @@ -588,7 +588,7 @@ static void create_v2m(VirtMachineState *vms) { int i; ArmMachineState *ams =3D ARM_MACHINE(vms); - int irq =3D vms->irqmap[VIRT_GIC_V2M]; + int irq =3D ams->irqmap[VIRT_GIC_V2M]; DeviceState *dev; =20 dev =3D qdev_create(NULL, "arm-gicv2m"); @@ -734,7 +734,7 @@ static void create_uart(const VirtMachineState *vms, in= t uart, const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D ams->memmap[uart].base; hwaddr size =3D ams->memmap[uart].size; - int irq =3D vms->irqmap[uart]; + int irq =3D ams->irqmap[uart]; const char compat[] =3D "arm,pl011\0arm,primecell"; const char clocknames[] =3D "uartclk\0apb_pclk"; DeviceState *dev =3D qdev_create(NULL, "pl011"); @@ -782,7 +782,7 @@ static void create_rtc(const VirtMachineState *vms) const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D ams->memmap[VIRT_RTC].base; hwaddr size =3D ams->memmap[VIRT_RTC].size; - int irq =3D vms->irqmap[VIRT_RTC]; + int irq =3D ams->irqmap[VIRT_RTC]; const char compat[] =3D "arm,pl031\0arm,primecell"; =20 sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); @@ -820,7 +820,7 @@ static void create_gpio(const VirtMachineState *vms) const ArmMachineState *ams =3D ARM_MACHINE(vms); hwaddr base =3D ams->memmap[VIRT_GPIO].base; hwaddr size =3D ams->memmap[VIRT_GPIO].size; - int irq =3D vms->irqmap[VIRT_GPIO]; + int irq =3D ams->irqmap[VIRT_GPIO]; const char compat[] =3D "arm,pl061\0arm,primecell"; =20 pl061_dev =3D sysbus_create_simple("pl061", base, @@ -892,7 +892,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) * of disks users must use UUIDs or similar mechanisms. */ for (i =3D 0; i < NUM_VIRTIO_TRANSPORTS; i++) { - int irq =3D vms->irqmap[VIRT_MMIO] + i; + int irq =3D ams->irqmap[VIRT_MMIO] + i; hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; =20 sysbus_create_simple("virtio-mmio", base, @@ -908,7 +908,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) */ for (i =3D NUM_VIRTIO_TRANSPORTS - 1; i >=3D 0; i--) { char *nodename; - int irq =3D vms->irqmap[VIRT_MMIO] + i; + int irq =3D ams->irqmap[VIRT_MMIO] + i; hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; =20 nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); @@ -1155,7 +1155,7 @@ static void create_smmu(const VirtMachineState *vms, char *node; const ArmMachineState *ams =3D ARM_MACHINE(vms); const char compat[] =3D "arm,smmu-v3"; - int irq =3D vms->irqmap[VIRT_SMMU]; + int irq =3D ams->irqmap[VIRT_SMMU]; int i; hwaddr base =3D ams->memmap[VIRT_SMMU].base; hwaddr size =3D ams->memmap[VIRT_SMMU].size; @@ -1213,7 +1213,7 @@ static void create_pcie(VirtMachineState *vms) hwaddr base_ecam, size_ecam; hwaddr base =3D base_mmio; int nr_pcie_buses; - int irq =3D vms->irqmap[VIRT_PCIE]; + int irq =3D ams->irqmap[VIRT_PCIE]; MemoryRegion *mmio_alias; MemoryRegion *mmio_reg; MemoryRegion *ecam_alias; @@ -1349,7 +1349,7 @@ static void create_platform_bus(VirtMachineState *vms) =20 s =3D SYS_BUS_DEVICE(dev); for (i =3D 0; i < PLATFORM_BUS_NUM_IRQS; i++) { - int irq =3D vms->irqmap[VIRT_PLATFORM_BUS] + i; + int irq =3D ams->irqmap[VIRT_PLATFORM_BUS] + i; sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); } =20 @@ -1440,7 +1440,7 @@ void virt_machine_done(Notifier *notifier, void *data) platform_bus_add_all_fdt_nodes(ams->fdt, "/intc", ams->memmap[VIRT_PLATFORM_BUS].base, ams->memmap[VIRT_PLATFORM_BUS].size, - vms->irqmap[VIRT_PLATFORM_BUS]); + ams->irqmap[VIRT_PLATFORM_BUS]); } if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { exit(1); @@ -2084,6 +2084,7 @@ static void virt_instance_init(Object *obj) { VirtMachineState *vms =3D VIRT_MACHINE(obj); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); =20 /* EL3 is disabled by default on virt: this makes us consistent * between KVM and TCG for this board, and it also allows us to @@ -2146,7 +2147,7 @@ static void virt_instance_init(Object *obj) "Valid values are none and smmuv3", NULL); =20 - vms->irqmap =3D a15irqmap; + ams->irqmap =3D a15irqmap; =20 virt_flash_create(vms); } diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index f269668d41..97cb902b6a 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -88,6 +88,7 @@ typedef struct { typedef struct { MachineState parent; MemMapEntry *memmap; + const int *irqmap; void *fdt; int fdt_size; } ArmMachineState; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 1b460d8d31..4028821a09 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -71,7 +71,6 @@ typedef struct { int32_t gic_version; VirtIOMMUType iommu; struct arm_boot_info bootinfo; - const int *irqmap; int smp_cpus; uint32_t clock_phandle; uint32_t gic_phandle; --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925408540168.94836506806428; Sun, 16 Feb 2020 23:43:28 -0800 (PST) Received: from localhost ([::1]:41424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b3u-0005ws-W2 for importer@patchew.org; Mon, 17 Feb 2020 02:43:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39288) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b2v-0004Hc-Kc for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2t-0000U0-Q0 for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:25 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:45474 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2q-0000Jp-F4; Mon, 17 Feb 2020 02:42:20 -0500 Received: from DGGEMS414-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id C1114725AEB8CBDF36BB; Mon, 17 Feb 2020 15:42:14 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS414-HUB.china.huawei.com (10.3.19.214) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:06 +0800 From: Xu Yandong To: Subject: [PATCH RFC 05/16] hw/arm: move shared smp_cpus member to ArmMachine Date: Mon, 17 Feb 2020 02:51:17 -0500 Message-ID: <1581925888-103620-6-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, "Michael S. Tsirkin" , Xu Yandong , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Igor Mammedov , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move smp_cpus member from VirtMachineState to ArmMachineState. Cc: Michael S. Tsirkin Cc: Igor Mammedov Cc: Shannon Zhao Signed-off-by: Xu Yandong --- hw/arm/virt-acpi-build.c | 4 ++-- hw/arm/virt.c | 12 ++++++------ include/hw/arm/arm.h | 1 + include/hw/arm/virt.h | 3 +-- 4 files changed, 10 insertions(+), 10 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 27e6c95eca..ef2761ef77 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -623,7 +623,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicd->base_address =3D cpu_to_le64(memmap[VIRT_GIC_DIST].base); gicd->version =3D vms->gic_version; =20 - for (i =3D 0; i < vms->smp_cpus; i++) { + for (i =3D 0; i < ams->smp_cpus; i++) { AcpiMadtGenericCpuInterface *gicc =3D acpi_data_push(table_data, sizeof(*gicc)); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(i)); @@ -742,7 +742,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) * the RTC ACPI device at all when using UEFI. */ scope =3D aml_scope("\\_SB"); - acpi_dsdt_add_cpus(scope, vms->smp_cpus); + acpi_dsdt_add_cpus(scope, ams->smp_cpus); acpi_dsdt_add_uart(scope, &memmap[VIRT_UART], (irqmap[VIRT_UART] + ARM_SPI_BASE)); acpi_dsdt_add_flash(scope, &memmap[VIRT_FLASH]); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index e7eee13385..9031fd6757 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -300,7 +300,7 @@ static void fdt_add_timer_nodes(const VirtMachineState = *vms) if (vms->gic_version =3D=3D 2) { irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, - (1 << vms->smp_cpus) - 1); + (1 << ams->smp_cpus) - 1); } =20 qemu_fdt_add_subnode(ams->fdt, "/timer"); @@ -342,7 +342,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) * The simplest way to go is to examine affinity IDs of all our CPUs.= If * at least one of them has Aff3 populated, we set #address-cells to = 2. */ - for (cpu =3D 0; cpu < vms->smp_cpus; cpu++) { + for (cpu =3D 0; cpu < ams->smp_cpus; cpu++) { ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); =20 if (armcpu->mp_affinity & ARM_AFF3_MASK) { @@ -355,7 +355,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#address-cells", addr_cells); qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#size-cells", 0x0); =20 - for (cpu =3D vms->smp_cpus - 1; cpu >=3D 0; cpu--) { + for (cpu =3D ams->smp_cpus - 1; cpu >=3D 0; cpu--) { char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); CPUState *cs =3D CPU(armcpu); @@ -366,7 +366,7 @@ static void fdt_add_cpu_nodes(const VirtMachineState *v= ms) armcpu->dtb_compatible); =20 if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED - && vms->smp_cpus > 1) { + && ams->smp_cpus > 1) { qemu_fdt_setprop_string(ams->fdt, nodename, "enable-method", "psci"); } @@ -525,7 +525,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *v= ms) if (vms->gic_version =3D=3D 2) { irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, - (1 << vms->smp_cpus) - 1); + (1 << ams->smp_cpus) - 1); } =20 armcpu =3D ARM_CPU(qemu_get_cpu(0)); @@ -1641,7 +1641,7 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - vms->smp_cpus =3D smp_cpus; + ams->smp_cpus =3D smp_cpus; =20 if (vms->virt && kvm_enabled()) { error_report("mach-virt: KVM does not support providing " diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 97cb902b6a..469f603e77 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -89,6 +89,7 @@ typedef struct { MachineState parent; MemMapEntry *memmap; const int *irqmap; + int smp_cpus; void *fdt; int fdt_size; } ArmMachineState; diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 4028821a09..dfc2a16010 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -71,7 +71,6 @@ typedef struct { int32_t gic_version; VirtIOMMUType iommu; struct arm_boot_info bootinfo; - int smp_cpus; uint32_t clock_phandle; uint32_t gic_phandle; uint32_t msi_phandle; @@ -104,7 +103,7 @@ static inline int virt_gicv3_redist_region_count(VirtMa= chineState *vms) =20 assert(vms->gic_version =3D=3D 3); =20 - return vms->smp_cpus > redist0_capacity ? 2 : 1; + return ams->smp_cpus > redist0_capacity ? 2 : 1; } =20 #endif /* QEMU_ARM_VIRT_H */ --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925410101247.86920569538643; Sun, 16 Feb 2020 23:43:30 -0800 (PST) Received: from localhost ([::1]:41426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b3w-00062p-Qy for importer@patchew.org; Mon, 17 Feb 2020 02:43:28 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39254) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b2u-0004Gy-IZ for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2s-0000So-Tm for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:24 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:36470 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2q-0000JD-FD; Mon, 17 Feb 2020 02:42:20 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id EAFCB999BEF12C43F04B; Mon, 17 Feb 2020 15:42:13 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:07 +0800 From: Xu Yandong To: Subject: [PATCH RFC 06/16] hw/arm/virt: split MSI related codes from create_gic Date: Mon, 17 Feb 2020 02:51:18 -0500 Message-ID: <1581925888-103620-7-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GICv2m and GICits is not always needed. Signed-off-by: Xu Yandong --- hw/arm/virt.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9031fd6757..32c3977e32 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -605,6 +605,15 @@ static void create_v2m(VirtMachineState *vms) fdt_add_v2m_gic_node(vms); } =20 +static void gic_set_msi_interrupt(VirtMachineState *vms) +{ + if (vms->gic_version =3D=3D 3 && vms->its) { + create_its(vms); + } else if (vms->gic_version =3D=3D 2) { + create_v2m(vms); + } +} + static void create_gic(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); @@ -719,12 +728,7 @@ static void create_gic(VirtMachineState *vms) } =20 fdt_add_gic_node(vms); - - if (type =3D=3D 3 && vms->its) { - create_its(vms); - } else if (type =3D=3D 2) { - create_v2m(vms); - } + gic_set_msi_interrupt(vms); } =20 static void create_uart(const VirtMachineState *vms, int uart, --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925410586196.2544866500699; Sun, 16 Feb 2020 23:43:30 -0800 (PST) Received: from localhost ([::1]:41428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b3x-00063L-7d for importer@patchew.org; Mon, 17 Feb 2020 02:43:29 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39340) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b2w-0004IP-Lv for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:28 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2u-0000Us-Fl for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:26 -0500 Received: from szxga06-in.huawei.com ([45.249.212.32]:36468 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2q-0000JC-FD; Mon, 17 Feb 2020 02:42:21 -0500 Received: from DGGEMS409-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 01E78AE914653679CE4E; Mon, 17 Feb 2020 15:42:14 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS409-HUB.china.huawei.com (10.3.19.209) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:07 +0800 From: Xu Yandong To: Subject: [PATCH RFC 07/16] hw/arm/virt: split virt extension related codes from create_gic Date: Mon, 17 Feb 2020 02:51:19 -0500 Message-ID: <1581925888-103620-8-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" EL2 extension is not always needed. Signed-off-by: Xu Yandong --- hw/arm/virt.c | 116 +++++++++++++++++++++++++++++++++----------------- 1 file changed, 77 insertions(+), 39 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 32c3977e32..afaf143888 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -426,6 +426,45 @@ static void fdt_add_v2m_gic_node(VirtMachineState *vms) g_free(nodename); } =20 +static void fdt_gic_set_virt_extension(VirtMachineState *vms) +{ + char *nodename; + ArmMachineState *ams =3D ARM_MACHINE(vms); + + nodename =3D g_strdup_printf("/intc@%" PRIx64, + ams->memmap[VIRT_GIC_DIST].base); + + + if (vms->gic_version =3D=3D 3) { + if (vms->virt) { + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + } + } else { + if (!vms->virt) { + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_CPU].base, + 2, ams->memmap[VIRT_GIC_CPU].size= ); + } else { + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_CPU].base, + 2, ams->memmap[VIRT_GIC_CPU].size, + 2, ams->memmap[VIRT_GIC_HYP].base, + 2, ams->memmap[VIRT_GIC_HYP].size, + 2, ams->memmap[VIRT_GIC_VCPU].bas= e, + 2, ams->memmap[VIRT_GIC_VCPU].siz= e); + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + } + } +} + static void fdt_add_gic_node(VirtMachineState *vms) { char *nodename; @@ -466,36 +505,10 @@ static void fdt_add_gic_node(VirtMachineState *vms) 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); } - - if (vms->virt) { - qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - } } else { /* 'cortex-a15-gic' means 'GIC v2' */ qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,cortex-a15-gic"); - if (!vms->virt) { - qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, ams->memmap[VIRT_GIC_DIST].bas= e, - 2, ams->memmap[VIRT_GIC_DIST].siz= e, - 2, ams->memmap[VIRT_GIC_CPU].base, - 2, ams->memmap[VIRT_GIC_CPU].size= ); - } else { - qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, ams->memmap[VIRT_GIC_DIST].bas= e, - 2, ams->memmap[VIRT_GIC_DIST].siz= e, - 2, ams->memmap[VIRT_GIC_CPU].base, - 2, ams->memmap[VIRT_GIC_CPU].size, - 2, ams->memmap[VIRT_GIC_HYP].base, - 2, ams->memmap[VIRT_GIC_HYP].size, - 2, ams->memmap[VIRT_GIC_VCPU].bas= e, - 2, ams->memmap[VIRT_GIC_VCPU].siz= e); - qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - } } =20 qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->gic_phandle); @@ -614,6 +627,40 @@ static void gic_set_msi_interrupt(VirtMachineState *vm= s) } } =20 +static void qdev_gic_set_virt_bit(VirtMachineState *vms) +{ + if (vms->gic_version !=3D 3 && !kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", + vms->virt); + } +} + +static void set_gic_virt_sysbus(VirtMachineState *vms) +{ + MachineState *ms =3D MACHINE(vms); + ArmMachineState *ams =3D ARM_MACHINE(vms); + SysBusDevice *gicbusdev; + int type =3D vms->gic_version, i; + unsigned int smp_cpus =3D ms->smp.cpus; + + if (!vms->virt) { + return; + } + + gicbusdev =3D SYS_BUS_DEVICE(vms->gic); + if (type !=3D 3) { + sysbus_mmio_map(gicbusdev, 2, ams->memmap[VIRT_GIC_HYP].base); + sysbus_mmio_map(gicbusdev, 3, ams->memmap[VIRT_GIC_VCPU].base); + } + + for (i =3D 0; i < smp_cpus; i++) { + int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + qemu_irq irq =3D qdev_get_gpio_in(vms->gic, + ppibase + ARCH_GIC_MAINT_IRQ); + sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); + } +} + static void create_gic(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); @@ -656,12 +703,8 @@ static void create_gic(VirtMachineState *vms) qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } - } else { - if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", - vms->virt); - } } + qdev_gic_set_virt_bit(vms); qdev_init_nofail(vms->gic); gicbusdev =3D SYS_BUS_DEVICE(vms->gic); sysbus_mmio_map(gicbusdev, 0, ams->memmap[VIRT_GIC_DIST].base); @@ -673,10 +716,6 @@ static void create_gic(VirtMachineState *vms) } } else { sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_CPU].base); - if (vms->virt) { - sysbus_mmio_map(gicbusdev, 2, ams->memmap[VIRT_GIC_HYP].base); - sysbus_mmio_map(gicbusdev, 3, ams->memmap[VIRT_GIC_VCPU].base); - } } =20 /* Wire the outputs from each CPU's generic timer and the GICv3 @@ -708,10 +747,6 @@ static void create_gic(VirtMachineState *vms) ppibase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", 0, irq); - } else if (vms->virt) { - qemu_irq irq =3D qdev_get_gpio_in(vms->gic, - ppibase + ARCH_GIC_MAINT_IRQ); - sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); } =20 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, @@ -727,7 +762,10 @@ static void create_gic(VirtMachineState *vms) qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); } =20 + set_gic_virt_sysbus(vms); fdt_add_gic_node(vms); + fdt_gic_set_virt_extension(vms); + gic_set_msi_interrupt(vms); } =20 --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925408140798.102004252796; Sun, 16 Feb 2020 23:43:28 -0800 (PST) Received: from localhost ([::1]:41422 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b3u-0005vN-75 for importer@patchew.org; Mon, 17 Feb 2020 02:43:26 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39270) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b2v-0004HC-0l for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:26 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2t-0000TZ-FR for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:24 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2715 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2q-0000Jq-FF; Mon, 17 Feb 2020 02:42:20 -0500 Received: from DGGEMS411-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 240E8450A0A70BD7C906; Mon, 17 Feb 2020 15:42:15 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS411-HUB.china.huawei.com (10.3.19.211) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:08 +0800 From: Xu Yandong To: Subject: [PATCH RFC 08/16] hw/arm/virt: split secure extension related codes from create_gic Date: Mon, 17 Feb 2020 02:51:20 -0500 Message-ID: <1581925888-103620-9-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" EL3 extension is not always needed. Signed-off-by: Xu Yandong --- hw/arm/virt.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index afaf143888..087616190e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -627,6 +627,14 @@ static void gic_set_msi_interrupt(VirtMachineState *vm= s) } } =20 +static void qdev_gic_set_secure_bit(VirtMachineState *vms) +{ + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(vms->gic, "has-security-extensions", + vms->secure); + } +} + static void qdev_gic_set_virt_bit(VirtMachineState *vms) { if (vms->gic_version !=3D 3 && !kvm_irqchip_in_kernel()) { @@ -681,9 +689,6 @@ static void create_gic(VirtMachineState *vms) * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); - if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); - } =20 if (type =3D=3D 3) { uint32_t redist0_capacity =3D @@ -704,6 +709,7 @@ static void create_gic(VirtMachineState *vms) MIN(smp_cpus - redist0_count, redist1_capacity)); } } + qdev_gic_set_secure_bit(vms); qdev_gic_set_virt_bit(vms); qdev_init_nofail(vms->gic); gicbusdev =3D SYS_BUS_DEVICE(vms->gic); --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925708707523.462876294008; Sun, 16 Feb 2020 23:48:28 -0800 (PST) Received: from localhost ([::1]:41518 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b8l-00066K-AM for importer@patchew.org; Mon, 17 Feb 2020 02:48:27 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39545) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b34-0004Xf-IK for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:37 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b31-0000eI-0s for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:34 -0500 Received: from szxga04-in.huawei.com ([45.249.212.190]:2716 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2r-0000ME-Of; Mon, 17 Feb 2020 02:42:22 -0500 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id D09AD3EBCC26B2E87BB5; Mon, 17 Feb 2020 15:42:17 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:08 +0800 From: Xu Yandong To: Subject: [PATCH RFC 09/16] hw/arm: move shared gic member to ArmMachine Date: Mon, 17 Feb 2020 02:51:21 -0500 Message-ID: <1581925888-103620-10-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, "Michael S. Tsirkin" , Xu Yandong , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Igor Mammedov , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move gic member from VirtMachineState to ArmMachineState. Cc: Michael S. Tsirkin Cc: Igor Mammedov Cc: Shannon Zhao Signed-off-by: Xu Yandong --- hw/arm/arm.c | 35 ++++++++++ hw/arm/virt-acpi-build.c | 8 +-- hw/arm/virt.c | 139 +++++++++++++++------------------------ include/hw/arm/arm.h | 17 +++++ include/hw/arm/virt.h | 15 ----- 5 files changed, 110 insertions(+), 104 deletions(-) diff --git a/hw/arm/arm.c b/hw/arm/arm.c index 4261d56832..ecb99611ed 100644 --- a/hw/arm/arm.c +++ b/hw/arm/arm.c @@ -39,6 +39,32 @@ #include "hw/intc/arm_gic.h" #include "kvm_arm.h" =20 +static char *virt_get_gic_version(Object *obj, Error **errp) +{ + ArmMachineState *ams =3D ARM_MACHINE(obj); + const char *val =3D ams->gic_version =3D=3D 3 ? "3" : "2"; + + return g_strdup(val); +} + +static void virt_set_gic_version(Object *obj, const char *value, Error **e= rrp) +{ + ArmMachineState *ams =3D ARM_MACHINE(obj); + + if (!strcmp(value, "3")) { + ams->gic_version =3D 3; + } else if (!strcmp(value, "2")) { + ams->gic_version =3D 2; + } else if (!strcmp(value, "host")) { + ams->gic_version =3D 0; /* Will probe later */ + } else if (!strcmp(value, "max")) { + ams->gic_version =3D -1; /* Will probe later */ + } else { + error_setg(errp, "Invalid gic-version value"); + error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); + } +} + static void arm_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -55,6 +81,15 @@ static void arm_machine_class_init(ObjectClass *oc, void= *data) =20 static void arm_instance_init(Object *obj) { + ArmMachineState *ams =3D ARM_MACHINE(obj); + /* Default GIC type is v2 */ + ams->gic_version =3D 2; + object_property_add_str(obj, "gic-version", virt_get_gic_version, + virt_set_gic_version, NULL); + object_property_set_description(obj, "gic-version", + "Set GIC version. " + "Valid values are 2, 3 and host", NULL= ); + } =20 static const TypeInfo arm_machine_info =3D { diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index ef2761ef77..770c53f5d0 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -621,7 +621,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) gicd->type =3D ACPI_APIC_GENERIC_DISTRIBUTOR; gicd->length =3D sizeof(*gicd); gicd->base_address =3D cpu_to_le64(memmap[VIRT_GIC_DIST].base); - gicd->version =3D vms->gic_version; + gicd->version =3D ams->gic_version; =20 for (i =3D 0; i < ams->smp_cpus; i++) { AcpiMadtGenericCpuInterface *gicc =3D acpi_data_push(table_data, @@ -630,7 +630,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) =20 gicc->type =3D ACPI_APIC_GENERIC_CPU_INTERFACE; gicc->length =3D sizeof(*gicc); - if (vms->gic_version =3D=3D 2) { + if (ams->gic_version =3D=3D 2) { gicc->base_address =3D cpu_to_le64(memmap[VIRT_GIC_CPU].base); gicc->gich_base_address =3D cpu_to_le64(memmap[VIRT_GIC_HYP].b= ase); gicc->gicv_base_address =3D cpu_to_le64(memmap[VIRT_GIC_VCPU].= base); @@ -648,9 +648,9 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) } } =20 - if (vms->gic_version =3D=3D 3) { + if (ams->gic_version =3D=3D 3) { AcpiMadtGenericTranslator *gic_its; - int nb_redist_regions =3D virt_gicv3_redist_region_count(vms); + int nb_redist_regions =3D virt_gicv3_redist_region_count(ams); AcpiMadtGenericRedistributor *gicr =3D acpi_data_push(table_data, sizeof *gicr); =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 087616190e..b9689b0f0c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -100,10 +100,6 @@ #define DEFINE_VIRT_MACHINE(major, minor) \ DEFINE_VIRT_MACHINE_LATEST(major, minor, false) =20 - -/* Number of external interrupt lines to configure the GIC with */ -#define NUM_IRQS 256 - #define PLATFORM_BUS_NUM_IRQS 64 =20 /* Legacy RAM limit in GB (< version 4.0) */ @@ -297,7 +293,7 @@ static void fdt_add_timer_nodes(const VirtMachineState = *vms) irqflags =3D GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; } =20 - if (vms->gic_version =3D=3D 2) { + if (ams->gic_version =3D=3D 2) { irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << ams->smp_cpus) - 1); @@ -435,7 +431,7 @@ static void fdt_gic_set_virt_extension(VirtMachineState= *vms) ams->memmap[VIRT_GIC_DIST].base); =20 =20 - if (vms->gic_version =3D=3D 3) { + if (ams->gic_version =3D=3D 3) { if (vms->virt) { qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IR= Q, @@ -470,8 +466,8 @@ static void fdt_add_gic_node(VirtMachineState *vms) char *nodename; ArmMachineState *ams =3D ARM_MACHINE(vms); =20 - vms->gic_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); - qemu_fdt_setprop_cell(ams->fdt, "/", "interrupt-parent", vms->gic_phan= dle); + ams->gic_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); + qemu_fdt_setprop_cell(ams->fdt, "/", "interrupt-parent", ams->gic_phan= dle); =20 nodename =3D g_strdup_printf("/intc@%" PRIx64, ams->memmap[VIRT_GIC_DIST].base); @@ -481,8 +477,8 @@ static void fdt_add_gic_node(VirtMachineState *vms) qemu_fdt_setprop_cell(ams->fdt, nodename, "#address-cells", 0x2); qemu_fdt_setprop_cell(ams->fdt, nodename, "#size-cells", 0x2); qemu_fdt_setprop(ams->fdt, nodename, "ranges", NULL, 0); - if (vms->gic_version =3D=3D 3) { - int nb_redist_regions =3D virt_gicv3_redist_region_count(vms); + if (ams->gic_version =3D=3D 3) { + int nb_redist_regions =3D virt_gicv3_redist_region_count(ams); =20 qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", "arm,gic-v3"); @@ -511,7 +507,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) "arm,cortex-a15-gic"); } =20 - qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", vms->gic_phandle); + qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", ams->gic_phandle); g_free(nodename); } =20 @@ -535,7 +531,7 @@ static void fdt_add_pmu_nodes(const VirtMachineState *v= ms) } } =20 - if (vms->gic_version =3D=3D 2) { + if (ams->gic_version =3D=3D 2) { irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, GIC_FDT_IRQ_PPI_CPU_WIDTH, (1 << ams->smp_cpus) - 1); @@ -569,7 +565,7 @@ static inline DeviceState *create_acpi_ged(VirtMachineS= tate *vms) =20 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_ACPI_GED].bas= e); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, ams->memmap[VIRT_PCDIMM_ACPI].= base); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(vms->gic, = irq)); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(ams->gic, = irq)); =20 qdev_init_nofail(dev); =20 @@ -589,7 +585,7 @@ static void create_its(VirtMachineState *vms) =20 dev =3D qdev_create(NULL, itsclass); =20 - object_property_set_link(OBJECT(dev), OBJECT(vms->gic), "parent-gicv3", + object_property_set_link(OBJECT(dev), OBJECT(ams->gic), "parent-gicv3", &error_abort); qdev_init_nofail(dev); sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ams->memmap[VIRT_GIC_ITS].base= ); @@ -612,7 +608,7 @@ static void create_v2m(VirtMachineState *vms) =20 for (i =3D 0; i < NUM_GICV2M_SPIS; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, - qdev_get_gpio_in(vms->gic, irq + i)); + qdev_get_gpio_in(ams->gic, irq + i)); } =20 fdt_add_v2m_gic_node(vms); @@ -620,25 +616,30 @@ static void create_v2m(VirtMachineState *vms) =20 static void gic_set_msi_interrupt(VirtMachineState *vms) { - if (vms->gic_version =3D=3D 3 && vms->its) { + ArmMachineState *ams =3D ARM_MACHINE(vms); + if (ams->gic_version =3D=3D 3 && vms->its) { create_its(vms); - } else if (vms->gic_version =3D=3D 2) { + } else if (ams->gic_version =3D=3D 2) { create_v2m(vms); } } =20 static void qdev_gic_set_secure_bit(VirtMachineState *vms) { + ArmMachineState *ams =3D ARM_MACHINE(vms); + if (!kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(vms->gic, "has-security-extensions", + qdev_prop_set_bit(ams->gic, "has-security-extensions", vms->secure); } } =20 static void qdev_gic_set_virt_bit(VirtMachineState *vms) { - if (vms->gic_version !=3D 3 && !kvm_irqchip_in_kernel()) { - qdev_prop_set_bit(vms->gic, "has-virtualization-extensions", + ArmMachineState *ams =3D ARM_MACHINE(vms); + + if (ams->gic_version !=3D 3 && !kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(ams->gic, "has-virtualization-extensions", vms->virt); } } @@ -648,14 +649,14 @@ static void set_gic_virt_sysbus(VirtMachineState *vms) MachineState *ms =3D MACHINE(vms); ArmMachineState *ams =3D ARM_MACHINE(vms); SysBusDevice *gicbusdev; - int type =3D vms->gic_version, i; + int type =3D ams->gic_version, i; unsigned int smp_cpus =3D ms->smp.cpus; =20 if (!vms->virt) { return; } =20 - gicbusdev =3D SYS_BUS_DEVICE(vms->gic); + gicbusdev =3D SYS_BUS_DEVICE(ams->gic); if (type !=3D 3) { sysbus_mmio_map(gicbusdev, 2, ams->memmap[VIRT_GIC_HYP].base); sysbus_mmio_map(gicbusdev, 3, ams->memmap[VIRT_GIC_VCPU].base); @@ -663,7 +664,7 @@ static void set_gic_virt_sysbus(VirtMachineState *vms) =20 for (i =3D 0; i < smp_cpus; i++) { int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; - qemu_irq irq =3D qdev_get_gpio_in(vms->gic, + qemu_irq irq =3D qdev_get_gpio_in(ams->gic, ppibase + ARCH_GIC_MAINT_IRQ); sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq); } @@ -676,43 +677,43 @@ static void create_gic(VirtMachineState *vms) /* We create a standalone GIC */ SysBusDevice *gicbusdev; const char *gictype; - int type =3D vms->gic_version, i; + int type =3D ams->gic_version, i; unsigned int smp_cpus =3D ms->smp.cpus; uint32_t nb_redist_regions =3D 0; =20 gictype =3D (type =3D=3D 3) ? gicv3_class_name() : gic_class_name(); =20 - vms->gic =3D qdev_create(NULL, gictype); - qdev_prop_set_uint32(vms->gic, "revision", type); - qdev_prop_set_uint32(vms->gic, "num-cpu", smp_cpus); + ams->gic =3D qdev_create(NULL, gictype); + qdev_prop_set_uint32(ams->gic, "revision", type); + qdev_prop_set_uint32(ams->gic, "num-cpu", smp_cpus); /* Note that the num-irq property counts both internal and external * interrupts; there are always 32 of the former (mandated by GIC spec= ). */ - qdev_prop_set_uint32(vms->gic, "num-irq", NUM_IRQS + 32); + qdev_prop_set_uint32(ams->gic, "num-irq", NUM_IRQS + 32); =20 if (type =3D=3D 3) { uint32_t redist0_capacity =3D ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); =20 - nb_redist_regions =3D virt_gicv3_redist_region_count(vms); + nb_redist_regions =3D virt_gicv3_redist_region_count(ams); =20 - qdev_prop_set_uint32(vms->gic, "len-redist-region-count", + qdev_prop_set_uint32(ams->gic, "len-redist-region-count", nb_redist_regions); - qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_c= ount); + qdev_prop_set_uint32(ams->gic, "redist-region-count[0]", redist0_c= ount); =20 if (nb_redist_regions =3D=3D 2) { uint32_t redist1_capacity =3D ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; =20 - qdev_prop_set_uint32(vms->gic, "redist-region-count[1]", + qdev_prop_set_uint32(ams->gic, "redist-region-count[1]", MIN(smp_cpus - redist0_count, redist1_capacity)); } } qdev_gic_set_secure_bit(vms); qdev_gic_set_virt_bit(vms); - qdev_init_nofail(vms->gic); - gicbusdev =3D SYS_BUS_DEVICE(vms->gic); + qdev_init_nofail(ams->gic); + gicbusdev =3D SYS_BUS_DEVICE(ams->gic); sysbus_mmio_map(gicbusdev, 0, ams->memmap[VIRT_GIC_DIST].base); if (type =3D=3D 3) { sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_REDIST].base); @@ -744,19 +745,19 @@ static void create_gic(VirtMachineState *vms) =20 for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(vms->gic, + qdev_get_gpio_in(ams->gic, ppibase + timer_irq[irq= ])); } =20 if (type =3D=3D 3) { - qemu_irq irq =3D qdev_get_gpio_in(vms->gic, + qemu_irq irq =3D qdev_get_gpio_in(ams->gic, ppibase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", 0, irq); } =20 qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(vms->gic, ppibase + qdev_get_gpio_in(ams->gic, ppibase + VIRTUAL_PMU_IRQ)); =20 sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); @@ -792,7 +793,7 @@ static void create_uart(const VirtMachineState *vms, in= t uart, qdev_init_nofail(dev); memory_region_add_subregion(mem, base, sysbus_mmio_get_region(s, 0)); - sysbus_connect_irq(s, 0, qdev_get_gpio_in(vms->gic, irq)); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(ams->gic, irq)); =20 nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); qemu_fdt_add_subnode(ams->fdt, nodename); @@ -833,7 +834,7 @@ static void create_rtc(const VirtMachineState *vms) int irq =3D ams->irqmap[VIRT_RTC]; const char compat[] =3D "arm,pl031\0arm,primecell"; =20 - sysbus_create_simple("pl031", base, qdev_get_gpio_in(vms->gic, irq)); + sysbus_create_simple("pl031", base, qdev_get_gpio_in(ams->gic, irq)); =20 nodename =3D g_strdup_printf("/pl031@%" PRIx64, base); qemu_fdt_add_subnode(ams->fdt, nodename); @@ -872,7 +873,7 @@ static void create_gpio(const VirtMachineState *vms) const char compat[] =3D "arm,pl061\0arm,primecell"; =20 pl061_dev =3D sysbus_create_simple("pl061", base, - qdev_get_gpio_in(vms->gic, irq)); + qdev_get_gpio_in(ams->gic, irq)); =20 uint32_t phandle =3D qemu_fdt_alloc_phandle(ams->fdt); nodename =3D g_strdup_printf("/pl061@%" PRIx64, base); @@ -944,7 +945,7 @@ static void create_virtio_devices(const VirtMachineStat= e *vms) hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; =20 sysbus_create_simple("virtio-mmio", base, - qdev_get_gpio_in(vms->gic, irq)); + qdev_get_gpio_in(ams->gic, irq)); } =20 /* We add dtb nodes in reverse order so that they appear in the finish= ed @@ -1222,7 +1223,7 @@ static void create_smmu(const VirtMachineState *vms, sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); for (i =3D 0; i < NUM_SMMU_IRQS; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, - qdev_get_gpio_in(vms->gic, irq + i)); + qdev_get_gpio_in(ams->gic, irq + i)); } =20 node =3D g_strdup_printf("/smmuv3@%" PRIx64, base); @@ -1311,7 +1312,7 @@ static void create_pcie(VirtMachineState *vms) =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, - qdev_get_gpio_in(vms->gic, irq + i)); + qdev_get_gpio_in(ams->gic, irq + i)); gpex_set_irq_num(GPEX_HOST(dev), i, irq + i); } =20 @@ -1366,7 +1367,7 @@ static void create_pcie(VirtMachineState *vms) } =20 qemu_fdt_setprop_cell(ams->fdt, nodename, "#interrupt-cells", 1); - create_pcie_irq_map(vms, vms->gic_phandle, irq, nodename); + create_pcie_irq_map(vms, ams->gic_phandle, irq, nodename); =20 if (vms->iommu) { vms->iommu_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); @@ -1398,7 +1399,7 @@ static void create_platform_bus(VirtMachineState *vms) s =3D SYS_BUS_DEVICE(dev); for (i =3D 0; i < PLATFORM_BUS_NUM_IRQS; i++) { int irq =3D ams->irqmap[VIRT_PLATFORM_BUS] + i; - sysbus_connect_irq(s, i, qdev_get_gpio_in(vms->gic, irq)); + sysbus_connect_irq(s, i, qdev_get_gpio_in(ams->gic, irq)); } =20 memory_region_add_subregion(sysmem, @@ -1501,6 +1502,7 @@ void virt_machine_done(Notifier *notifier, void *data) static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) { uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; + ArmMachineState *ams =3D ARM_MACHINE(vms); VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); =20 if (!vmc->disallow_affinity_adjustment) { @@ -1512,7 +1514,7 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineState= *vms, int idx) * purposes are to make TCG consistent (with 64-bit KVM hosts) * and to improve SGI efficiency. */ - if (vms->gic_version =3D=3D 3) { + if (ams->gic_version =3D=3D 3) { clustersz =3D GICV3_TARGETLIST_BITS; } else { clustersz =3D GIC_TARGETLIST_BITS; @@ -1606,19 +1608,19 @@ static void machvirt_init(MachineState *machine) /* We can probe only here because during property set * KVM is not available yet */ - if (vms->gic_version <=3D 0) { + if (ams->gic_version <=3D 0) { /* "host" or "max" */ if (!kvm_enabled()) { - if (vms->gic_version =3D=3D 0) { + if (ams->gic_version =3D=3D 0) { error_report("gic-version=3Dhost requires KVM"); exit(1); } else { /* "max": currently means 3 for TCG */ - vms->gic_version =3D 3; + ams->gic_version =3D 3; } } else { - vms->gic_version =3D kvm_arm_vgic_probe(); - if (!vms->gic_version) { + ams->gic_version =3D kvm_arm_vgic_probe(); + if (!ams->gic_version) { error_report( "Unable to determine GIC version supported by host"); exit(1); @@ -1673,7 +1675,7 @@ static void machvirt_init(MachineState *machine) /* The maximum number of CPUs depends on the GIC version, or on how * many redistributors we can fit into the memory map. */ - if (vms->gic_version =3D=3D 3) { + if (ams->gic_version =3D=3D 3) { virt_max_cpus =3D ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; virt_max_cpus +=3D @@ -1899,32 +1901,6 @@ static void virt_set_its(Object *obj, bool value, Er= ror **errp) vms->its =3D value; } =20 -static char *virt_get_gic_version(Object *obj, Error **errp) -{ - VirtMachineState *vms =3D VIRT_MACHINE(obj); - const char *val =3D vms->gic_version =3D=3D 3 ? "3" : "2"; - - return g_strdup(val); -} - -static void virt_set_gic_version(Object *obj, const char *value, Error **e= rrp) -{ - VirtMachineState *vms =3D VIRT_MACHINE(obj); - - if (!strcmp(value, "3")) { - vms->gic_version =3D 3; - } else if (!strcmp(value, "2")) { - vms->gic_version =3D 2; - } else if (!strcmp(value, "host")) { - vms->gic_version =3D 0; /* Will probe later */ - } else if (!strcmp(value, "max")) { - vms->gic_version =3D -1; /* Will probe later */ - } else { - error_setg(errp, "Invalid gic-version value"); - error_append_hint(errp, "Valid values are 3, 2, host, max.\n"); - } -} - static char *virt_get_iommu(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); @@ -2164,13 +2140,6 @@ static void virt_instance_init(Object *obj) "Set on/off to enable/disable using " "physical address space above 32 bits", NULL); - /* Default GIC type is v2 */ - vms->gic_version =3D 2; - object_property_add_str(obj, "gic-version", virt_get_gic_version, - virt_set_gic_version, NULL); - object_property_set_description(obj, "gic-version", - "Set GIC version. " - "Valid values are 2, 3 and host", NULL= ); =20 vms->highmem_ecam =3D !vmc->no_highmem_ecam; =20 diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 469f603e77..f8bde03cc3 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -74,6 +74,9 @@ enum { VIRT_HIGH_PCIE_MMIO, }; =20 +/* Number of external interrupt lines to configure the GIC with */ +#define NUM_IRQS 256 + /* indices of IO regions located after the RAM */ =20 typedef struct MemMapEntry { @@ -87,11 +90,14 @@ typedef struct { =20 typedef struct { MachineState parent; + int32_t gic_version; MemMapEntry *memmap; const int *irqmap; int smp_cpus; void *fdt; int fdt_size; + uint32_t gic_phandle; + DeviceState *gic; } ArmMachineState; =20 #define TYPE_ARM_MACHINE MACHINE_TYPE_NAME("arm") @@ -102,4 +108,15 @@ typedef struct { #define ARM_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(ArmMachineClass, klass, TYPE_ARM_MACHINE) =20 +/* Return the number of used redistributor regions */ +static inline int virt_gicv3_redist_region_count(ArmMachineState *ams) +{ + uint32_t redist0_capacity =3D + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + + assert(ams->gic_version =3D=3D 3); + + return ams->smp_cpus > redist0_capacity ? 2 : 1; +} + #endif /* QEMU_ARM_ARM_H */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index dfc2a16010..393afb7faf 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -68,16 +68,13 @@ typedef struct { bool highmem_ecam; bool its; bool virt; - int32_t gic_version; VirtIOMMUType iommu; struct arm_boot_info bootinfo; uint32_t clock_phandle; - uint32_t gic_phandle; uint32_t msi_phandle; uint32_t iommu_phandle; int psci_conduit; hwaddr highest_gpa; - DeviceState *gic; DeviceState *acpi_dev; Notifier powerdown_notifier; } VirtMachineState; @@ -94,16 +91,4 @@ typedef struct { =20 void virt_acpi_setup(VirtMachineState *vms); =20 -/* Return the number of used redistributor regions */ -static inline int virt_gicv3_redist_region_count(VirtMachineState *vms) -{ - ArmMachineState *ams =3D ARM_MACHINE(vms); - uint32_t redist0_capacity =3D - ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; - - assert(vms->gic_version =3D=3D 3); - - return ams->smp_cpus > redist0_capacity ? 2 : 1; -} - #endif /* QEMU_ARM_VIRT_H */ --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925498063593.4010959264531; Sun, 16 Feb 2020 23:44:58 -0800 (PST) Received: from localhost ([::1]:41462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b5M-00016j-OX for importer@patchew.org; Mon, 17 Feb 2020 02:44:56 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39483) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b31-0004PE-2b for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2z-0000cK-5R for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:30 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3230 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2t-0000RO-LK; Mon, 17 Feb 2020 02:42:24 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id CEE603A42C8FA0934C31; Mon, 17 Feb 2020 15:42:19 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:09 +0800 From: Xu Yandong To: Subject: [PATCH RFC 10/16] hw/arm: split create_gic function Date: Mon, 17 Feb 2020 02:51:22 -0500 Message-ID: <1581925888-103620-11-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Split sharable GIC qdev create and sysbus initiatea codes as independent fu= nction. Signed-off-by: Xu Yandong --- hw/arm/arm.c | 106 +++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt.c | 93 +------------------------------------ include/hw/arm/arm.h | 4 ++ 3 files changed, 112 insertions(+), 91 deletions(-) diff --git a/hw/arm/arm.c b/hw/arm/arm.c index ecb99611ed..c51bf513d2 100644 --- a/hw/arm/arm.c +++ b/hw/arm/arm.c @@ -39,6 +39,112 @@ #include "hw/intc/arm_gic.h" #include "kvm_arm.h" =20 +void qdev_create_gic(ArmMachineState *ams) +{ + MachineState *ms =3D MACHINE(ams); + /* We create a standalone GIC */ + const char *gictype; + int type =3D ams->gic_version; + unsigned int smp_cpus =3D ms->smp.cpus; + uint32_t nb_redist_regions =3D 0; + + gictype =3D (type =3D=3D 3) ? gicv3_class_name() : gic_class_name(); + + ams->gic =3D qdev_create(NULL, gictype); + qdev_prop_set_uint32(ams->gic, "revision", type); + qdev_prop_set_uint32(ams->gic, "num-cpu", smp_cpus); + /* Note that the num-irq property counts both internal and external + * interrupts; there are always 32 of the former (mandated by GIC spec= ). + */ + qdev_prop_set_uint32(ams->gic, "num-irq", NUM_IRQS + 32); + + if (type =3D=3D 3) { + uint32_t redist0_capacity =3D + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); + + nb_redist_regions =3D virt_gicv3_redist_region_count(ams); + + qdev_prop_set_uint32(ams->gic, "len-redist-region-count", + nb_redist_regions); + qdev_prop_set_uint32(ams->gic, "redist-region-count[0]", redist0_c= ount); + + if (nb_redist_regions =3D=3D 2) { + uint32_t redist1_capacity =3D + ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; + + qdev_prop_set_uint32(ams->gic, "redist-region-count[1]", + MIN(smp_cpus - redist0_count, redist1_capacity)); + } + } +} + +void init_gic_sysbus(ArmMachineState *ams) +{ + MachineState *ms =3D MACHINE(ams); + /* We create a standalone GIC */ + SysBusDevice *gicbusdev; + int type =3D ams->gic_version, i; + unsigned int smp_cpus =3D ms->smp.cpus; + uint32_t nb_redist_regions =3D 0; + + gicbusdev =3D SYS_BUS_DEVICE(ams->gic); + sysbus_mmio_map(gicbusdev, 0, ams->memmap[VIRT_GIC_DIST].base); + if (type =3D=3D 3) { + sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_REDIST].base); + if (nb_redist_regions =3D=3D 2) { + sysbus_mmio_map(gicbusdev, 2, + ams->memmap[VIRT_HIGH_GIC_REDIST2].base); + } + } else { + sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_CPU].base); + } + + /* Wire the outputs from each CPU's generic timer and the GICv3 + * maintenance interrupt signal to the appropriate GIC PPI inputs, + * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. + */ + for (i =3D 0; i < smp_cpus; i++) { + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); + int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; + int irq; + /* Mapping from the output timer irq lines from the CPU to the + * GIC PPI inputs we use for the virt board. + */ + const int timer_irq[] =3D { + [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, + [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, + [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, + [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, + }; + + for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { + qdev_connect_gpio_out(cpudev, irq, + qdev_get_gpio_in(ams->gic, + ppibase + timer_irq[irq= ])); + } + + if (type =3D=3D 3) { + qemu_irq irq =3D qdev_get_gpio_in(ams->gic, + ppibase + ARCH_GIC_MAINT_IRQ); + qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", + 0, irq); + } + + qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, + qdev_get_gpio_in(ams->gic, ppibase + + VIRTUAL_PMU_IRQ)); + + sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); + sysbus_connect_irq(gicbusdev, i + smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); + sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); + sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, + qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); + } +} + static char *virt_get_gic_version(Object *obj, Error **errp) { ArmMachineState *ams =3D ARM_MACHINE(obj); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b9689b0f0c..f971f49bcf 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -672,103 +672,14 @@ static void set_gic_virt_sysbus(VirtMachineState *vm= s) =20 static void create_gic(VirtMachineState *vms) { - MachineState *ms =3D MACHINE(vms); ArmMachineState *ams =3D ARM_MACHINE(vms); - /* We create a standalone GIC */ - SysBusDevice *gicbusdev; - const char *gictype; - int type =3D ams->gic_version, i; - unsigned int smp_cpus =3D ms->smp.cpus; - uint32_t nb_redist_regions =3D 0; - - gictype =3D (type =3D=3D 3) ? gicv3_class_name() : gic_class_name(); - - ams->gic =3D qdev_create(NULL, gictype); - qdev_prop_set_uint32(ams->gic, "revision", type); - qdev_prop_set_uint32(ams->gic, "num-cpu", smp_cpus); - /* Note that the num-irq property counts both internal and external - * interrupts; there are always 32 of the former (mandated by GIC spec= ). - */ - qdev_prop_set_uint32(ams->gic, "num-irq", NUM_IRQS + 32); =20 - if (type =3D=3D 3) { - uint32_t redist0_capacity =3D - ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; - uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); - - nb_redist_regions =3D virt_gicv3_redist_region_count(ams); - - qdev_prop_set_uint32(ams->gic, "len-redist-region-count", - nb_redist_regions); - qdev_prop_set_uint32(ams->gic, "redist-region-count[0]", redist0_c= ount); - - if (nb_redist_regions =3D=3D 2) { - uint32_t redist1_capacity =3D - ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST= _SIZE; - - qdev_prop_set_uint32(ams->gic, "redist-region-count[1]", - MIN(smp_cpus - redist0_count, redist1_capacity)); - } - } + qdev_create_gic(ams); qdev_gic_set_secure_bit(vms); qdev_gic_set_virt_bit(vms); qdev_init_nofail(ams->gic); - gicbusdev =3D SYS_BUS_DEVICE(ams->gic); - sysbus_mmio_map(gicbusdev, 0, ams->memmap[VIRT_GIC_DIST].base); - if (type =3D=3D 3) { - sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_REDIST].base); - if (nb_redist_regions =3D=3D 2) { - sysbus_mmio_map(gicbusdev, 2, - ams->memmap[VIRT_HIGH_GIC_REDIST2].base); - } - } else { - sysbus_mmio_map(gicbusdev, 1, ams->memmap[VIRT_GIC_CPU].base); - } - - /* Wire the outputs from each CPU's generic timer and the GICv3 - * maintenance interrupt signal to the appropriate GIC PPI inputs, - * and the GIC's IRQ/FIQ/VIRQ/VFIQ interrupt outputs to the CPU's inpu= ts. - */ - for (i =3D 0; i < smp_cpus; i++) { - DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); - int ppibase =3D NUM_IRQS + i * GIC_INTERNAL + GIC_NR_SGIS; - int irq; - /* Mapping from the output timer irq lines from the CPU to the - * GIC PPI inputs we use for the virt board. - */ - const int timer_irq[] =3D { - [GTIMER_PHYS] =3D ARCH_TIMER_NS_EL1_IRQ, - [GTIMER_VIRT] =3D ARCH_TIMER_VIRT_IRQ, - [GTIMER_HYP] =3D ARCH_TIMER_NS_EL2_IRQ, - [GTIMER_SEC] =3D ARCH_TIMER_S_EL1_IRQ, - }; - - for (irq =3D 0; irq < ARRAY_SIZE(timer_irq); irq++) { - qdev_connect_gpio_out(cpudev, irq, - qdev_get_gpio_in(ams->gic, - ppibase + timer_irq[irq= ])); - } - - if (type =3D=3D 3) { - qemu_irq irq =3D qdev_get_gpio_in(ams->gic, - ppibase + ARCH_GIC_MAINT_IRQ); - qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", - 0, irq); - } - - qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0, - qdev_get_gpio_in(ams->gic, ppibase - + VIRTUAL_PMU_IRQ)); - - sysbus_connect_irq(gicbusdev, i, qdev_get_gpio_in(cpudev, ARM_CPU_= IRQ)); - sysbus_connect_irq(gicbusdev, i + smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_FIQ)); - sysbus_connect_irq(gicbusdev, i + 2 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VIRQ)); - sysbus_connect_irq(gicbusdev, i + 3 * smp_cpus, - qdev_get_gpio_in(cpudev, ARM_CPU_VFIQ)); - } =20 + init_gic_sysbus(ams); set_gic_virt_sysbus(vms); fdt_add_gic_node(vms); fdt_gic_set_virt_extension(vms); diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index f8bde03cc3..9ba51c4882 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -108,6 +108,10 @@ typedef struct { #define ARM_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(ArmMachineClass, klass, TYPE_ARM_MACHINE) =20 +void qdev_create_gic(ArmMachineState *ams); + +void init_gic_sysbus(ArmMachineState *ams); + /* Return the number of used redistributor regions */ static inline int virt_gicv3_redist_region_count(ArmMachineState *ams) { --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925496185986.1939807743488; Sun, 16 Feb 2020 23:44:56 -0800 (PST) Received: from localhost ([::1]:41460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b5L-00012c-0q for importer@patchew.org; Mon, 17 Feb 2020 02:44:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39382) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b2x-0004J5-UB for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:29 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2v-0000Wk-S1 for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:27 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3227 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2r-0000Mi-NK; Mon, 17 Feb 2020 02:42:22 -0500 Received: from DGGEMS406-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 06E233DDC85F7053ED44; Mon, 17 Feb 2020 15:42:18 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS406-HUB.china.huawei.com (10.3.19.206) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:09 +0800 From: Xu Yandong To: Subject: [PATCH RFC 11/16] hw/arm: move shared psci_enable and claim_edge_triggered_timers member to ArmMachine Date: Mon, 17 Feb 2020 02:51:23 -0500 Message-ID: <1581925888-103620-12-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, "Michael S. Tsirkin" , Xu Yandong , qemu-devel@nongnu.org, Shannon Zhao , qemu-arm@nongnu.org, Igor Mammedov , wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move psci_enable member from VirtMachineState to ArmMachineState. Move claim_edge_triggered_timers member from VirtMachineClass to ArmMachineClass. Cc: Michael S. Tsirkin Cc: Igor Mammedov Cc: Shannon Zhao Signed-off-by: Xu Yandong --- hw/arm/virt-acpi-build.c | 7 ++++--- hw/arm/virt.c | 14 +++++++------- include/hw/arm/arm.h | 2 ++ include/hw/arm/virt.h | 2 -- 4 files changed, 13 insertions(+), 12 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 770c53f5d0..f2de897694 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -570,12 +570,12 @@ build_srat(GArray *table_data, BIOSLinker *linker, Vi= rtMachineState *vms) static void build_gtdt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) { - VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); + ArmMachineClass *amc =3D ARM_MACHINE_GET_CLASS(ARM_MACHINE(vms)); int gtdt_start =3D table_data->len; AcpiGenericTimerTable *gtdt; uint32_t irqflags; =20 - if (vmc->claim_edge_triggered_timers) { + if (amc->claim_edge_triggered_timers) { irqflags =3D ACPI_GTDT_INTERRUPT_MODE_EDGE; } else { irqflags =3D ACPI_GTDT_INTERRUPT_MODE_LEVEL; @@ -696,6 +696,7 @@ build_madt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) static void build_fadt_rev5(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms, unsigned dsdt_tbl_offse= t) { + ArmMachineState *ams =3D ARM_MACHINE(vms); /* ACPI v5.1 */ AcpiFadtData fadt =3D { .rev =3D 5, @@ -704,7 +705,7 @@ static void build_fadt_rev5(GArray *table_data, BIOSLin= ker *linker, .xdsdt_tbl_offset =3D &dsdt_tbl_offset, }; =20 - switch (vms->psci_conduit) { + switch (ams->psci_conduit) { case QEMU_PSCI_CONDUIT_DISABLED: fadt.arm_boot_arch =3D 0; break; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f971f49bcf..2c0dfb2695 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1576,11 +1576,11 @@ static void machvirt_init(MachineState *machine) * because if we're using KVM then we must use HVC). */ if (vms->secure && firmware_loaded) { - vms->psci_conduit =3D QEMU_PSCI_CONDUIT_DISABLED; + ams->psci_conduit =3D QEMU_PSCI_CONDUIT_DISABLED; } else if (vms->virt) { - vms->psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; + ams->psci_conduit =3D QEMU_PSCI_CONDUIT_SMC; } else { - vms->psci_conduit =3D QEMU_PSCI_CONDUIT_HVC; + ams->psci_conduit =3D QEMU_PSCI_CONDUIT_HVC; } =20 /* The maximum number of CPUs depends on the GIC version, or on how @@ -1641,8 +1641,8 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, false, "has_el2", NULL); } =20 - if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { - object_property_set_int(cpuobj, vms->psci_conduit, + if (ams->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED) { + object_property_set_int(cpuobj, ams->psci_conduit, "psci-conduit", NULL); =20 /* Secondary CPUs start in PSCI powered-down state */ @@ -2186,14 +2186,14 @@ DEFINE_VIRT_MACHINE(2, 9) =20 static void virt_machine_2_8_options(MachineClass *mc) { - VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + ArmMachineClass *amc =3D ARM_MACHINE_CLASS(OBJECT_CLASS(mc)); =20 virt_machine_2_9_options(mc); compat_props_add(mc->compat_props, hw_compat_2_8, hw_compat_2_8_len); /* For 2.8 and earlier we falsely claimed in the DT that * our timers were edge-triggered, not level-triggered. */ - vmc->claim_edge_triggered_timers =3D true; + amc->claim_edge_triggered_timers =3D true; } DEFINE_VIRT_MACHINE(2, 8) =20 diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 9ba51c4882..bb3680e583 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -86,6 +86,7 @@ typedef struct MemMapEntry { =20 typedef struct { MachineClass parent; + bool claim_edge_triggered_timers; } ArmMachineClass; =20 typedef struct { @@ -97,6 +98,7 @@ typedef struct { void *fdt; int fdt_size; uint32_t gic_phandle; + int psci_conduit; DeviceState *gic; } ArmMachineState; =20 diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 393afb7faf..ad94634038 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -50,7 +50,6 @@ typedef struct { bool disallow_affinity_adjustment; bool no_its; bool no_pmu; - bool claim_edge_triggered_timers; bool smbios_old_sys_ver; bool no_highmem_ecam; bool no_ged; /* Machines < 4.2 has no support for ACPI GED device */ @@ -73,7 +72,6 @@ typedef struct { uint32_t clock_phandle; uint32_t msi_phandle; uint32_t iommu_phandle; - int psci_conduit; hwaddr highest_gpa; DeviceState *acpi_dev; Notifier powerdown_notifier; --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 17 Feb 2020 02:42:23 -0500 Received: from DGGEMS407-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 7A5DEB51FF8740FA55DE; Mon, 17 Feb 2020 15:42:20 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS407-HUB.china.huawei.com (10.3.19.207) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:10 +0800 From: Xu Yandong To: Subject: [PATCH RFC 12/16] hw/arm: move shared devices related functions to arm.c and export them Date: Mon, 17 Feb 2020 02:51:24 -0500 Message-ID: <1581925888-103620-13-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move device related functions to arm.c, include RTC(pl031), UART(pl011), virtio devices. Signed-off-by: Xu Yandong --- hw/arm/arm.c | 137 +++++++++++++++++++++++++++++++++++++ hw/arm/virt.c | 156 +++--------------------------------------- include/hw/arm/arm.h | 8 +++ include/hw/arm/virt.h | 1 - 4 files changed, 153 insertions(+), 149 deletions(-) diff --git a/hw/arm/arm.c b/hw/arm/arm.c index c51bf513d2..6751c6a624 100644 --- a/hw/arm/arm.c +++ b/hw/arm/arm.c @@ -145,6 +145,143 @@ void init_gic_sysbus(ArmMachineState *ams) } } =20 +void create_uart(const ArmMachineState *ams, int uart, + MemoryRegion *mem, Chardev *chr) +{ + char *nodename; + hwaddr base =3D ams->memmap[uart].base; + hwaddr size =3D ams->memmap[uart].size; + int irq =3D ams->irqmap[uart]; + const char compat[] =3D "arm,pl011\0arm,primecell"; + const char clocknames[] =3D "uartclk\0apb_pclk"; + DeviceState *dev =3D qdev_create(NULL, "pl011"); + SysBusDevice *s =3D SYS_BUS_DEVICE(dev); + + qdev_prop_set_chr(dev, "chardev", chr); + qdev_init_nofail(dev); + memory_region_add_subregion(mem, base, + sysbus_mmio_get_region(s, 0)); + sysbus_connect_irq(s, 0, qdev_get_gpio_in(ams->gic, irq)); + + nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); + qemu_fdt_add_subnode(ams->fdt, nodename); + /* Note that we can't use setprop_string because of the embedded NUL */ + qemu_fdt_setprop(ams->fdt, nodename, "compatible", + compat, sizeof(compat)); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cells(ams->fdt, nodename, "clocks", + ams->clock_phandle, ams->clock_phandle); + qemu_fdt_setprop(ams->fdt, nodename, "clock-names", + clocknames, sizeof(clocknames)); + + if (uart =3D=3D VIRT_UART) { + qemu_fdt_setprop_string(ams->fdt, "/chosen", "stdout-path", nodena= me); + } else { + /* Mark as not usable by the normal world */ + qemu_fdt_setprop_string(ams->fdt, nodename, "status", "disabled"); + qemu_fdt_setprop_string(ams->fdt, nodename, "secure-status", "okay= "); + + qemu_fdt_add_subnode(ams->fdt, "/secure-chosen"); + qemu_fdt_setprop_string(ams->fdt, "/secure-chosen", "stdout-path", + nodename); + } + + g_free(nodename); +} + +void create_rtc(const ArmMachineState *ams) +{ + char *nodename; + hwaddr base =3D ams->memmap[VIRT_RTC].base; + hwaddr size =3D ams->memmap[VIRT_RTC].size; + int irq =3D ams->irqmap[VIRT_RTC]; + const char compat[] =3D "arm,pl031\0arm,primecell"; + + sysbus_create_simple("pl031", base, qdev_get_gpio_in(ams->gic, irq)); + + nodename =3D g_strdup_printf("/pl031@%" PRIx64, base); + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop(ams->fdt, nodename, "compatible", compat, sizeof(comp= at)); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_LEVEL_HI); + qemu_fdt_setprop_cell(ams->fdt, nodename, "clocks", ams->clock_phandle= ); + qemu_fdt_setprop_string(ams->fdt, nodename, "clock-names", "apb_pclk"); + g_free(nodename); +} + +void create_virtio_devices(const ArmMachineState *ams) +{ + int i; + hwaddr size =3D ams->memmap[VIRT_MMIO].size; + + /* We create the transports in forwards order. Since qbus_realize() + * prepends (not appends) new child buses, the incrementing loop below= will + * create a list of virtio-mmio buses with decreasing base addresses. + * + * When a -device option is processed from the command line, + * qbus_find_recursive() picks the next free virtio-mmio bus in forwar= ds + * order. The upshot is that -device options in increasing command line + * order are mapped to virtio-mmio buses with decreasing base addresse= s. + * + * When this code was originally written, that arrangement ensured tha= t the + * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, et= c) to + * the first -device on the command line. (The end-to-end order is a + * function of this loop, qbus_realize(), qbus_find_recursive(), and t= he + * guest kernel's name-to-address assignment strategy.) + * + * Meanwhile, the kernel's traversal seems to have been reversed; see = eg. + * the message, if not necessarily the code, of commit 70161ff336. + * Therefore the loop now establishes the inverse of the original inte= nt. + * + * Unfortunately, we can't counteract the kernel change by reversing t= he + * loop; it would break existing command lines. + * + * In any case, the kernel makes no guarantee about the stability of + * enumeration order of virtio devices (as demonstrated by it changing + * between kernel versions). For reliable and stable identification + * of disks users must use UUIDs or similar mechanisms. + */ + for (i =3D 0; i < NUM_VIRTIO_TRANSPORTS; i++) { + int irq =3D ams->irqmap[VIRT_MMIO] + i; + hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; + + sysbus_create_simple("virtio-mmio", base, + qdev_get_gpio_in(ams->gic, irq)); + } + + /* We add dtb nodes in reverse order so that they appear in the finish= ed + * device tree lowest address first. + * + * Note that this mapping is independent of the loop above. The previo= us + * loop influences virtio device to virtio transport assignment, where= as + * this loop controls how virtio transports are laid out in the dtb. + */ + for (i =3D NUM_VIRTIO_TRANSPORTS - 1; i >=3D 0; i--) { + char *nodename; + int irq =3D ams->irqmap[VIRT_MMIO] + i; + hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; + + nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, + "compatible", "virtio,mmio"); + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, base, 2, size); + qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", + GIC_FDT_IRQ_TYPE_SPI, irq, + GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); + qemu_fdt_setprop(ams->fdt, nodename, "dma-coherent", NULL, 0); + g_free(nodename); + } +} + static char *virt_get_gic_version(Object *obj, Error **errp) { ArmMachineState *ams =3D ARM_MACHINE(obj); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2c0dfb2695..b3267b873a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -231,14 +231,14 @@ static void create_fdt(VirtMachineState *vms) * optional but in practice if you omit them the kernel refuses to * probe for the device. */ - vms->clock_phandle =3D qemu_fdt_alloc_phandle(fdt); + ams->clock_phandle =3D qemu_fdt_alloc_phandle(fdt); qemu_fdt_add_subnode(fdt, "/apb-pclk"); qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", "clk24mhz"); - qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", vms->clock_phandle); + qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", ams->clock_phandle); =20 if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -687,79 +687,6 @@ static void create_gic(VirtMachineState *vms) gic_set_msi_interrupt(vms); } =20 -static void create_uart(const VirtMachineState *vms, int uart, - MemoryRegion *mem, Chardev *chr) -{ - char *nodename; - const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D ams->memmap[uart].base; - hwaddr size =3D ams->memmap[uart].size; - int irq =3D ams->irqmap[uart]; - const char compat[] =3D "arm,pl011\0arm,primecell"; - const char clocknames[] =3D "uartclk\0apb_pclk"; - DeviceState *dev =3D qdev_create(NULL, "pl011"); - SysBusDevice *s =3D SYS_BUS_DEVICE(dev); - - qdev_prop_set_chr(dev, "chardev", chr); - qdev_init_nofail(dev); - memory_region_add_subregion(mem, base, - sysbus_mmio_get_region(s, 0)); - sysbus_connect_irq(s, 0, qdev_get_gpio_in(ams->gic, irq)); - - nodename =3D g_strdup_printf("/pl011@%" PRIx64, base); - qemu_fdt_add_subnode(ams->fdt, nodename); - /* Note that we can't use setprop_string because of the embedded NUL */ - qemu_fdt_setprop(ams->fdt, nodename, "compatible", - compat, sizeof(compat)); - qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, base, 2, size); - qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cells(ams->fdt, nodename, "clocks", - vms->clock_phandle, vms->clock_phandle); - qemu_fdt_setprop(ams->fdt, nodename, "clock-names", - clocknames, sizeof(clocknames)); - - if (uart =3D=3D VIRT_UART) { - qemu_fdt_setprop_string(ams->fdt, "/chosen", "stdout-path", nodena= me); - } else { - /* Mark as not usable by the normal world */ - qemu_fdt_setprop_string(ams->fdt, nodename, "status", "disabled"); - qemu_fdt_setprop_string(ams->fdt, nodename, "secure-status", "okay= "); - - qemu_fdt_add_subnode(ams->fdt, "/secure-chosen"); - qemu_fdt_setprop_string(ams->fdt, "/secure-chosen", "stdout-path", - nodename); - } - - g_free(nodename); -} - -static void create_rtc(const VirtMachineState *vms) -{ - char *nodename; - const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr base =3D ams->memmap[VIRT_RTC].base; - hwaddr size =3D ams->memmap[VIRT_RTC].size; - int irq =3D ams->irqmap[VIRT_RTC]; - const char compat[] =3D "arm,pl031\0arm,primecell"; - - sysbus_create_simple("pl031", base, qdev_get_gpio_in(ams->gic, irq)); - - nodename =3D g_strdup_printf("/pl031@%" PRIx64, base); - qemu_fdt_add_subnode(ams->fdt, nodename); - qemu_fdt_setprop(ams->fdt, nodename, "compatible", compat, sizeof(comp= at)); - qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, base, 2, size); - qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cell(ams->fdt, nodename, "clocks", vms->clock_phandle= ); - qemu_fdt_setprop_string(ams->fdt, nodename, "clock-names", "apb_pclk"); - g_free(nodename); -} - static DeviceState *gpio_key_dev; static void virt_powerdown_req(Notifier *n, void *opaque) { @@ -797,7 +724,7 @@ static void create_gpio(const VirtMachineState *vms) qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", GIC_FDT_IRQ_TYPE_SPI, irq, GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_cell(ams->fdt, nodename, "clocks", vms->clock_phandle= ); + qemu_fdt_setprop_cell(ams->fdt, nodename, "clocks", ams->clock_phandle= ); qemu_fdt_setprop_string(ams->fdt, nodename, "clock-names", "apb_pclk"); qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", phandle); =20 @@ -818,73 +745,6 @@ static void create_gpio(const VirtMachineState *vms) g_free(nodename); } =20 -static void create_virtio_devices(const VirtMachineState *vms) -{ - int i; - const ArmMachineState *ams =3D ARM_MACHINE(vms); - hwaddr size =3D ams->memmap[VIRT_MMIO].size; - - /* We create the transports in forwards order. Since qbus_realize() - * prepends (not appends) new child buses, the incrementing loop below= will - * create a list of virtio-mmio buses with decreasing base addresses. - * - * When a -device option is processed from the command line, - * qbus_find_recursive() picks the next free virtio-mmio bus in forwar= ds - * order. The upshot is that -device options in increasing command line - * order are mapped to virtio-mmio buses with decreasing base addresse= s. - * - * When this code was originally written, that arrangement ensured tha= t the - * guest Linux kernel would give the lowest "name" (/dev/vda, eth0, et= c) to - * the first -device on the command line. (The end-to-end order is a - * function of this loop, qbus_realize(), qbus_find_recursive(), and t= he - * guest kernel's name-to-address assignment strategy.) - * - * Meanwhile, the kernel's traversal seems to have been reversed; see = eg. - * the message, if not necessarily the code, of commit 70161ff336. - * Therefore the loop now establishes the inverse of the original inte= nt. - * - * Unfortunately, we can't counteract the kernel change by reversing t= he - * loop; it would break existing command lines. - * - * In any case, the kernel makes no guarantee about the stability of - * enumeration order of virtio devices (as demonstrated by it changing - * between kernel versions). For reliable and stable identification - * of disks users must use UUIDs or similar mechanisms. - */ - for (i =3D 0; i < NUM_VIRTIO_TRANSPORTS; i++) { - int irq =3D ams->irqmap[VIRT_MMIO] + i; - hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; - - sysbus_create_simple("virtio-mmio", base, - qdev_get_gpio_in(ams->gic, irq)); - } - - /* We add dtb nodes in reverse order so that they appear in the finish= ed - * device tree lowest address first. - * - * Note that this mapping is independent of the loop above. The previo= us - * loop influences virtio device to virtio transport assignment, where= as - * this loop controls how virtio transports are laid out in the dtb. - */ - for (i =3D NUM_VIRTIO_TRANSPORTS - 1; i >=3D 0; i--) { - char *nodename; - int irq =3D ams->irqmap[VIRT_MMIO] + i; - hwaddr base =3D ams->memmap[VIRT_MMIO].base + i * size; - - nodename =3D g_strdup_printf("/virtio_mmio@%" PRIx64, base); - qemu_fdt_add_subnode(ams->fdt, nodename); - qemu_fdt_setprop_string(ams->fdt, nodename, - "compatible", "virtio,mmio"); - qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, base, 2, size); - qemu_fdt_setprop_cells(ams->fdt, nodename, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irq, - GIC_FDT_IRQ_FLAGS_EDGE_LO_HI); - qemu_fdt_setprop(ams->fdt, nodename, "dma-coherent", NULL, 0); - g_free(nodename); - } -} - #define VIRT_FLASH_SECTOR_SIZE (256 * KiB) =20 static PFlashCFI01 *virt_flash_create1(VirtMachineState *vms, @@ -1151,7 +1011,7 @@ static void create_smmu(const VirtMachineState *vms, qemu_fdt_setprop(ams->fdt, node, "interrupt-names", irq_names, sizeof(irq_names)); =20 - qemu_fdt_setprop_cell(ams->fdt, node, "clocks", vms->clock_phandle); + qemu_fdt_setprop_cell(ams->fdt, node, "clocks", ams->clock_phandle); qemu_fdt_setprop_string(ams->fdt, node, "clock-names", "apb_pclk"); qemu_fdt_setprop(ams->fdt, node, "dma-coherent", NULL, 0); =20 @@ -1709,16 +1569,16 @@ static void machvirt_init(MachineState *machine) =20 fdt_add_pmu_nodes(vms); =20 - create_uart(vms, VIRT_UART, sysmem, serial_hd(0)); + create_uart(ams, VIRT_UART, sysmem, serial_hd(0)); =20 if (vms->secure) { create_secure_ram(vms, secure_sysmem); - create_uart(vms, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); + create_uart(ams, VIRT_SECURE_UART, secure_sysmem, serial_hd(1)); } =20 vms->highmem_ecam &=3D vms->highmem && (!firmware_loaded || aarch64); =20 - create_rtc(vms); + create_rtc(ams); =20 create_pcie(vms); =20 @@ -1736,7 +1596,7 @@ static void machvirt_init(MachineState *machine) * (which will be automatically plugged in to the transports). If * no backend is created the transport will just sit harmlessly idle. */ - create_virtio_devices(vms); + create_virtio_devices(ams); =20 vms->fw_cfg =3D create_fw_cfg(vms, &address_space_memory); rom_set_fw(vms->fw_cfg); diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index bb3680e583..8fec23985e 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -97,6 +97,7 @@ typedef struct { int smp_cpus; void *fdt; int fdt_size; + uint32_t clock_phandle; uint32_t gic_phandle; int psci_conduit; DeviceState *gic; @@ -114,6 +115,13 @@ void qdev_create_gic(ArmMachineState *ams); =20 void init_gic_sysbus(ArmMachineState *ams); =20 +void create_uart(const ArmMachineState *ams, int uart, + MemoryRegion *mem, Chardev *chr); + +void create_rtc(const ArmMachineState *ams); + +void create_virtio_devices(const ArmMachineState *ams); + /* Return the number of used redistributor regions */ static inline int virt_gicv3_redist_region_count(ArmMachineState *ams) { diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index ad94634038..086a27682f 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -69,7 +69,6 @@ typedef struct { bool virt; VirtIOMMUType iommu; struct arm_boot_info bootinfo; - uint32_t clock_phandle; uint32_t msi_phandle; uint32_t iommu_phandle; hwaddr highest_gpa; --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925766807297.77199830598397; Sun, 16 Feb 2020 23:49:26 -0800 (PST) Received: from localhost ([::1]:41542 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b9h-0008E6-3P for importer@patchew.org; Mon, 17 Feb 2020 02:49:25 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39524) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b33-0004UH-9U for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:36 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b30-0000dH-5D for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:33 -0500 Received: from szxga07-in.huawei.com ([45.249.212.35]:45544 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2r-0000Ot-JZ; Mon, 17 Feb 2020 02:42:22 -0500 Received: from DGGEMS404-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6A3993AAADE75E5B0609; Mon, 17 Feb 2020 15:42:19 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS404-HUB.china.huawei.com (10.3.19.204) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:11 +0800 From: Xu Yandong To: Subject: [PATCH RFC 13/16] hw/arm: move shared fdt related functions to arm.c and export them Date: Mon, 17 Feb 2020 02:51:25 -0500 Message-ID: <1581925888-103620-14-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.35 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move fdt related functions that will be shared between VIRT and non-VIRT machine types to arm.c. Signed-off-by: Xu Yandong --- hw/arm/arm.c | 226 ++++++++++++++++++++++++++++++++++++++++ hw/arm/virt.c | 238 +------------------------------------------ include/hw/arm/arm.h | 8 ++ 3 files changed, 238 insertions(+), 234 deletions(-) diff --git a/hw/arm/arm.c b/hw/arm/arm.c index 6751c6a624..4bffee0f37 100644 --- a/hw/arm/arm.c +++ b/hw/arm/arm.c @@ -39,6 +39,232 @@ #include "hw/intc/arm_gic.h" #include "kvm_arm.h" =20 +void create_fdt(ArmMachineState *ams) +{ + MachineState *ms =3D MACHINE(ams); + int nb_numa_nodes =3D ms->numa_state->num_nodes; + void *fdt =3D create_device_tree(&ams->fdt_size); + + if (!fdt) { + error_report("create_device_tree() failed"); + exit(1); + } + + ams->fdt =3D fdt; + + /* Header */ + qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); + qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); + qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); + + /* /chosen must exist for load_dtb to fill in necessary properties lat= er */ + qemu_fdt_add_subnode(fdt, "/chosen"); + + /* Clock node, for the benefit of the UART. The kernel device tree + * binding documentation claims the PL011 node clock properties are + * optional but in practice if you omit them the kernel refuses to + * probe for the device. + */ + ams->clock_phandle =3D qemu_fdt_alloc_phandle(fdt); + qemu_fdt_add_subnode(fdt, "/apb-pclk"); + qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); + qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); + qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", + "clk24mhz"); + qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", ams->clock_phandle); + + if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { + int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); + uint32_t *matrix =3D g_malloc0(size); + int idx, i, j; + + for (i =3D 0; i < nb_numa_nodes; i++) { + for (j =3D 0; j < nb_numa_nodes; j++) { + idx =3D (i * nb_numa_nodes + j) * 3; + matrix[idx + 0] =3D cpu_to_be32(i); + matrix[idx + 1] =3D cpu_to_be32(j); + matrix[idx + 2] =3D + cpu_to_be32(ms->numa_state->nodes[i].distance[j]); + } + } + + qemu_fdt_add_subnode(fdt, "/distance-map"); + qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", + "numa-distance-map-v1"); + qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", + matrix, size); + g_free(matrix); + } +} + +void fdt_add_timer_nodes(const ArmMachineState *ams) +{ + /* On real hardware these interrupts are level-triggered. + * On KVM they were edge-triggered before host kernel version 4.4, + * and level-triggered afterwards. + * On emulated QEMU they are level-triggered. + * + * Getting the DTB info about them wrong is awkward for some + * guest kernels: + * pre-4.8 ignore the DT and leave the interrupt configured + * with whatever the GIC reset value (or the bootloader) left it at + * 4.8 before rc6 honour the incorrect data by programming it back + * into the GIC, causing problems + * 4.8rc6 and later ignore the DT and always write "level triggered" + * into the GIC + * + * For backwards-compatibility, virt-2.8 and earlier will continue + * to say these are edge-triggered, but later machines will report + * the correct information. + */ + ARMCPU *armcpu; + ArmMachineClass *amc =3D ARM_MACHINE_GET_CLASS(ams); + uint32_t irqflags =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; + + if (amc->claim_edge_triggered_timers) { + irqflags =3D GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; + } + + if (ams->gic_version =3D=3D 2) { + irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, + GIC_FDT_IRQ_PPI_CPU_WIDTH, + (1 << ams->smp_cpus) - 1); + } + + qemu_fdt_add_subnode(ams->fdt, "/timer"); + + armcpu =3D ARM_CPU(qemu_get_cpu(0)); + if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { + const char compat[] =3D "arm,armv8-timer\0arm,armv7-timer"; + qemu_fdt_setprop(ams->fdt, "/timer", "compatible", + compat, sizeof(compat)); + } else { + qemu_fdt_setprop_string(ams->fdt, "/timer", "compatible", + "arm,armv7-timer"); + } + qemu_fdt_setprop(ams->fdt, "/timer", "always-on", NULL, 0); + qemu_fdt_setprop_cells(ams->fdt, "/timer", "interrupts", + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflag= s, + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqfla= gs, + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, + GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqfla= gs); +} + +void fdt_add_cpu_nodes(const ArmMachineState *ams) +{ + int cpu; + int addr_cells =3D 1; + const MachineState *ms =3D MACHINE(ams); + + /* + * From Documentation/devicetree/bindings/arm/cpus.txt + * On ARM v8 64-bit systems value should be set to 2, + * that corresponds to the MPIDR_EL1 register size. + * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs + * in the system, #address-cells can be set to 1, since + * MPIDR_EL1[63:32] bits are not used for CPUs + * identification. + * + * Here we actually don't know whether our system is 32- or 64-bit on= e. + * The simplest way to go is to examine affinity IDs of all our CPUs.= If + * at least one of them has Aff3 populated, we set #address-cells to = 2. + */ + for (cpu =3D 0; cpu < ams->smp_cpus; cpu++) { + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + + if (armcpu->mp_affinity & ARM_AFF3_MASK) { + addr_cells =3D 2; + break; + } + } + + qemu_fdt_add_subnode(ams->fdt, "/cpus"); + qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#address-cells", addr_cells); + qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#size-cells", 0x0); + + for (cpu =3D ams->smp_cpus - 1; cpu >=3D 0; cpu--) { + char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); + ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); + CPUState *cs =3D CPU(armcpu); + + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_string(ams->fdt, nodename, "device_type", "cpu"); + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", + armcpu->dtb_compatible); + + if (ams->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED + && ams->smp_cpus > 1) { + qemu_fdt_setprop_string(ams->fdt, nodename, + "enable-method", "psci"); + } + + if (addr_cells =3D=3D 2) { + qemu_fdt_setprop_u64(ams->fdt, nodename, "reg", + armcpu->mp_affinity); + } else { + qemu_fdt_setprop_cell(ams->fdt, nodename, "reg", + armcpu->mp_affinity); + } + + if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { + qemu_fdt_setprop_cell(ams->fdt, nodename, "numa-node-id", + ms->possible_cpus->cpus[cs->cpu_index].props.node_id); + } + + g_free(nodename); + } +} + +void fdt_add_gic_node(ArmMachineState *ams) +{ + char *nodename; + + ams->gic_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); + qemu_fdt_setprop_cell(ams->fdt, "/", "interrupt-parent", ams->gic_phan= dle); + + nodename =3D g_strdup_printf("/intc@%" PRIx64, + ams->memmap[VIRT_GIC_DIST].base); + qemu_fdt_add_subnode(ams->fdt, nodename); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#interrupt-cells", 3); + qemu_fdt_setprop(ams->fdt, nodename, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#address-cells", 0x2); + qemu_fdt_setprop_cell(ams->fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop(ams->fdt, nodename, "ranges", NULL, 0); + if (ams->gic_version =3D=3D 3) { + int nb_redist_regions =3D virt_gicv3_redist_region_count(ams); + + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", + "arm,gic-v3"); + + qemu_fdt_setprop_cell(ams->fdt, nodename, + "#redistributor-regions", nb_redist_regions); + + if (nb_redist_regions =3D=3D 1) { + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, ams->memmap[VIRT_GIC_DIST].bas= e, + 2, ams->memmap[VIRT_GIC_DIST].siz= e, + 2, ams->memmap[VIRT_GIC_REDIST].b= ase, + 2, ams->memmap[VIRT_GIC_REDIST].s= ize); + } else { + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, ams->memmap[VIRT_GIC_DIST].base, + 2, ams->memmap[VIRT_GIC_DIST].size, + 2, ams->memmap[VIRT_GIC_REDIST].base, + 2, ams->memmap[VIRT_GIC_REDIST].size, + 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, + 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); + } + } else { + /* 'cortex-a15-gic' means 'GIC v2' */ + qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", + "arm,cortex-a15-gic"); + } + + qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", ams->gic_phandle); + g_free(nodename); +} + void qdev_create_gic(ArmMachineState *ams) { MachineState *ms =3D MACHINE(ams); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index b3267b873a..11e753906b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,186 +204,6 @@ static bool cpu_type_valid(const char *cpu) return false; } =20 -static void create_fdt(VirtMachineState *vms) -{ - MachineState *ms =3D MACHINE(vms); - ArmMachineState *ams =3D ARM_MACHINE(vms); - int nb_numa_nodes =3D ms->numa_state->num_nodes; - void *fdt =3D create_device_tree(&ams->fdt_size); - - if (!fdt) { - error_report("create_device_tree() failed"); - exit(1); - } - - ams->fdt =3D fdt; - - /* Header */ - qemu_fdt_setprop_string(fdt, "/", "compatible", "linux,dummy-virt"); - qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); - qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); - - /* /chosen must exist for load_dtb to fill in necessary properties lat= er */ - qemu_fdt_add_subnode(fdt, "/chosen"); - - /* Clock node, for the benefit of the UART. The kernel device tree - * binding documentation claims the PL011 node clock properties are - * optional but in practice if you omit them the kernel refuses to - * probe for the device. - */ - ams->clock_phandle =3D qemu_fdt_alloc_phandle(fdt); - qemu_fdt_add_subnode(fdt, "/apb-pclk"); - qemu_fdt_setprop_string(fdt, "/apb-pclk", "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, "/apb-pclk", "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, "/apb-pclk", "clock-frequency", 24000000); - qemu_fdt_setprop_string(fdt, "/apb-pclk", "clock-output-names", - "clk24mhz"); - qemu_fdt_setprop_cell(fdt, "/apb-pclk", "phandle", ams->clock_phandle); - - if (nb_numa_nodes > 0 && ms->numa_state->have_numa_distance) { - int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); - uint32_t *matrix =3D g_malloc0(size); - int idx, i, j; - - for (i =3D 0; i < nb_numa_nodes; i++) { - for (j =3D 0; j < nb_numa_nodes; j++) { - idx =3D (i * nb_numa_nodes + j) * 3; - matrix[idx + 0] =3D cpu_to_be32(i); - matrix[idx + 1] =3D cpu_to_be32(j); - matrix[idx + 2] =3D - cpu_to_be32(ms->numa_state->nodes[i].distance[j]); - } - } - - qemu_fdt_add_subnode(fdt, "/distance-map"); - qemu_fdt_setprop_string(fdt, "/distance-map", "compatible", - "numa-distance-map-v1"); - qemu_fdt_setprop(fdt, "/distance-map", "distance-matrix", - matrix, size); - g_free(matrix); - } -} - -static void fdt_add_timer_nodes(const VirtMachineState *vms) -{ - /* On real hardware these interrupts are level-triggered. - * On KVM they were edge-triggered before host kernel version 4.4, - * and level-triggered afterwards. - * On emulated QEMU they are level-triggered. - * - * Getting the DTB info about them wrong is awkward for some - * guest kernels: - * pre-4.8 ignore the DT and leave the interrupt configured - * with whatever the GIC reset value (or the bootloader) left it at - * 4.8 before rc6 honour the incorrect data by programming it back - * into the GIC, causing problems - * 4.8rc6 and later ignore the DT and always write "level triggered" - * into the GIC - * - * For backwards-compatibility, virt-2.8 and earlier will continue - * to say these are edge-triggered, but later machines will report - * the correct information. - */ - ARMCPU *armcpu; - ArmMachineState *ams =3D ARM_MACHINE(vms); - VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); - uint32_t irqflags =3D GIC_FDT_IRQ_FLAGS_LEVEL_HI; - - if (vmc->claim_edge_triggered_timers) { - irqflags =3D GIC_FDT_IRQ_FLAGS_EDGE_LO_HI; - } - - if (ams->gic_version =3D=3D 2) { - irqflags =3D deposit32(irqflags, GIC_FDT_IRQ_PPI_CPU_START, - GIC_FDT_IRQ_PPI_CPU_WIDTH, - (1 << ams->smp_cpus) - 1); - } - - qemu_fdt_add_subnode(ams->fdt, "/timer"); - - armcpu =3D ARM_CPU(qemu_get_cpu(0)); - if (arm_feature(&armcpu->env, ARM_FEATURE_V8)) { - const char compat[] =3D "arm,armv8-timer\0arm,armv7-timer"; - qemu_fdt_setprop(ams->fdt, "/timer", "compatible", - compat, sizeof(compat)); - } else { - qemu_fdt_setprop_string(ams->fdt, "/timer", "compatible", - "arm,armv7-timer"); - } - qemu_fdt_setprop(ams->fdt, "/timer", "always-on", NULL, 0); - qemu_fdt_setprop_cells(ams->fdt, "/timer", "interrupts", - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_S_EL1_IRQ, irqflag= s, - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL1_IRQ, irqfla= gs, - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_VIRT_IRQ, irqflags, - GIC_FDT_IRQ_TYPE_PPI, ARCH_TIMER_NS_EL2_IRQ, irqfla= gs); -} - -static void fdt_add_cpu_nodes(const VirtMachineState *vms) -{ - int cpu; - int addr_cells =3D 1; - const MachineState *ms =3D MACHINE(vms); - const ArmMachineState *ams =3D ARM_MACHINE(vms); - - /* - * From Documentation/devicetree/bindings/arm/cpus.txt - * On ARM v8 64-bit systems value should be set to 2, - * that corresponds to the MPIDR_EL1 register size. - * If MPIDR_EL1[63:32] value is equal to 0 on all CPUs - * in the system, #address-cells can be set to 1, since - * MPIDR_EL1[63:32] bits are not used for CPUs - * identification. - * - * Here we actually don't know whether our system is 32- or 64-bit on= e. - * The simplest way to go is to examine affinity IDs of all our CPUs.= If - * at least one of them has Aff3 populated, we set #address-cells to = 2. - */ - for (cpu =3D 0; cpu < ams->smp_cpus; cpu++) { - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); - - if (armcpu->mp_affinity & ARM_AFF3_MASK) { - addr_cells =3D 2; - break; - } - } - - qemu_fdt_add_subnode(ams->fdt, "/cpus"); - qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#address-cells", addr_cells); - qemu_fdt_setprop_cell(ams->fdt, "/cpus", "#size-cells", 0x0); - - for (cpu =3D ams->smp_cpus - 1; cpu >=3D 0; cpu--) { - char *nodename =3D g_strdup_printf("/cpus/cpu@%d", cpu); - ARMCPU *armcpu =3D ARM_CPU(qemu_get_cpu(cpu)); - CPUState *cs =3D CPU(armcpu); - - qemu_fdt_add_subnode(ams->fdt, nodename); - qemu_fdt_setprop_string(ams->fdt, nodename, "device_type", "cpu"); - qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", - armcpu->dtb_compatible); - - if (vms->psci_conduit !=3D QEMU_PSCI_CONDUIT_DISABLED - && ams->smp_cpus > 1) { - qemu_fdt_setprop_string(ams->fdt, nodename, - "enable-method", "psci"); - } - - if (addr_cells =3D=3D 2) { - qemu_fdt_setprop_u64(ams->fdt, nodename, "reg", - armcpu->mp_affinity); - } else { - qemu_fdt_setprop_cell(ams->fdt, nodename, "reg", - armcpu->mp_affinity); - } - - if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { - qemu_fdt_setprop_cell(ams->fdt, nodename, "numa-node-id", - ms->possible_cpus->cpus[cs->cpu_index].props.node_id); - } - - g_free(nodename); - } -} - static void fdt_add_its_gic_node(VirtMachineState *vms) { char *nodename; @@ -461,56 +281,6 @@ static void fdt_gic_set_virt_extension(VirtMachineStat= e *vms) } } =20 -static void fdt_add_gic_node(VirtMachineState *vms) -{ - char *nodename; - ArmMachineState *ams =3D ARM_MACHINE(vms); - - ams->gic_phandle =3D qemu_fdt_alloc_phandle(ams->fdt); - qemu_fdt_setprop_cell(ams->fdt, "/", "interrupt-parent", ams->gic_phan= dle); - - nodename =3D g_strdup_printf("/intc@%" PRIx64, - ams->memmap[VIRT_GIC_DIST].base); - qemu_fdt_add_subnode(ams->fdt, nodename); - qemu_fdt_setprop_cell(ams->fdt, nodename, "#interrupt-cells", 3); - qemu_fdt_setprop(ams->fdt, nodename, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(ams->fdt, nodename, "#address-cells", 0x2); - qemu_fdt_setprop_cell(ams->fdt, nodename, "#size-cells", 0x2); - qemu_fdt_setprop(ams->fdt, nodename, "ranges", NULL, 0); - if (ams->gic_version =3D=3D 3) { - int nb_redist_regions =3D virt_gicv3_redist_region_count(ams); - - qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", - "arm,gic-v3"); - - qemu_fdt_setprop_cell(ams->fdt, nodename, - "#redistributor-regions", nb_redist_regions); - - if (nb_redist_regions =3D=3D 1) { - qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, ams->memmap[VIRT_GIC_DIST].bas= e, - 2, ams->memmap[VIRT_GIC_DIST].siz= e, - 2, ams->memmap[VIRT_GIC_REDIST].b= ase, - 2, ams->memmap[VIRT_GIC_REDIST].s= ize); - } else { - qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", - 2, ams->memmap[VIRT_GIC_DIST].base, - 2, ams->memmap[VIRT_GIC_DIST].size, - 2, ams->memmap[VIRT_GIC_REDIST].base, - 2, ams->memmap[VIRT_GIC_REDIST].size, - 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].bas= e, - 2, ams->memmap[VIRT_HIGH_GIC_REDIST2].siz= e); - } - } else { - /* 'cortex-a15-gic' means 'GIC v2' */ - qemu_fdt_setprop_string(ams->fdt, nodename, "compatible", - "arm,cortex-a15-gic"); - } - - qemu_fdt_setprop_cell(ams->fdt, nodename, "phandle", ams->gic_phandle); - g_free(nodename); -} - static void fdt_add_pmu_nodes(const VirtMachineState *vms) { CPUState *cpu; @@ -681,7 +451,7 @@ static void create_gic(VirtMachineState *vms) =20 init_gic_sysbus(ams); set_gic_virt_sysbus(vms); - fdt_add_gic_node(vms); + fdt_add_gic_node(ams); fdt_gic_set_virt_extension(vms); =20 gic_set_msi_interrupt(vms); @@ -1470,7 +1240,7 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 - create_fdt(vms); + create_fdt(ams); =20 possible_cpus =3D mc->possible_cpu_arch_ids(machine); for (n =3D 0; n < possible_cpus->len; n++) { @@ -1536,8 +1306,8 @@ static void machvirt_init(MachineState *machine) object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } - fdt_add_timer_nodes(vms); - fdt_add_cpu_nodes(vms); + fdt_add_timer_nodes(ams); + fdt_add_cpu_nodes(ams); =20 if (!kvm_enabled()) { ARMCPU *cpu =3D ARM_CPU(first_cpu); diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 8fec23985e..743a90ba36 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -111,6 +111,14 @@ typedef struct { #define ARM_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(ArmMachineClass, klass, TYPE_ARM_MACHINE) =20 +void create_fdt(ArmMachineState *ams); + +void fdt_add_timer_nodes(const ArmMachineState *ams); + +void fdt_add_cpu_nodes(const ArmMachineState *ams); + +void fdt_add_gic_node(ArmMachineState *ams); + void qdev_create_gic(ArmMachineState *ams); =20 void init_gic_sysbus(ArmMachineState *ams); --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925641160301.1367353455206; Sun, 16 Feb 2020 23:47:21 -0800 (PST) Received: from localhost ([::1]:41512 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b7f-0004Se-O2 for importer@patchew.org; Mon, 17 Feb 2020 02:47:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:39443) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j3b30-0004Md-1q for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:31 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j3b2y-0000bn-MR for qemu-devel@nongnu.org; Mon, 17 Feb 2020 02:42:29 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:3231 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j3b2u-0000Ro-8H; Mon, 17 Feb 2020 02:42:24 -0500 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id 0F484F9413AD7C18766C; Mon, 17 Feb 2020 15:42:20 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:12 +0800 From: Xu Yandong To: Subject: [PATCH RFC 14/16] hw/arm: move shared bootinfo member to ArmMachine Date: Mon, 17 Feb 2020 02:51:26 -0500 Message-ID: <1581925888-103620-15-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move bootinfo member from VirtMachineState to ArmMachineState. Signed-off-by: Xu Yandong --- hw/arm/arm.c | 9 +++++++++ hw/arm/virt.c | 28 +++++++++------------------- include/hw/arm/arm.h | 3 +++ include/hw/arm/virt.h | 1 - 4 files changed, 21 insertions(+), 20 deletions(-) diff --git a/hw/arm/arm.c b/hw/arm/arm.c index 4bffee0f37..7d880dd8e7 100644 --- a/hw/arm/arm.c +++ b/hw/arm/arm.c @@ -508,6 +508,15 @@ void create_virtio_devices(const ArmMachineState *ams) } } =20 +void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) +{ + const ArmMachineState *board =3D container_of(binfo, ArmMachineState, + bootinfo); + + *fdt_size =3D board->fdt_size; + return board->fdt; +} + static char *virt_get_gic_version(Object *obj, Error **errp) { ArmMachineState *ams =3D ARM_MACHINE(obj); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 11e753906b..2f498ea687 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -971,16 +971,6 @@ static void create_secure_ram(VirtMachineState *vms, g_free(nodename); } =20 -static void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size) -{ - const VirtMachineState *vms =3D container_of(binfo, VirtMachineState, - bootinfo); - - ArmMachineState *board =3D ARM_MACHINE(vms); - *fdt_size =3D board->fdt_size; - return board->fdt; -} - static void virt_build_smbios(VirtMachineState *vms) { MachineClass *mc =3D MACHINE_GET_CLASS(vms); @@ -1016,7 +1006,7 @@ void virt_machine_done(Notifier *notifier, void *data) MachineState *ms =3D MACHINE(vms); ArmMachineState *ams =3D ARM_MACHINE(vms); ARMCPU *cpu =3D ARM_CPU(first_cpu); - struct arm_boot_info *info =3D &vms->bootinfo; + struct arm_boot_info *info =3D &ams->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); =20 /* @@ -1373,14 +1363,14 @@ static void machvirt_init(MachineState *machine) =20 create_platform_bus(vms); =20 - vms->bootinfo.ram_size =3D machine->ram_size; - vms->bootinfo.nb_cpus =3D smp_cpus; - vms->bootinfo.board_id =3D -1; - vms->bootinfo.loader_start =3D ams->memmap[VIRT_MEM].base; - vms->bootinfo.get_dtb =3D machvirt_dtb; - vms->bootinfo.skip_dtb_autoload =3D true; - vms->bootinfo.firmware_loaded =3D firmware_loaded; - arm_load_kernel(ARM_CPU(first_cpu), machine, &vms->bootinfo); + ams->bootinfo.ram_size =3D machine->ram_size; + ams->bootinfo.nb_cpus =3D smp_cpus; + ams->bootinfo.board_id =3D -1; + ams->bootinfo.loader_start =3D ams->memmap[VIRT_MEM].base; + ams->bootinfo.get_dtb =3D machvirt_dtb; + ams->bootinfo.skip_dtb_autoload =3D true; + ams->bootinfo.firmware_loaded =3D firmware_loaded; + arm_load_kernel(ARM_CPU(first_cpu), machine, &ams->bootinfo); =20 vms->machine_done.notify =3D virt_machine_done; qemu_add_machine_init_done_notifier(&vms->machine_done); diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 743a90ba36..372f4dea28 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -92,6 +92,7 @@ typedef struct { typedef struct { MachineState parent; int32_t gic_version; + struct arm_boot_info bootinfo; MemMapEntry *memmap; const int *irqmap; int smp_cpus; @@ -130,6 +131,8 @@ void create_rtc(const ArmMachineState *ams); =20 void create_virtio_devices(const ArmMachineState *ams); =20 +void *machvirt_dtb(const struct arm_boot_info *binfo, int *fdt_size); + /* Return the number of used redistributor regions */ static inline int virt_gicv3_redist_region_count(ArmMachineState *ams) { diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 086a27682f..8276e2c02c 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -68,7 +68,6 @@ typedef struct { bool its; bool virt; VirtIOMMUType iommu; - struct arm_boot_info bootinfo; uint32_t msi_phandle; uint32_t iommu_phandle; hwaddr highest_gpa; --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581925644904567.3468703118875; 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Mon, 17 Feb 2020 15:42:12 +0800 From: Xu Yandong To: Subject: [PATCH RFC 15/16] hw/arm: move shared cpu related functions to arm.c and export them Date: Mon, 17 Feb 2020 02:51:27 -0500 Message-ID: <1581925888-103620-16-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move cpu related functions that will be shared between VIRT and non-VIRT machine types to arm.c. Signed-off-by: Xu Yandong --- hw/arm/arm.c | 89 ++++++++++++++++++++++++++++++++++++++++++ hw/arm/virt.c | 91 +------------------------------------------ include/hw/arm/arm.h | 3 ++ include/hw/arm/virt.h | 1 - 4 files changed, 94 insertions(+), 90 deletions(-) diff --git a/hw/arm/arm.c b/hw/arm/arm.c index 7d880dd8e7..8bb5d92d2e 100644 --- a/hw/arm/arm.c +++ b/hw/arm/arm.c @@ -39,6 +39,28 @@ #include "hw/intc/arm_gic.h" #include "kvm_arm.h" =20 +static const char *valid_cpus[] =3D { + ARM_CPU_TYPE_NAME("cortex-a7"), + ARM_CPU_TYPE_NAME("cortex-a15"), + ARM_CPU_TYPE_NAME("cortex-a53"), + ARM_CPU_TYPE_NAME("cortex-a57"), + ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("host"), + ARM_CPU_TYPE_NAME("max"), +}; + +bool cpu_type_valid(const char *cpu) +{ + int i; + + for (i =3D 0; i < ARRAY_SIZE(valid_cpus); i++) { + if (strcmp(cpu, valid_cpus[i]) =3D=3D 0) { + return true; + } + } + return false; +} + void create_fdt(ArmMachineState *ams) { MachineState *ms =3D MACHINE(ams); @@ -543,6 +565,70 @@ static void virt_set_gic_version(Object *obj, const ch= ar *value, Error **errp) } } =20 +static uint64_t virt_cpu_mp_affinity(ArmMachineState *ams, int idx) +{ + uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; + ArmMachineClass *amc =3D ARM_MACHINE_GET_CLASS(ams); + + if (!amc->disallow_affinity_adjustment) { + /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the + * GIC's target-list limitations. 32-bit KVM hosts currently + * always create clusters of 4 CPUs, but that is expected to + * change when they gain support for gicv3. When KVM is enabled + * it will override the changes we make here, therefore our + * purposes are to make TCG consistent (with 64-bit KVM hosts) + * and to improve SGI efficiency. + */ + if (ams->gic_version =3D=3D 3) { + clustersz =3D GICV3_TARGETLIST_BITS; + } else { + clustersz =3D GIC_TARGETLIST_BITS; + } + } + return arm_cpu_mp_affinity(idx, clustersz); +} + + +static CpuInstanceProperties +virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) +{ + MachineClass *mc =3D MACHINE_GET_CLASS(ms); + const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(ms); + + assert(cpu_index < possible_cpus->len); + return possible_cpus->cpus[cpu_index].props; +} + + +static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int id= x) +{ + return idx % ms->numa_state->num_nodes; +} + +static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) +{ + int n; + unsigned int max_cpus =3D ms->smp.max_cpus; + ArmMachineState *ams =3D ARM_MACHINE(ms); + + if (ms->possible_cpus) { + assert(ms->possible_cpus->len =3D=3D max_cpus); + return ms->possible_cpus; + } + + ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + + sizeof(CPUArchId) * max_cpus); + ms->possible_cpus->len =3D max_cpus; + for (n =3D 0; n < ms->possible_cpus->len; n++) { + ms->possible_cpus->cpus[n].type =3D ms->cpu_type; + ms->possible_cpus->cpus[n].arch_id =3D + virt_cpu_mp_affinity(ams, n); + ms->possible_cpus->cpus[n].props.has_thread_id =3D true; + ms->possible_cpus->cpus[n].props.thread_id =3D n; + } + return ms->possible_cpus; +} + static void arm_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -555,6 +641,9 @@ static void arm_machine_class_init(ObjectClass *oc, voi= d *data) mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("cortex-a15"); mc->numa_mem_supported =3D true; mc->auto_enable_numa_with_memhp =3D true; + mc->cpu_index_to_instance_props =3D virt_cpu_index_to_props; + mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; + mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; } =20 static void arm_instance_init(Object *obj) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 2f498ea687..14d20d5c46 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -182,28 +182,6 @@ static const int a15irqmap[] =3D { [VIRT_PLATFORM_BUS] =3D 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */ }; =20 -static const char *valid_cpus[] =3D { - ARM_CPU_TYPE_NAME("cortex-a7"), - ARM_CPU_TYPE_NAME("cortex-a15"), - ARM_CPU_TYPE_NAME("cortex-a53"), - ARM_CPU_TYPE_NAME("cortex-a57"), - ARM_CPU_TYPE_NAME("cortex-a72"), - ARM_CPU_TYPE_NAME("host"), - ARM_CPU_TYPE_NAME("max"), -}; - -static bool cpu_type_valid(const char *cpu) -{ - int i; - - for (i =3D 0; i < ARRAY_SIZE(valid_cpus); i++) { - if (strcmp(cpu, valid_cpus[i]) =3D=3D 0) { - return true; - } - } - return false; -} - static void fdt_add_its_gic_node(VirtMachineState *vms) { char *nodename; @@ -1030,30 +1008,6 @@ void virt_machine_done(Notifier *notifier, void *dat= a) virt_build_smbios(vms); } =20 -static uint64_t virt_cpu_mp_affinity(VirtMachineState *vms, int idx) -{ - uint8_t clustersz =3D ARM_DEFAULT_CPUS_PER_CLUSTER; - ArmMachineState *ams =3D ARM_MACHINE(vms); - VirtMachineClass *vmc =3D VIRT_MACHINE_GET_CLASS(vms); - - if (!vmc->disallow_affinity_adjustment) { - /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the - * GIC's target-list limitations. 32-bit KVM hosts currently - * always create clusters of 4 CPUs, but that is expected to - * change when they gain support for gicv3. When KVM is enabled - * it will override the changes we make here, therefore our - * purposes are to make TCG consistent (with 64-bit KVM hosts) - * and to improve SGI efficiency. - */ - if (ams->gic_version =3D=3D 3) { - clustersz =3D GICV3_TARGETLIST_BITS; - } else { - clustersz =3D GIC_TARGETLIST_BITS; - } - } - return arm_cpu_mp_affinity(idx, clustersz); -} - static void virt_set_memmap(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); @@ -1460,45 +1414,6 @@ static void virt_set_iommu(Object *obj, const char *= value, Error **errp) } } =20 -static CpuInstanceProperties -virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) -{ - MachineClass *mc =3D MACHINE_GET_CLASS(ms); - const CPUArchIdList *possible_cpus =3D mc->possible_cpu_arch_ids(ms); - - assert(cpu_index < possible_cpus->len); - return possible_cpus->cpus[cpu_index].props; -} - -static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int id= x) -{ - return idx % ms->numa_state->num_nodes; -} - -static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) -{ - int n; - unsigned int max_cpus =3D ms->smp.max_cpus; - VirtMachineState *vms =3D VIRT_MACHINE(ms); - - if (ms->possible_cpus) { - assert(ms->possible_cpus->len =3D=3D max_cpus); - return ms->possible_cpus; - } - - ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + - sizeof(CPUArchId) * max_cpus); - ms->possible_cpus->len =3D max_cpus; - for (n =3D 0; n < ms->possible_cpus->len; n++) { - ms->possible_cpus->cpus[n].type =3D ms->cpu_type; - ms->possible_cpus->cpus[n].arch_id =3D - virt_cpu_mp_affinity(vms, n); - ms->possible_cpus->cpus[n].props.has_thread_id =3D true; - ms->possible_cpus->cpus[n].props.thread_id =3D n; - } - return ms->possible_cpus; -} - static void virt_memory_pre_plug(HotplugHandler *hotplug_dev, DeviceState = *dev, Error **errp) { @@ -1624,9 +1539,6 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_AMD_XGBE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); machine_class_allow_dynamic_sysbus_dev(mc, TYPE_VFIO_PLATFORM); - mc->possible_cpu_arch_ids =3D virt_possible_cpu_arch_ids; - mc->cpu_index_to_instance_props =3D virt_cpu_index_to_props; - mc->get_default_cpu_node_id =3D virt_get_default_cpu_node_id; mc->kvm_type =3D virt_kvm_type; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler =3D virt_machine_get_hotplug_handler; @@ -1833,10 +1745,11 @@ DEFINE_VIRT_MACHINE(2, 7) static void virt_machine_2_6_options(MachineClass *mc) { VirtMachineClass *vmc =3D VIRT_MACHINE_CLASS(OBJECT_CLASS(mc)); + ArmMachineClass *amc =3D ARM_MACHINE_CLASS(OBJECT_CLASS(mc)); =20 virt_machine_2_7_options(mc); compat_props_add(mc->compat_props, hw_compat_2_6, hw_compat_2_6_len); - vmc->disallow_affinity_adjustment =3D true; + amc->disallow_affinity_adjustment =3D true; /* Disable PMU for 2.6 as PMU support was first introduced in 2.7 */ vmc->no_pmu =3D true; } diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 372f4dea28..37a419b784 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -86,6 +86,7 @@ typedef struct MemMapEntry { =20 typedef struct { MachineClass parent; + bool disallow_affinity_adjustment; bool claim_edge_triggered_timers; } ArmMachineClass; =20 @@ -112,6 +113,8 @@ typedef struct { #define ARM_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(ArmMachineClass, klass, TYPE_ARM_MACHINE) =20 +bool cpu_type_valid(const char *cpu); + void create_fdt(ArmMachineState *ams); =20 void fdt_add_timer_nodes(const ArmMachineState *ams); diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 8276e2c02c..aa66cd78d5 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -47,7 +47,6 @@ typedef enum VirtIOMMUType { =20 typedef struct { ArmMachineClass parent; - bool disallow_affinity_adjustment; bool no_its; bool no_pmu; bool smbios_old_sys_ver; --=20 2.18.1 From nobody Mon Feb 9 06:56:28 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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Mon, 17 Feb 2020 02:42:24 -0500 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id D4A2E50EFFD6B15E4E00; Mon, 17 Feb 2020 15:42:19 +0800 (CST) Received: from localhost (10.175.124.177) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.439.0; Mon, 17 Feb 2020 15:42:13 +0800 From: Xu Yandong To: Subject: [PATCH RFC 16/16] hw/arm: Introduce the microvm machine type Date: Mon, 17 Feb 2020 02:51:28 -0500 Message-ID: <1581925888-103620-17-git-send-email-xuyandong2@huawei.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> References: <1581925888-103620-1-git-send-email-xuyandong2@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.175.124.177] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: zhang.zhanghailiang@huawei.com, slp@redhat.com, Xu Yandong , qemu-devel@nongnu.org, qemu-arm@nongnu.org, wu.wubin@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It's a minimalist machine type without PCI nor ACPI support, designed for short-lived guests. microvm also establishes a baseline for benchmarking and optimizing both QEMU and guest operating systems, since it is optimized for both boot time and footprint. Signed-off-by: Xu Yandong --- default-configs/aarch64-softmmu.mak | 2 + hw/arm/Kconfig | 7 + hw/arm/Makefile.objs | 1 + hw/arm/arm.c | 8 + hw/arm/microvm.c | 303 ++++++++++++++++++++++++++++ hw/arm/virt.c | 17 +- include/hw/arm/arm.h | 2 + include/hw/arm/microvm.h | 40 ++++ include/hw/arm/virt.h | 1 - 9 files changed, 372 insertions(+), 9 deletions(-) create mode 100644 hw/arm/microvm.c create mode 100644 include/hw/arm/microvm.h diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-= softmmu.mak index 958b1e08e4..e9e994801c 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -6,3 +6,5 @@ include arm-softmmu.mak CONFIG_XLNX_ZYNQMP_ARM=3Dy CONFIG_XLNX_VERSAL=3Dy CONFIG_SBSA_REF=3Dy + +CONFIG_ARM_MICROVM=3Dy diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3d86691ae0..153ffbabac 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -25,6 +25,13 @@ config ARM_VIRT select ACPI_MEMORY_HOTPLUG select ACPI_HW_REDUCED =20 +config ARM_MICROVM + bool + select A15MPCORE + select PL011 # UART + select PL031 # RTC + select VIRTIO_MMIO + config CHEETAH bool select OMAP diff --git a/hw/arm/Makefile.objs b/hw/arm/Makefile.objs index 51fcee2ac8..2a2f643774 100644 --- a/hw/arm/Makefile.objs +++ b/hw/arm/Makefile.objs @@ -1,6 +1,7 @@ obj-y +=3D boot.o obj-$(CONFIG_PLATFORM_BUS) +=3D sysbus-fdt.o obj-$(CONFIG_ARM_VIRT) +=3D arm.o virt.o +obj-$(CONFIG_ARM_MICROVM) +=3D arm.o microvm.o obj-$(CONFIG_ACPI) +=3D virt-acpi-build.o obj-$(CONFIG_DIGIC) +=3D digic_boards.o obj-$(CONFIG_EXYNOS4) +=3D exynos4_boards.o diff --git a/hw/arm/arm.c b/hw/arm/arm.c index 8bb5d92d2e..0c5bf1a2f8 100644 --- a/hw/arm/arm.c +++ b/hw/arm/arm.c @@ -306,6 +306,14 @@ void qdev_create_gic(ArmMachineState *ams) */ qdev_prop_set_uint32(ams->gic, "num-irq", NUM_IRQS + 32); =20 + if (!kvm_irqchip_in_kernel()) { + qdev_prop_set_bit(ams->gic, "has-security-extensions", false); + if (type !=3D 3) { + qdev_prop_set_bit(ams->gic, "has-virtualization-extensions", + false); + } + } + if (type =3D=3D 3) { uint32_t redist0_capacity =3D ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; diff --git a/hw/arm/microvm.c b/hw/arm/microvm.c new file mode 100644 index 0000000000..04f98d63cb --- /dev/null +++ b/hw/arm/microvm.c @@ -0,0 +1,303 @@ +/* + * ARM mach-virt emulation + * + * Copyright (c) 2013 Linaro Limited + * Copyright (c) 2020 Huawei. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "hw/arm/arm.h" +#include "hw/arm/microvm.h" +#include "sysemu/device_tree.h" +#include "sysemu/numa.h" +#include "sysemu/sysemu.h" +#include "hw/loader.h" +#include "hw/qdev-properties.h" +#include "hw/arm/fdt.h" +#include "kvm_arm.h" + +/* Number of external interrupt lines to configure the GIC with */ +#define NUM_IRQS 256 + +#define PLATFORM_BUS_NUM_IRQS 64 + +/* Legacy RAM limit in GB (< version 4.0) */ +#define LEGACY_RAMLIMIT_GB 255 +#define LEGACY_RAMLIMIT_BYTES (LEGACY_RAMLIMIT_GB * GiB) + +/* Addresses and sizes of our components. + * 0..128MB is space for a flash device so we can run bootrom code such as= UEFI. + * 128MB..256MB is used for miscellaneous device I/O. + * 256MB..1GB is reserved for possible future PCI support (ie where the + * PCI memory window will go if we add a PCI host controller). + * 1GB and up is RAM (which may happily spill over into the + * high memory region beyond 4GB). + * This represents a compromise between how much RAM can be given to + * a 32 bit VM and leaving space for expansion and in particular for PCI. + * Note that devices should generally be placed at multiples of 0x10000, + * to accommodate guests using 64K pages. + */ +static MemMapEntry base_memmap[] =3D { + /* Space up to 0x8000000 is reserved for a boot ROM */ + [VIRT_CPUPERIPHS] =3D { 0x08000000, 0x00020000 }, + /* GIC distributor and CPU interfaces sit inside the CPU peripheral sp= ace */ + [VIRT_GIC_DIST] =3D { 0x08000000, 0x00010000 }, + [VIRT_GIC_CPU] =3D { 0x08010000, 0x00010000 }, + /* This redistributor space allows up to 2*64kB*123 CPUs */ + [VIRT_GIC_REDIST] =3D { 0x080A0000, 0x00F60000 }, + [VIRT_UART] =3D { 0x09000000, 0x00001000 }, + [VIRT_RTC] =3D { 0x09010000, 0x00001000 }, + [VIRT_MMIO] =3D { 0x0a000000, 0x00000200 }, + /* Actual RAM size depends on initial RAM and device memory settings */ + [VIRT_MEM] =3D { 0x40000000, LEGACY_RAMLIMIT_BYTES }, + /* Additional 64 MB redist region (can contain up to 512 redistributor= s) */ + [VIRT_HIGH_GIC_REDIST2] =3D { 0x4000000000ULL, 0x4000000 }, +}; + +static const int a15irqmap[] =3D { + [VIRT_UART] =3D 1, + [VIRT_RTC] =3D 2, + [VIRT_MMIO] =3D 16, /* ...to 16 + NUM_VIRTIO_TRANSPORTS - 1 */ +}; + +static void fdt_gic_intc_node(MicrovmMachineState *mms) +{ + char *nodename; + ArmMachineState *ams =3D ARM_MACHINE(mms); + + if (ams->gic_version =3D=3D 3) { + return; + } + + nodename =3D g_strdup_printf("/intc@%" PRIx64, + ams->memmap[VIRT_GIC_DIST].base); + + qemu_fdt_setprop_sized_cells(ams->fdt, nodename, "reg", + 2, ams->memmap[VIRT_GIC_DIST].base, + 2, ams->memmap[VIRT_GIC_DIST].size, + 2, ams->memmap[VIRT_GIC_CPU].base, + 2, ams->memmap[VIRT_GIC_CPU].size); + + g_free(nodename); +} + + +static void create_gic(MicrovmMachineState *mms) +{ + ArmMachineState *ams =3D ARM_MACHINE(mms); + + qdev_create_gic(ams); + qdev_init_nofail(ams->gic); + + init_gic_sysbus(ams); + fdt_add_gic_node(ams); + fdt_gic_intc_node(mms); +} + +static +void microvm_machine_done(Notifier *notifier, void *data) +{ + ArmMachineState *ams =3D container_of(notifier, ArmMachineState, + machine_done); + MachineState *ms =3D MACHINE(ams); + ARMCPU *cpu =3D ARM_CPU(first_cpu); + struct arm_boot_info *info =3D &ams->bootinfo; + AddressSpace *as =3D arm_boot_address_space(cpu, info); + + if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as, ms) < 0) { + exit(1); + } +} + +static void microvm_init(MachineState *machine) +{ + ArmMachineState *ams =3D ARM_MACHINE(machine); + MicrovmMachineState *mms =3D MICROVM_MACHINE(machine); + MachineClass *mc =3D MACHINE_GET_CLASS(machine); + const CPUArchIdList *possible_cpus; + MemoryRegion *sysmem =3D get_system_memory(); + int n, arm_max_cpus; + MemoryRegion *ram =3D g_new(MemoryRegion, 1); + bool aarch64 =3D true; + unsigned int smp_cpus =3D machine->smp.cpus; + unsigned int max_cpus =3D machine->smp.max_cpus; + + /* microvm, only support KVM */ + if (!kvm_enabled()) { + error_report("microvm requires KVM"); + exit(1); + } + + /* We can probe only here because during property set + * KVM is not available yet + */ + if (ams->gic_version <=3D 0) { + ams->gic_version =3D kvm_arm_vgic_probe(); + if (!ams->gic_version) { + error_report( + "Unable to determine GIC version supported by host"); + exit(1); + } + } + + if (!cpu_type_valid(machine->cpu_type)) { + error_report("mach-virt: CPU type %s not supported", machine->cpu_= type); + exit(1); + } + + ams->psci_conduit =3D QEMU_PSCI_CONDUIT_HVC; + + /* The maximum number of CPUs depends on the GIC version, or on how + * many redistributors we can fit into the memory map. + */ + if (ams->gic_version =3D=3D 3) { + arm_max_cpus =3D + ams->memmap[VIRT_GIC_REDIST].size / GICV3_REDIST_SIZE; + arm_max_cpus +=3D + ams->memmap[VIRT_HIGH_GIC_REDIST2].size / GICV3_REDIST_SIZE; + } else { + arm_max_cpus =3D GIC_NCPU; + } + + if (max_cpus > arm_max_cpus) { + error_report("Number of SMP CPUs requested (%d) exceeds max CPUs " + "supported by machine 'mach-microvm' (%d)", + max_cpus, arm_max_cpus); + exit(1); + } + + ams->smp_cpus =3D smp_cpus; + + create_fdt(ams); + + possible_cpus =3D mc->possible_cpu_arch_ids(machine); + for (n =3D 0; n < possible_cpus->len; n++) { + Object *cpuobj; + CPUState *cs; + + if (n >=3D smp_cpus) { + break; + } + + cpuobj =3D object_new(possible_cpus->cpus[n].type); + object_property_set_int(cpuobj, possible_cpus->cpus[n].arch_id, + "mp-affinity", NULL); + + cs =3D CPU(cpuobj); + cs->cpu_index =3D n; + + numa_cpu_pre_plug(&possible_cpus->cpus[cs->cpu_index], DEVICE(cpuo= bj), + &error_fatal); + + aarch64 &=3D object_property_get_bool(cpuobj, "aarch64", NULL); + + object_property_set_int(cpuobj, ams->psci_conduit, + "psci-conduit", NULL); + + /* Secondary CPUs start in PSCI powered-down state */ + if (n > 0) { + object_property_set_bool(cpuobj, true, + "start-powered-off", NULL); + } + + if (object_property_find(cpuobj, "pmu", NULL)) { + object_property_set_bool(cpuobj, false, "pmu", NULL); + } + + if (object_property_find(cpuobj, "reset-cbar", NULL)) { + object_property_set_int(cpuobj, ams->memmap[VIRT_CPUPERIPHS].b= ase, + "reset-cbar", &error_abort); + } + + object_property_set_link(cpuobj, OBJECT(sysmem), "memory", + &error_abort); + + object_property_set_bool(cpuobj, true, "realized", &error_fatal); + object_unref(cpuobj); + } + fdt_add_timer_nodes(ams); + fdt_add_cpu_nodes(ams); + + memory_region_allocate_system_memory(ram, NULL, "mach-virt.ram", + machine->ram_size); + memory_region_add_subregion(sysmem, ams->memmap[VIRT_MEM].base, ram); + + create_gic(mms); + + create_uart(ams, VIRT_UART, sysmem, serial_hd(0)); + create_rtc(ams); + + /* Create mmio transports, so the user can create virtio backends + * (which will be automatically plugged in to the transports). If + * no backend is created the transport will just sit harmlessly idle. + */ + create_virtio_devices(ams); + + ams->bootinfo.ram_size =3D machine->ram_size; + ams->bootinfo.nb_cpus =3D smp_cpus; + ams->bootinfo.board_id =3D -1; + ams->bootinfo.loader_start =3D ams->memmap[VIRT_MEM].base; + ams->bootinfo.get_dtb =3D machvirt_dtb; + ams->bootinfo.skip_dtb_autoload =3D true; + ams->bootinfo.firmware_loaded =3D false; + arm_load_kernel(ARM_CPU(first_cpu), machine, &ams->bootinfo); + + ams->machine_done.notify =3D microvm_machine_done; + qemu_add_machine_init_done_notifier(&ams->machine_done); +} + +static void microvm_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + + mc->desc =3D "QEMU ARM MicroVM Virtual Machine"; + mc->init =3D microvm_init; + /* Start with max_cpus set to 512, which is the maximum supported by K= VM. + * The value may be reduced later when we have more information about = the + * configuration of the particular instance. + */ + mc->max_cpus =3D 512; + mc->default_cpu_type =3D ARM_CPU_TYPE_NAME("host"); + mc->default_machine_opts =3D "accel=3Dkvm"; +} + +static void microvm_instance_init(Object *obj) +{ + ArmMachineState *ams =3D ARM_MACHINE(obj); + + ams->memmap =3D base_memmap; + ams->irqmap =3D a15irqmap; +} + +static const TypeInfo microvm_machine_info =3D { + .name =3D TYPE_MICROVM_MACHINE, + .parent =3D TYPE_ARM_MACHINE, + .instance_size =3D sizeof(MicrovmMachineState), + .instance_init =3D microvm_instance_init, + .class_size =3D sizeof(MicrovmMachineClass), + .class_init =3D microvm_class_init, + .interfaces =3D (InterfaceInfo[]) { + { } + }, +}; + +static void microvm_machine_init(void) +{ + type_register_static(µvm_machine_info); +} + +type_init(microvm_machine_init); diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 14d20d5c46..c4ffeff4aa 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -979,10 +979,10 @@ static void virt_build_smbios(VirtMachineState *vms) static void virt_machine_done(Notifier *notifier, void *data) { - VirtMachineState *vms =3D container_of(notifier, VirtMachineState, + ArmMachineState *ams =3D container_of(notifier, ArmMachineState, machine_done); - MachineState *ms =3D MACHINE(vms); - ArmMachineState *ams =3D ARM_MACHINE(vms); + MachineState *ms =3D MACHINE(ams); + VirtMachineState *vms =3D VIRT_MACHINE(ams); ARMCPU *cpu =3D ARM_CPU(first_cpu); struct arm_boot_info *info =3D &ams->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); @@ -1056,7 +1056,7 @@ static void virt_set_memmap(VirtMachineState *vms) ams->memmap[i].size =3D size; base +=3D size; } - vms->highest_gpa =3D base - 1; + ams->highest_gpa =3D base - 1; if (device_memory_size > 0) { ms->device_memory =3D g_malloc0(sizeof(*ms->device_memory)); ms->device_memory->base =3D device_memory_base; @@ -1260,7 +1260,7 @@ static void machvirt_init(MachineState *machine) if (aarch64 && vms->highmem) { int requested_pa_size, pamax =3D arm_pamax(cpu); =20 - requested_pa_size =3D 64 - clz64(vms->highest_gpa); + requested_pa_size =3D 64 - clz64(ams->highest_gpa); if (pamax < requested_pa_size) { error_report("VCPU supports less PA bits (%d) than request= ed " "by the memory map (%d)", pamax, requested_pa_= size); @@ -1326,8 +1326,8 @@ static void machvirt_init(MachineState *machine) ams->bootinfo.firmware_loaded =3D firmware_loaded; arm_load_kernel(ARM_CPU(first_cpu), machine, &ams->bootinfo); =20 - vms->machine_done.notify =3D virt_machine_done; - qemu_add_machine_init_done_notifier(&vms->machine_done); + ams->machine_done.notify =3D virt_machine_done; + qemu_add_machine_init_done_notifier(&ams->machine_done); } =20 static bool virt_get_secure(Object *obj, Error **errp) @@ -1501,13 +1501,14 @@ static HotplugHandler *virt_machine_get_hotplug_han= dler(MachineState *machine, static int virt_kvm_type(MachineState *ms, const char *type_str) { VirtMachineState *vms =3D VIRT_MACHINE(ms); + ArmMachineState *ams =3D ARM_MACHINE(ms); int max_vm_pa_size =3D kvm_arm_get_max_vm_ipa_size(ms); int requested_pa_size; =20 /* we freeze the memory map to compute the highest gpa */ virt_set_memmap(vms); =20 - requested_pa_size =3D 64 - clz64(vms->highest_gpa); + requested_pa_size =3D 64 - clz64(ams->highest_gpa); =20 if (requested_pa_size > max_vm_pa_size) { error_report("-m and ,maxmem option values " diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index 37a419b784..f9ec676579 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h @@ -92,6 +92,7 @@ typedef struct { =20 typedef struct { MachineState parent; + Notifier machine_done; int32_t gic_version; struct arm_boot_info bootinfo; MemMapEntry *memmap; @@ -102,6 +103,7 @@ typedef struct { uint32_t clock_phandle; uint32_t gic_phandle; int psci_conduit; + hwaddr highest_gpa; DeviceState *gic; } ArmMachineState; =20 diff --git a/include/hw/arm/microvm.h b/include/hw/arm/microvm.h new file mode 100644 index 0000000000..be8e771b07 --- /dev/null +++ b/include/hw/arm/microvm.h @@ -0,0 +1,40 @@ +/* + * + * Copyright (c) 2015 Linaro Limited + * Copyright (c) 2020 Huawei. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef QEMU_ARM_MICROVM_H +#define QEMU_ARM_MICROVM_H + +#include "hw/arm/arm.h" + +typedef struct { + ArmMachineClass parent; +} MicrovmMachineClass; + +typedef struct { + ArmMachineState parent; +} MicrovmMachineState; + +#define TYPE_MICROVM_MACHINE MACHINE_TYPE_NAME("microvm") +#define MICROVM_MACHINE(obj) \ + OBJECT_CHECK(MicrovmMachineState, (obj), TYPE_MICROVM_MACHINE) +#define MICROVM_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(MicrovmMachineClass, obj, TYPE_MICROVM_MACHINE) +#define MICROVM_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(MicrovmMachineClass, klass, TYPE_MICROVM_MACHINE) + +#endif /* QEMU_ARM_MICROVM_H */ diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index aa66cd78d5..4e32c650b4 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -69,7 +69,6 @@ typedef struct { VirtIOMMUType iommu; uint32_t msi_phandle; uint32_t iommu_phandle; - hwaddr highest_gpa; DeviceState *acpi_dev; Notifier powerdown_notifier; } VirtMachineState; --=20 2.18.1