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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Hm8mXPTuet02JHj/1pvMnNJg8GRLzCMhsprgCZwB10RWjvC7yNnXtKYcNxHQhQnJxLjg2epnm7kR0uG8G7PNUTGHmZuozQfJkdRYNEMtmldt1F6Xn8zWKxJd+NRDvG36j2yiGGMaPa9ILG/oHMlRonL6c/1lxP04yz1t9JMGvopLx/yhYZ9d1GyMAwpruIWU48JzheZwqVSawQ3goTRXchGcwKbm56X5OoZuT8ISzm7KZ3FMFvspf7M5gDfHNyNoY/UTps/Pf2ByTCFmr9ITHL/iHOQddhBYgMyKmNYV2IMDI3xHJEdIQzmCVHt2V4ln0AEn8LepOxaS+GYdlJERtBVLtEk+OPRM0O4fRROYXLvHbspJePmi8UMDTzFDxuG2n3T3zZ17zmGnH/gdzbCW5luAuh1iCqI0sUZfpue8Bd36GRtovOMAcolu88v9hp0z X-MS-Exchange-AntiSpam-MessageData: uQU9KP3BEmzQfizIq0nh6EI05YgPQlEBlbUfRCkZ7KJAqXNEpqsGd/SDXQ1e0sIhna4Bym2UeYwq/tZewuUVJLuv9xfYdI2wMWpqOpQE2uI8l70eMRLmJeaJfEvBWlhbZq/VZkChhpuFlxyml5du7Q== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: e29b569d-2e03-4bc9-b796-08d7b0b0da8b X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:16:32.4996 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iK2ACGj2hwYQq1/1/ccvzaHzS+qv1ibSNqfJovBbtWZDpkXrqea/hrJLC3AicSsN X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1318 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.236.46 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) Rename few data structures related to X86 topology. X86CPUTopoIDs will have individual arch ids. Next patch introduces X86CPUTopoInfo which will have all topology information(like cores, threads etc..). Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 42 +++++++++++++++++++++-------------------= -- hw/i386/x86.c | 18 +++++++++--------- include/hw/i386/topology.h | 40 ++++++++++++++++++++-------------------- 3 files changed, 50 insertions(+), 50 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 58867f987d..3a580f6a60 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1733,7 +1733,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, int idx; CPUState *cs; CPUArchId *cpu_slot; - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; X86CPU *cpu =3D X86_CPU(dev); CPUX86State *env =3D &cpu->env; MachineState *ms =3D MACHINE(hotplug_dev); @@ -1799,12 +1799,12 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, return; } =20 - topo.pkg_id =3D cpu->socket_id; - topo.die_id =3D cpu->die_id; - topo.core_id =3D cpu->core_id; - topo.smt_id =3D cpu->thread_id; + topo_ids.pkg_id =3D cpu->socket_id; + topo_ids.die_id =3D cpu->die_id; + topo_ids.core_id =3D cpu->core_id; + topo_ids.smt_id =3D cpu->thread_id; cpu->apic_id =3D apicid_from_topo_ids(x86ms->smp_dies, smp_cores, - smp_threads, &topo); + smp_threads, &topo_ids); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); @@ -1812,11 +1812,11 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, MachineState *ms =3D MACHINE(pcms); =20 x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, - smp_cores, smp_threads, &topo); + smp_cores, smp_threads, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", - topo.pkg_id, topo.die_id, topo.core_id, topo.smt_id, + topo_ids.pkg_id, topo_ids.die_id, topo_ids.core_id, topo_ids.s= mt_id, cpu->apic_id, ms->possible_cpus->len - 1); return; } @@ -1834,34 +1834,34 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, - smp_cores, smp_threads, &topo); - if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo.pkg_id) { + smp_cores, smp_threads, &topo_ids); + if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" - " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo.pk= g_id); + " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_id= s.pkg_id); return; } - cpu->socket_id =3D topo.pkg_id; + cpu->socket_id =3D topo_ids.pkg_id; =20 - if (cpu->die_id !=3D -1 && cpu->die_id !=3D topo.die_id) { + if (cpu->die_id !=3D -1 && cpu->die_id !=3D topo_ids.die_id) { error_setg(errp, "property die-id: %u doesn't match set apic-id:" - " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo.die_id); + " 0x%x (die-id: %u)", cpu->die_id, cpu->apic_id, topo_ids.die_= id); return; } - cpu->die_id =3D topo.die_id; + cpu->die_id =3D topo_ids.die_id; =20 - if (cpu->core_id !=3D -1 && cpu->core_id !=3D topo.core_id) { + if (cpu->core_id !=3D -1 && cpu->core_id !=3D topo_ids.core_id) { error_setg(errp, "property core-id: %u doesn't match set apic-id:" - " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo.core_i= d); + " 0x%x (core-id: %u)", cpu->core_id, cpu->apic_id, topo_ids.co= re_id); return; } - cpu->core_id =3D topo.core_id; + cpu->core_id =3D topo_ids.core_id; =20 - if (cpu->thread_id !=3D -1 && cpu->thread_id !=3D topo.smt_id) { + if (cpu->thread_id !=3D -1 && cpu->thread_id !=3D topo_ids.smt_id) { error_setg(errp, "property thread-id: %u doesn't match set apic-id= :" - " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo.sm= t_id); + " 0x%x (thread-id: %u)", cpu->thread_id, cpu->apic_id, topo_id= s.smt_id); return; } - cpu->thread_id =3D topo.smt_id; + cpu->thread_id =3D topo_ids.smt_id; =20 if (hyperv_feat_enabled(cpu, HYPERV_FEAT_VPINDEX) && !kvm_hv_vpindex_settable()) { diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 394edc2f72..4a112c8e30 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -138,14 +138,14 @@ x86_cpu_index_to_props(MachineState *ms, unsigned cpu= _index) =20 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx) { - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; X86MachineState *x86ms =3D X86_MACHINE(ms); =20 assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, x86ms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo); - return topo.pkg_id % ms->numa_state->num_nodes; + ms->smp.threads, &topo_ids); + return topo_ids.pkg_id % ms->numa_state->num_nodes; } =20 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) @@ -167,7 +167,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineS= tate *ms) sizeof(CPUArchId) * max_cpus); ms->possible_cpus->len =3D max_cpus; for (i =3D 0; i < ms->possible_cpus->len; i++) { - X86CPUTopoInfo topo; + X86CPUTopoIDs topo_ids; =20 ms->possible_cpus->cpus[i].type =3D ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count =3D 1; @@ -175,17 +175,17 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(Machin= eState *ms) x86_cpu_apic_id_from_index(x86ms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, x86ms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo); + ms->smp.threads, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; - ms->possible_cpus->cpus[i].props.socket_id =3D topo.pkg_id; + ms->possible_cpus->cpus[i].props.socket_id =3D topo_ids.pkg_id; if (x86ms->smp_dies > 1) { ms->possible_cpus->cpus[i].props.has_die_id =3D true; - ms->possible_cpus->cpus[i].props.die_id =3D topo.die_id; + ms->possible_cpus->cpus[i].props.die_id =3D topo_ids.die_id; } ms->possible_cpus->cpus[i].props.has_core_id =3D true; - ms->possible_cpus->cpus[i].props.core_id =3D topo.core_id; + ms->possible_cpus->cpus[i].props.core_id =3D topo_ids.core_id; ms->possible_cpus->cpus[i].props.has_thread_id =3D true; - ms->possible_cpus->cpus[i].props.thread_id =3D topo.smt_id; + ms->possible_cpus->cpus[i].props.thread_id =3D topo_ids.smt_id; } return ms->possible_cpus; } diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 4ff5b2da6c..6c184f3115 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -45,12 +45,12 @@ */ typedef uint32_t apic_id_t; =20 -typedef struct X86CPUTopoInfo { +typedef struct X86CPUTopoIDs { unsigned pkg_id; unsigned die_id; unsigned core_id; unsigned smt_id; -} X86CPUTopoInfo; +} X86CPUTopoIDs; =20 /* Return the bit width needed for 'count' IDs */ @@ -122,12 +122,12 @@ static inline unsigned apicid_pkg_offset(unsigned nr_= dies, static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, - const X86CPUTopoInfo *topo) + const X86CPUTopoIDs *topo_ids) { - return (topo->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_threa= ds)) | - (topo->die_id << apicid_die_offset(nr_dies, nr_cores, nr_threa= ds)) | - (topo->core_id << apicid_core_offset(nr_dies, nr_cores, nr_threa= ds)) | - topo->smt_id; + return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_t= hreads)) | + (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_t= hreads)) | + (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_= threads)) | + topo_ids->smt_id; } =20 /* Calculate thread/core/package IDs for a specific topology, @@ -137,12 +137,12 @@ static inline void x86_topo_ids_from_idx(unsigned nr_= dies, unsigned nr_cores, unsigned nr_threads, unsigned cpu_index, - X86CPUTopoInfo *topo) + X86CPUTopoIDs *topo_ids) { - topo->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); - topo->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; - topo->core_id =3D cpu_index / nr_threads % nr_cores; - topo->smt_id =3D cpu_index % nr_threads; + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); + topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; + topo_ids->smt_id =3D cpu_index % nr_threads; } =20 /* Calculate thread/core/package IDs for a specific topology, @@ -152,17 +152,17 @@ static inline void x86_topo_ids_from_apicid(apic_id_t= apicid, unsigned nr_dies, unsigned nr_cores, unsigned nr_threads, - X86CPUTopoInfo *topo) + X86CPUTopoIDs *topo_ids) { - topo->smt_id =3D apicid & + topo_ids->smt_id =3D apicid & ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threa= ds)); - topo->core_id =3D + topo_ids->core_id =3D (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_thre= ads)); - topo->die_id =3D + topo_ids->die_id =3D (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threa= ds)); - topo->pkg_id =3D apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr_thr= eads); + topo_ids->pkg_id =3D apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr= _threads); } =20 /* Make APIC ID for the CPU 'cpu_index' @@ -174,9 +174,9 @@ static inline apic_id_t x86_apicid_from_cpu_idx(unsigne= d nr_dies, unsigned nr_threads, unsigned cpu_index) { - X86CPUTopoInfo topo; - x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo); - return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo); + X86CPUTopoIDs topo_ids; + x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_= ids); + return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids); } =20 #endif /* HW_I386_TOPOLOGY_H */ From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Subject: [PATCH v4 02/16] hw/i386: Introduce X86CPUTopoInfo to contain topology info From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Thu, 13 Feb 2020 12:16:37 -0600 Message-ID: <158161779774.48948.3579168862801203963.stgit@naples-babu.amd.com> In-Reply-To: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> References: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SN6PR05CA0019.namprd05.prod.outlook.com (2603:10b6:805:de::32) To CY4PR12MB1574.namprd12.prod.outlook.com (2603:10b6:910:e::23) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 568460ee-748c-4286-41ec-08d7b0b0de96 X-MS-TrafficTypeDiagnostic: CY4PR12MB1318:|CY4PR12MB1318: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2733; 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Add X86CPUTopoInfo which will have all the topology informations required to build the cpu topology. There is no functional changes. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- hw/i386/pc.c | 14 ++++++++------ hw/i386/x86.c | 28 +++++++++++++++++++++------- include/hw/i386/topology.h | 38 ++++++++++++++++++++++++-------------- 3 files changed, 53 insertions(+), 27 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 3a580f6a60..2adf7f6afa 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1741,6 +1741,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, X86MachineState *x86ms =3D X86_MACHINE(pcms); unsigned int smp_cores =3D ms->smp.cores; unsigned int smp_threads =3D ms->smp.threads; + X86CPUTopoInfo topo_info; =20 if(!object_dynamic_cast(OBJECT(cpu), ms->cpu_type)) { error_setg(errp, "Invalid CPU type, expected cpu type: '%s'", @@ -1748,6 +1749,10 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_= dev, return; } =20 + topo_info.dies_per_pkg =3D x86ms->smp_dies; + topo_info.cores_per_die =3D smp_cores; + topo_info.threads_per_core =3D smp_threads; + env->nr_dies =3D x86ms->smp_dies; =20 /* @@ -1803,16 +1808,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; - cpu->apic_id =3D apicid_from_topo_ids(x86ms->smp_dies, smp_cores, - smp_threads, &topo_ids); + cpu->apic_id =3D apicid_from_topo_ids(&topo_info, &topo_ids); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms =3D MACHINE(pcms); =20 - x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, - smp_cores, smp_threads, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -1833,8 +1836,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizef= n() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ - x86_topo_ids_from_apicid(cpu->apic_id, x86ms->smp_dies, - smp_cores, smp_threads, &topo_ids); + x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_id= s.pkg_id); diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 4a112c8e30..f18cab8e5c 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -65,11 +65,15 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x8= 6ms, { MachineState *ms =3D MACHINE(x86ms); X86MachineClass *x86mc =3D X86_MACHINE_GET_CLASS(x86ms); + X86CPUTopoInfo topo_info; uint32_t correct_id; static bool warned; =20 - correct_id =3D x86_apicid_from_cpu_idx(x86ms->smp_dies, ms->smp.cores, - ms->smp.threads, cpu_index); + topo_info.dies_per_pkg =3D x86ms->smp_dies; + topo_info.cores_per_die =3D ms->smp.cores; + topo_info.threads_per_core =3D ms->smp.threads; + + correct_id =3D x86_apicid_from_cpu_idx(&topo_info, cpu_index); if (x86mc->compat_apic_id_mode) { if (cpu_index !=3D correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -140,19 +144,25 @@ int64_t x86_get_default_cpu_node_id(const MachineStat= e *ms, int idx) { X86CPUTopoIDs topo_ids; X86MachineState *x86ms =3D X86_MACHINE(ms); + X86CPUTopoInfo topo_info; + + topo_info.dies_per_pkg =3D x86ms->smp_dies; + topo_info.cores_per_die =3D ms->smp.cores; + topo_info.threads_per_core =3D ms->smp.threads; + =20 assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - x86ms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo_ids); + &topo_info, &topo_ids); return topo_ids.pkg_id % ms->numa_state->num_nodes; } =20 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms) { X86MachineState *x86ms =3D X86_MACHINE(ms); - int i; unsigned int max_cpus =3D ms->smp.max_cpus; + X86CPUTopoInfo topo_info; + int i; =20 if (ms->possible_cpus) { /* @@ -166,6 +176,11 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(Machine= State *ms) ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + sizeof(CPUArchId) * max_cpus); ms->possible_cpus->len =3D max_cpus; + + topo_info.dies_per_pkg =3D x86ms->smp_dies; + topo_info.cores_per_die =3D ms->smp.cores; + topo_info.threads_per_core =3D ms->smp.threads; + for (i =3D 0; i < ms->possible_cpus->len; i++) { X86CPUTopoIDs topo_ids; =20 @@ -174,8 +189,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineS= tate *ms) ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(x86ms, i); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - x86ms->smp_dies, ms->smp.cores, - ms->smp.threads, &topo_ids); + &topo_info, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo_ids.pkg_id; if (x86ms->smp_dies > 1) { diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 6c184f3115..cf1935d548 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -52,6 +52,12 @@ typedef struct X86CPUTopoIDs { unsigned smt_id; } X86CPUTopoIDs; =20 +typedef struct X86CPUTopoInfo { + unsigned dies_per_pkg; + unsigned cores_per_die; + unsigned threads_per_core; +} X86CPUTopoInfo; + /* Return the bit width needed for 'count' IDs */ static unsigned apicid_bitwidth_for_count(unsigned count) @@ -119,11 +125,13 @@ static inline unsigned apicid_pkg_offset(unsigned nr_= dies, * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { + unsigned nr_dies =3D topo_info->dies_per_pkg; + unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_threads =3D topo_info->threads_per_core; + return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_t= hreads)) | (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_t= hreads)) | (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_= threads)) | @@ -133,12 +141,14 @@ static inline apic_id_t apicid_from_topo_ids(unsigned= nr_dies, /* Calculate thread/core/package IDs for a specific topology, * based on (contiguous) CPU index */ -static inline void x86_topo_ids_from_idx(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, unsigned cpu_index, X86CPUTopoIDs *topo_ids) { + unsigned nr_dies =3D topo_info->dies_per_pkg; + unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_threads =3D topo_info->threads_per_core; + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; @@ -149,11 +159,13 @@ static inline void x86_topo_ids_from_idx(unsigned nr_= dies, * based on APIC ID */ static inline void x86_topo_ids_from_apicid(apic_id_t apicid, - unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, + X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids) { + unsigned nr_dies =3D topo_info->dies_per_pkg; + unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_threads =3D topo_info->threads_per_core; + topo_ids->smt_id =3D apicid & ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threa= ds)); topo_ids->core_id =3D @@ -169,14 +181,12 @@ static inline void x86_topo_ids_from_apicid(apic_id_t= apicid, * * 'cpu_index' is a sequential, contiguous ID for the CPU. */ -static inline apic_id_t x86_apicid_from_cpu_idx(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads, +static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, unsigned cpu_index) { X86CPUTopoIDs topo_ids; - x86_topo_ids_from_idx(nr_dies, nr_cores, nr_threads, cpu_index, &topo_= ids); - return apicid_from_topo_ids(nr_dies, nr_cores, nr_threads, &topo_ids); + x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); + return apicid_from_topo_ids(topo_info, &topo_ids); } =20 #endif /* HW_I386_TOPOLOGY_H */ From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=amd.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581617932765330.77825485186554; Thu, 13 Feb 2020 10:18:52 -0800 (PST) Received: from localhost ([::1]:57580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2J4d-0003XC-EI for importer@patchew.org; Thu, 13 Feb 2020 13:18:51 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40295) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2J2f-0001W5-TE for qemu-devel@nongnu.org; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YW3rCrEdc/3pJaFHqE7eUXTFvvtD4rmyVnDd2QJSrNSgDovlEwp0Do0CqZrzFbjo8g6NiaFJKGf891gls2q+03wewJSo+8NUcYgtbPafExY/VDMp/2yVTCEDOSQpuu0oE7pgD7la03yKYGUwcxkVD3Ziyo/3iBtEVANJ8KrvFvN3pC7wdfN45mIGKijxLNU60e4xqAc1E3b8NNA08Fft6pr3L8D0bIvBN0LvLLArT0QSyquWdN6UoB5uRKsyrOIOlPTmVtPIH/CxiUPly/Yf4KGRIIlO6Wu0A81X2dP4DfrAdSmh63i0hFcNFl+j5hbrKh00owUcRmO/k4SsVCSj8nrZF1HGXXV7WCC/hUd2LTYcs27/MsvAzhKO8ERH5NM/Y95AkVDnTJvWSm0/CqFjE0Dz97fHTRy9M64FhOuvmuSmBCeS7OpGZZfPqvy+Ogk/ X-MS-Exchange-AntiSpam-MessageData: kylVbY6Jh0i3EOPsx5VPpDCNP+ko9mX15PSIT8SZUjDFX8zUJF55DPk6+WwWSAG2c4s1tISxVIRsQf4WTDtX+KQC/Jd3sg5V+vTO6nu4bKMtpeGhqZQ7p2tcJwA2AK3Un0CxOmXsVyLc62EUshLliQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4fdaf45b-aa2c-4558-b72e-08d7b0b0e28f X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:16:45.9715 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 3ndQWLiwaHnpA9UgI/welMORmy3t6cDL/5cBaWcQxhzxmpAyzP40PzJuqf7qaXZv X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1318 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.236.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) Now that we have all the parameters in X86CPUTopoInfo, we can just pass the structure to calculate the offsets and width. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- include/hw/i386/topology.h | 64 ++++++++++++++--------------------------= ---- target/i386/cpu.c | 23 ++++++++-------- 2 files changed, 32 insertions(+), 55 deletions(-) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index cf1935d548..ba52d49079 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -69,56 +69,42 @@ static unsigned apicid_bitwidth_for_count(unsigned coun= t) =20 /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ -static inline unsigned apicid_smt_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_threads); + return apicid_bitwidth_for_count(topo_info->threads_per_core); } =20 /* Bit width of the Core_ID field */ -static inline unsigned apicid_core_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_cores); + return apicid_bitwidth_for_count(topo_info->cores_per_die); } =20 /* Bit width of the Die_ID field */ -static inline unsigned apicid_die_width(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) { - return apicid_bitwidth_for_count(nr_dies); + return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } =20 /* Bit offset of the Core_ID field */ -static inline unsigned apicid_core_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) { - return apicid_smt_width(nr_dies, nr_cores, nr_threads); + return apicid_smt_width(topo_info); } =20 /* Bit offset of the Die_ID field */ -static inline unsigned apicid_die_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) { - return apicid_core_offset(nr_dies, nr_cores, nr_threads) + - apicid_core_width(nr_dies, nr_cores, nr_threads); + return apicid_core_offset(topo_info) + apicid_core_width(topo_info); } =20 /* Bit offset of the Pkg_ID (socket ID) field */ -static inline unsigned apicid_pkg_offset(unsigned nr_dies, - unsigned nr_cores, - unsigned nr_threads) +static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) { - return apicid_die_offset(nr_dies, nr_cores, nr_threads) + - apicid_die_width(nr_dies, nr_cores, nr_threads); + return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } =20 /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID @@ -128,13 +114,9 @@ static inline unsigned apicid_pkg_offset(unsigned nr_d= ies, static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, const X86CPUTopoIDs *topo_ids) { - unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_die; - unsigned nr_threads =3D topo_info->threads_per_core; - - return (topo_ids->pkg_id << apicid_pkg_offset(nr_dies, nr_cores, nr_t= hreads)) | - (topo_ids->die_id << apicid_die_offset(nr_dies, nr_cores, nr_t= hreads)) | - (topo_ids->core_id << apicid_core_offset(nr_dies, nr_cores, nr_= threads)) | + return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | + (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->core_id << apicid_core_offset(topo_info)) | topo_ids->smt_id; } =20 @@ -162,19 +144,15 @@ static inline void x86_topo_ids_from_apicid(apic_id_t= apicid, X86CPUTopoInfo *topo_info, X86CPUTopoIDs *topo_ids) { - unsigned nr_dies =3D topo_info->dies_per_pkg; - unsigned nr_cores =3D topo_info->cores_per_die; - unsigned nr_threads =3D topo_info->threads_per_core; - topo_ids->smt_id =3D apicid & - ~(0xFFFFFFFFUL << apicid_smt_width(nr_dies, nr_cores, nr_threa= ds)); + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); topo_ids->core_id =3D - (apicid >> apicid_core_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_core_width(nr_dies, nr_cores, nr_thre= ads)); + (apicid >> apicid_core_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); topo_ids->die_id =3D - (apicid >> apicid_die_offset(nr_dies, nr_cores, nr_threads)) & - ~(0xFFFFFFFFUL << apicid_die_width(nr_dies, nr_cores, nr_threa= ds)); - topo_ids->pkg_id =3D apicid >> apicid_pkg_offset(nr_dies, nr_cores, nr= _threads); + (apicid >> apicid_die_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); + topo_ids->pkg_id =3D apicid >> apicid_pkg_offset(topo_info); } =20 /* Make APIC ID for the CPU 'cpu_index' diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ba5e9d5d6b..7e630f47ac 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5316,6 +5316,11 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, uint32_t die_offset; uint32_t limit; uint32_t signature[3]; + X86CPUTopoInfo topo_info; + + topo_info.dies_per_pkg =3D env->nr_dies; + topo_info.cores_per_die =3D cs->nr_cores; + topo_info.threads_per_core =3D cs->nr_threads; =20 /* Calculate & apply limits for different index ranges */ if (index >=3D 0xC0000000) { @@ -5402,8 +5407,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - die_offset =3D apicid_die_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + die_offset =3D apicid_die_offset(&topo_info); if (cpu->enable_l3_cache) { encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, (1 << die_offset), cs->nr_cores, @@ -5494,14 +5498,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, =20 switch (count) { case 0: - *eax =3D apicid_core_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax =3D apicid_core_offset(&topo_info); *ebx =3D cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_pkg_offset(env->nr_dies, - cs->nr_cores, cs->nr_threads); + *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -5525,20 +5527,17 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, *edx =3D cpu->apic_id; switch (count) { case 0: - *eax =3D apicid_core_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax =3D apicid_core_offset(&topo_info); *ebx =3D cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_die_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax =3D apicid_die_offset(&topo_info); *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: - *eax =3D apicid_pkg_offset(env->nr_dies, cs->nr_cores, - cs->nr_threads); + *eax =3D apicid_pkg_offset(&topo_info); *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; 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Move the data structure X86CPUTopoIDs and X86CPUTopoInfo into x86.h. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost --- hw/i386/pc.c | 4 +--- hw/i386/x86.c | 14 +++----------- include/hw/i386/topology.h | 26 ++++++++++---------------- include/hw/i386/x86.h | 17 +++++++++++++++++ 4 files changed, 31 insertions(+), 30 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 2adf7f6afa..9803413dd9 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1749,9 +1749,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, return; } =20 - topo_info.dies_per_pkg =3D x86ms->smp_dies; - topo_info.cores_per_die =3D smp_cores; - topo_info.threads_per_core =3D smp_threads; + init_topo_info(&topo_info, x86ms); =20 env->nr_dies =3D x86ms->smp_dies; =20 diff --git a/hw/i386/x86.c b/hw/i386/x86.c index f18cab8e5c..083effb2f5 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -63,15 +63,12 @@ static size_t pvh_start_addr; uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86ms, unsigned int cpu_index) { - MachineState *ms =3D MACHINE(x86ms); X86MachineClass *x86mc =3D X86_MACHINE_GET_CLASS(x86ms); X86CPUTopoInfo topo_info; uint32_t correct_id; static bool warned; =20 - topo_info.dies_per_pkg =3D x86ms->smp_dies; - topo_info.cores_per_die =3D ms->smp.cores; - topo_info.threads_per_core =3D ms->smp.threads; + init_topo_info(&topo_info, x86ms); =20 correct_id =3D x86_apicid_from_cpu_idx(&topo_info, cpu_index); if (x86mc->compat_apic_id_mode) { @@ -146,10 +143,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState= *ms, int idx) X86MachineState *x86ms =3D X86_MACHINE(ms); X86CPUTopoInfo topo_info; =20 - topo_info.dies_per_pkg =3D x86ms->smp_dies; - topo_info.cores_per_die =3D ms->smp.cores; - topo_info.threads_per_core =3D ms->smp.threads; - + init_topo_info(&topo_info, x86ms); =20 assert(idx < ms->possible_cpus->len); x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, @@ -177,9 +171,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineS= tate *ms) sizeof(CPUArchId) * max_cpus); ms->possible_cpus->len =3D max_cpus; =20 - topo_info.dies_per_pkg =3D x86ms->smp_dies; - topo_info.cores_per_die =3D ms->smp.cores; - topo_info.threads_per_core =3D ms->smp.threads; + init_topo_info(&topo_info, x86ms); =20 for (i =3D 0; i < ms->possible_cpus->len; i++) { X86CPUTopoIDs topo_ids; diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index ba52d49079..ef0ab0b6a3 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -40,23 +40,17 @@ =20 =20 #include "qemu/bitops.h" +#include "hw/i386/x86.h" =20 -/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC suppo= rt - */ -typedef uint32_t apic_id_t; - -typedef struct X86CPUTopoIDs { - unsigned pkg_id; - unsigned die_id; - unsigned core_id; - unsigned smt_id; -} X86CPUTopoIDs; - -typedef struct X86CPUTopoInfo { - unsigned dies_per_pkg; - unsigned cores_per_die; - unsigned threads_per_core; -} X86CPUTopoInfo; +static inline void init_topo_info(X86CPUTopoInfo *topo_info, + const X86MachineState *x86ms) +{ + MachineState *ms =3D MACHINE(x86ms); + + topo_info->dies_per_pkg =3D x86ms->smp_dies; + topo_info->cores_per_die =3D ms->smp.cores; + topo_info->threads_per_core =3D ms->smp.threads; +} =20 /* Return the bit width needed for 'count' IDs */ diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 4b84917885..ad62b01cf2 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -36,6 +36,23 @@ typedef struct { bool compat_apic_id_mode; } X86MachineClass; =20 +/* APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC suppo= rt + */ +typedef uint32_t apic_id_t; + +typedef struct X86CPUTopoIDs { + unsigned pkg_id; + unsigned die_id; + unsigned core_id; + unsigned smt_id; +} X86CPUTopoIDs; + +typedef struct X86CPUTopoInfo { + unsigned dies_per_pkg; + unsigned cores_per_die; + unsigned threads_per_core; +} X86CPUTopoInfo; + typedef struct { /*< private >*/ MachineState parent; From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Subject: [PATCH v4 05/16] machine: Add SMP Sockets in CpuTopology From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Thu, 13 Feb 2020 12:16:58 -0600 Message-ID: <158161781807.48948.6804322747644119810.stgit@naples-babu.amd.com> In-Reply-To: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> References: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SN1PR12CA0086.namprd12.prod.outlook.com (2603:10b6:802:21::21) To CY4PR12MB1574.namprd12.prod.outlook.com (2603:10b6:910:e::23) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 224af5bf-d630-4073-8591-08d7b0b0eabb X-MS-TrafficTypeDiagnostic: CY4PR12MB1318:|CY4PR12MB1318: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:7219; 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The socket information required to build the apic id in EPYC mode. Right now socket information is not passed to down when decoding the apic id. Add the socket information here. Signed-off-by: Babu Moger Reviewed-by: Eduardo Habkost Reviewed-by: Igor Mammedov --- hw/core/machine.c | 1 + hw/i386/pc.c | 1 + include/hw/boards.h | 2 ++ vl.c | 1 + 4 files changed, 5 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index 023548b4f3..ea03c25565 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -789,6 +789,7 @@ static void smp_parse(MachineState *ms, QemuOpts *opts) ms->smp.cpus =3D cpus; ms->smp.cores =3D cores; ms->smp.threads =3D threads; + ms->smp.sockets =3D sockets; } =20 if (ms->smp.cpus > 1) { diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 9803413dd9..f13721ac43 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -978,6 +978,7 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) ms->smp.cpus =3D cpus; ms->smp.cores =3D cores; ms->smp.threads =3D threads; + ms->smp.sockets =3D sockets; x86ms->smp_dies =3D dies; } =20 diff --git a/include/hw/boards.h b/include/hw/boards.h index 24cbeecbae..a50a2d779e 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -256,12 +256,14 @@ typedef struct DeviceMemoryState { * @cpus: the number of present logical processors on the machine * @cores: the number of cores in one package * @threads: the number of threads in one core + * @sockets: the number of sockets on the machine * @max_cpus: the maximum number of logical processors on the machine */ typedef struct CpuTopology { unsigned int cpus; unsigned int cores; unsigned int threads; + unsigned int sockets; unsigned int max_cpus; } CpuTopology; =20 diff --git a/vl.c b/vl.c index 94508300c3..3f6d396a95 100644 --- a/vl.c +++ b/vl.c @@ -3819,6 +3819,7 @@ int main(int argc, char **argv, char **envp) current_machine->smp.max_cpus =3D machine_class->default_cpus; current_machine->smp.cores =3D 1; current_machine->smp.threads =3D 1; + current_machine->smp.sockets =3D 1; =20 machine_class->smp_parse(current_machine, qemu_opts_find(qemu_find_opts("smp-opts"), NULL)); From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=amd.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581618247536606.585308721505; Thu, 13 Feb 2020 10:24:07 -0800 (PST) Received: from localhost ([::1]:57674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2J9g-0001jS-9W for importer@patchew.org; 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This is required to build EPYC mode topology. Signed-off-by: Babu Moger --- hw/i386/pc.c | 1 + hw/i386/x86.c | 2 ++ include/hw/i386/topology.h | 2 ++ include/hw/i386/x86.h | 1 + target/i386/cpu.c | 1 + target/i386/cpu.h | 1 + 6 files changed, 8 insertions(+) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f13721ac43..02fdb3d506 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1753,6 +1753,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, init_topo_info(&topo_info, x86ms); =20 env->nr_dies =3D x86ms->smp_dies; + env->nr_nodes =3D ms->numa_state->num_nodes / ms->smp.sockets; =20 /* * If APIC ID is not set, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 083effb2f5..3d944f68e6 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -89,11 +89,13 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic_i= d, Error **errp) Object *cpu =3D NULL; Error *local_err =3D NULL; CPUX86State *env =3D NULL; + MachineState *ms =3D MACHINE(x86ms); =20 cpu =3D object_new(MACHINE(x86ms)->cpu_type); =20 env =3D &X86_CPU(cpu)->env; env->nr_dies =3D x86ms->smp_dies; + env->nr_nodes =3D ms->numa_state->num_nodes / ms->smp.sockets; =20 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); object_property_set_bool(cpu, true, "realized", &local_err); diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index ef0ab0b6a3..522c77e6a9 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -41,12 +41,14 @@ =20 #include "qemu/bitops.h" #include "hw/i386/x86.h" +#include "sysemu/numa.h" =20 static inline void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms) { MachineState *ms =3D MACHINE(x86ms); =20 + topo_info->nodes_per_pkg =3D ms->numa_state->num_nodes / ms->smp.socke= ts; topo_info->dies_per_pkg =3D x86ms->smp_dies; topo_info->cores_per_die =3D ms->smp.cores; topo_info->threads_per_core =3D ms->smp.threads; diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index ad62b01cf2..d76fd0bbb1 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -48,6 +48,7 @@ typedef struct X86CPUTopoIDs { } X86CPUTopoIDs; =20 typedef struct X86CPUTopoInfo { + unsigned nodes_per_pkg; unsigned dies_per_pkg; unsigned cores_per_die; unsigned threads_per_core; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 7e630f47ac..5d6edfd09b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6761,6 +6761,7 @@ static void x86_cpu_initfn(Object *obj) FeatureWord w; =20 env->nr_dies =3D 1; + env->nr_nodes =3D 1; cpu_set_cpustate_pointers(cpu); =20 object_property_add(obj, "family", "int", diff --git a/target/i386/cpu.h b/target/i386/cpu.h index af282936a7..627a8cb9be 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1603,6 +1603,7 @@ typedef struct CPUX86State { TPRAccess tpr_access_type; =20 unsigned nr_dies; + unsigned nr_nodes; } CPUX86State; =20 struct kvm_msrs; From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Subject: [PATCH v4 07/16] hw/i386: Rename apicid_from_topo_ids to x86_apicid_from_topo_ids From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Thu, 13 Feb 2020 12:17:12 -0600 Message-ID: <158161783201.48948.10267676745424104315.stgit@naples-babu.amd.com> In-Reply-To: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> References: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SN1PR12CA0110.namprd12.prod.outlook.com (2603:10b6:802:21::45) To CY4PR12MB1574.namprd12.prod.outlook.com (2603:10b6:910:e::23) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 8116797b-6051-45f2-94d4-08d7b0b0f2ed X-MS-TrafficTypeDiagnostic: CY4PR12MB1318:|CY4PR12MB1318: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:534; 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No functional change. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov --- hw/i386/pc.c | 2 +- include/hw/i386/topology.h | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 02fdb3d506..be72a49716 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1808,7 +1808,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; - cpu->apic_id =3D apicid_from_topo_ids(&topo_info, &topo_ids); + cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 522c77e6a9..3158157430 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -107,8 +107,8 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInfo= *topo_info) * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. */ -static inline apic_id_t apicid_from_topo_ids(X86CPUTopoInfo *topo_info, - const X86CPUTopoIDs *topo_ids) +static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo= _ids) { return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | (topo_ids->die_id << apicid_die_offset(topo_info)) | @@ -160,7 +160,7 @@ static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUT= opoInfo *topo_info, { X86CPUTopoIDs topo_ids; x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); - return apicid_from_topo_ids(topo_info, &topo_ids); + return x86_apicid_from_topo_ids(topo_info, &topo_ids); } =20 #endif /* HW_I386_TOPOLOGY_H */ From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=amd.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581618481271104.29124262351377; Thu, 13 Feb 2020 10:28:01 -0800 (PST) Received: from localhost ([::1]:57736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2JDT-0007BJ-JY for importer@patchew.org; Thu, 13 Feb 2020 13:27:59 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41532) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2J3F-0002IO-ON for qemu-devel@nongnu.org; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: U3nXuDyaFbtrD+Bds2qg7qVdzmwLZV/zVDvCWf7+rqKDuMmQcj4H46KxxXnQ9IgSfL4x066J/N/M3fajakvw0vsBhnCSDysVEGGZ0ie9fGGVT6dpP5ALxutxYlqpHUlTa8T3xp4v+IwcOpQe1jtUmHZ5L/caYeQbbqWqnownFkp7S+c3jNmT1i/vH50JH/4+oBo/qZH6fP+FA6kvgAjFECBhU7yRXWufCqcK5R0SEzUVbqiMx6SCFfe7aqsJn/cZum2NY6dQwqEus4InuqZb+3dME8Cs3Vot+6pWg06tpQfScsQIb1RVeMOHFF+czae0hK79FiKBcLXOonFvMNJ4Pim9AtK6ramr3ogLF1f3LVZWviqWKzRBfB8JVpKOR0VdQo4JdTfMa0lCDKZJaBq8aNiHfNBczmsdC5RgvDh5FPA2dCUSQIwwsWdzmsBMpIhmJto5yAI5iMFVM/DtJHo/h+hNj+s4sVcgvM26rWOQOSIWycUNg9L84kWXnThLy+gB1PoHo6wVkOIvgHxfXtxSDg== X-MS-Exchange-AntiSpam-MessageData: 9kOkYgQkTZsC4u+RL/SaErEiwfpVxjwR1flAuIdGJQfpbKykxDTknPdPNYA54ZPLtQMqKFhS4VPkz3FaKbqYVWKMBiE9BmvZNdyS7Ko61Iz3/+YT3a0lH41MnbEQA2NpGCzXHl+O/aG7UKsVEy353w== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d335fec2-e8e9-46c9-3846-08d7b0b0f710 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:17:20.4141 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: VT5L/qxj0IHA6xKKUGWNRfEvSl7d0FrHb2Fp+IPIUMptvp0ed2GpE5N485h+iokP X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1318 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.236.59 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) These functions add support for building EPYC mode topology given the smp details like numa nodes, cores, threads and sockets. The new apic id decoding is mostly similar to current apic id decoding except that it adds a new field llc_id when numa configured. Removes all the hardcoded values. Subsequent patches will use these functions to build the topology. Following functions are added. apicid_llc_width_epyc apicid_llc_offset_epyc apicid_pkg_offset_epyc apicid_from_topo_ids_epyc x86_topo_ids_from_idx_epyc x86_topo_ids_from_apicid_epyc x86_apicid_from_cpu_idx_epyc The topology details are available in Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip Signed-off-by: Babu Moger --- include/hw/i386/topology.h | 93 ++++++++++++++++++++++++++++++++++++++++= ++++ include/hw/i386/x86.h | 1=20 2 files changed, 94 insertions(+) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index 3158157430..d9319dc2ac 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -83,6 +83,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *= topo_info) return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } =20 +/* Bit width of the node_id field per socket */ +static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info) +{ + return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1)); +} /* Bit offset of the Core_ID field */ static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) @@ -103,6 +108,94 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoInf= o *topo_info) return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } =20 +#define LLC_OFFSET 3 /* Minimum LLC offset if numa configured */ + +/* Bit offset of the node_id field */ +static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info) +{ + unsigned offset =3D apicid_die_offset(topo_info) + + apicid_die_width(topo_info); + + if (topo_info->nodes_per_pkg) { + return MAX(LLC_OFFSET, offset); + } else { + return offset; + } +} + +/* Bit offset of the Pkg_ID (socket ID) field */ +static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info) +{ + return apicid_node_offset_epyc(topo_info) + apicid_node_width_epyc(top= o_info); +} + +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID + * + * The caller must make sure core_id < nr_cores and smt_id < nr_threads. + */ +static inline apic_id_t x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo= _info, + const X86CPUTopoIDs = *topo_ids) +{ + return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) | + (topo_ids->node_id << apicid_node_offset_epyc(topo_info)) | + (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->core_id << apicid_core_offset(topo_info)) | + topo_ids->smt_id; +} + +static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info, + unsigned cpu_index, + X86CPUTopoIDs *topo_ids) +{ + unsigned nr_nodes =3D MAX(topo_info->nodes_per_pkg, 1); + unsigned nr_dies =3D topo_info->dies_per_pkg; + unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_threads =3D topo_info->threads_per_core; + unsigned cores_per_node =3D DIV_ROUND_UP((nr_dies * nr_cores * nr_thre= ads), + nr_nodes); + + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); + topo_ids->node_id =3D (cpu_index / cores_per_node) % nr_nodes; + topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; + topo_ids->smt_id =3D cpu_index % nr_threads; +} + +/* + * Calculate thread/core/package IDs for a specific topology, + * based on APIC ID + */ +static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid, + X86CPUTopoInfo *topo_info, + X86CPUTopoIDs *topo_ids) +{ + topo_ids->smt_id =3D apicid & + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); + topo_ids->core_id =3D + (apicid >> apicid_core_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); + topo_ids->die_id =3D + (apicid >> apicid_die_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); + topo_ids->node_id =3D + (apicid >> apicid_node_offset_epyc(topo_info)) & + ~(0xFFFFFFFFUL << apicid_node_width_epyc(topo_info)); + topo_ids->pkg_id =3D apicid >> apicid_pkg_offset_epyc(topo_info); +} + +/* + * Make APIC ID for the CPU 'cpu_index' + * + * 'cpu_index' is a sequential, contiguous ID for the CPU. + */ +static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_= info, + unsigned cpu_index) +{ + X86CPUTopoIDs topo_ids; + x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids); + return x86_apicid_from_topo_ids_epyc(topo_info, &topo_ids); +} /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index d76fd0bbb1..38c2d27910 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -42,6 +42,7 @@ typedef uint32_t apic_id_t; =20 typedef struct X86CPUTopoIDs { unsigned pkg_id; + unsigned node_id; unsigned die_id; unsigned core_id; unsigned smt_id; From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581618484173180.43817058928812; Thu, 13 Feb 2020 10:28:04 -0800 (PST) Received: from localhost ([::1]:57738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2JDW-0007Db-Sk for importer@patchew.org; Thu, 13 Feb 2020 13:28:02 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41777) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2J3L-0002Wk-RU for qemu-devel@nongnu.org; Thu, 13 Feb 2020 13:17:33 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j2J3K-0008FS-2B for qemu-devel@nongnu.org; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: YipMIKRuEVt7cE7nG8t0AJdVNfJ9BldWyGeHz4QZRYhzwGU1QoxuZEkSXyD4V5soXTi3ZQpN74WyIM6UBKt8KSIN2i8PDbM1jSmJb7nW1XrGoSoOOej4zf+qszlMTv4CffnCDkxCASH/UIJ4KN7s80Gq6Ukmq6kFI2fZQhICI4WcLiKTimqG1m9GLOW+CLOznKklaJJLTbUh/7AnULnNYtvv7dHGqQzAhBSnBcr5en0D6SDH3ba7QNv29TNg241o6Mn2zzKaMFCLZDZ1kotfjLfYMqEGpupqHrpp8kPGD59l0JGM+9TYFqVh2lRkgycJ8Pesu27LncgoJupmr+OUDGzqO3stASGL/CshSEx+zuHsvQ/s4RFzf3QvgxPxSZ/L88ds+XgBr68VwrN+pZm4YE59pmGqdBMy+1rZRcqfGQRTId506AliqmOuKxBd34IF X-MS-Exchange-AntiSpam-MessageData: pfirflFwcjgyNSRB0BpmynG+V+QOdptZ9+oB2BAlLd50+8mcuks1DvdfzMfc9wTtFCF/Mu3yyImPoBmGE74e7eaP3h+lxSj223oM5k5rW4IKH6yzgRC4Z8MnIAlw88nK6WIn+6nKzw2uGR229R4ojw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: f3e51231-c6ff-4745-c6bd-08d7b0b0fb21 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:17:27.1821 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: PYrmspCN2iGCZiHUbf44bOVzqhdubmgKy4k0S2BUwD1lj0d/rTdEp/QedLcJAaiP X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1318 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.220.82 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Computed bodyhash is different from the expected one) Use the new functions from topology.h and delete the unused code. Given the sockets, nodes, cores and threads, the new functions generate apic id for E= PYC mode. Removes all the hardcoded values. Signed-off-by: Babu Moger --- target/i386/cpu.c | 162 +++++++++++--------------------------------------= ---- 1 file changed, 35 insertions(+), 127 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 5d6edfd09b..19675eb696 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -338,68 +338,15 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *= l2, } } =20 -/* - * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E - * Please refer to the AMD64 Architecture Programmer=E2=80=99s Manual Volu= me 3. - * Define the constants to build the cpu topology. Right now, TOPOEXT - * feature is enabled only on EPYC. So, these constants are based on - * EPYC supported configurations. We may need to handle the cases if - * these values change in future. - */ -/* Maximum core complexes in a node */ -#define MAX_CCX 2 -/* Maximum cores in a core complex */ -#define MAX_CORES_IN_CCX 4 -/* Maximum cores in a node */ -#define MAX_CORES_IN_NODE 8 -/* Maximum nodes in a socket */ -#define MAX_NODES_PER_SOCKET 4 - -/* - * Figure out the number of nodes required to build this config. - * Max cores in a node is 8 - */ -static int nodes_in_socket(int nr_cores) -{ - int nodes; - - nodes =3D DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); - - /* Hardware does not support config with 3 nodes, return 4 in that case= */ - return (nodes =3D=3D 3) ? 4 : nodes; -} - -/* - * Decide the number of cores in a core complex with the given nr_cores us= ing - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible - * L3 cache is shared across all cores in a core complex. So, this will al= so - * tell us how many cores are sharing the L3 cache. - */ -static int cores_in_core_complex(int nr_cores) -{ - int nodes; - - /* Check if we can fit all the cores in one core complex */ - if (nr_cores <=3D MAX_CORES_IN_CCX) { - return nr_cores; - } - /* Get the number of nodes required to build this config */ - nodes =3D nodes_in_socket(nr_cores); - - /* - * Divide the cores accros all the core complexes - * Return rounded up value - */ - return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); -} - /* Encode cache info for CPUID[8000001D] */ -static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, + X86CPUTopoInfo *topo_info, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { uint32_t l3_cores; + unsigned nodes =3D MAX(topo_info->nodes_per_pkg, 1); + assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -408,10 +355,13 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, CPUState *cs, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_cores =3D cores_in_core_complex(cs->nr_cores); - *eax |=3D ((l3_cores * cs->nr_threads) - 1) << 14; + l3_cores =3D DIV_ROUND_UP((topo_info->dies_per_pkg * + topo_info->cores_per_die * + topo_info->threads_per_core), + nodes); + *eax |=3D (l3_cores - 1) << 14; } else { - *eax |=3D ((cs->nr_threads - 1) << 14); + *eax |=3D ((topo_info->threads_per_core - 1) << 14); } =20 assert(cache->line_size > 0); @@ -431,55 +381,17 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, CPUState *cs, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } =20 -/* Data structure to hold the configuration info for a given core index */ -struct core_topology { - /* core complex id of the current core index */ - int ccx_id; - /* - * Adjusted core index for this core in the topology - * This can be 0,1,2,3 with max 4 cores in a core complex - */ - int core_id; - /* Node id for this core index */ - int node_id; - /* Number of nodes in this config */ - int num_nodes; -}; - -/* - * Build the configuration closely match the EPYC hardware. Using the EPYC - * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_= NODE) - * right now. This could change in future. - * nr_cores : Total number of cores in the config - * core_id : Core index of the current CPU - * topo : Data structure to hold all the config info for this core ind= ex - */ -static void build_core_topology(int nr_cores, int core_id, - struct core_topology *topo) -{ - int nodes, cores_in_ccx; - - /* First get the number of nodes required */ - nodes =3D nodes_in_socket(nr_cores); - - cores_in_ccx =3D cores_in_core_complex(nr_cores); - - topo->node_id =3D core_id / (cores_in_ccx * MAX_CCX); - topo->ccx_id =3D (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; - topo->core_id =3D core_id % cores_in_ccx; - topo->num_nodes =3D nodes; -} - /* Encode cache info for CPUID[8000001E] */ -static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, +static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *c= pu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - struct core_topology topo =3D {0}; - unsigned long nodes; + X86CPUTopoIDs topo_ids =3D {0}; + unsigned long nodes =3D MAX(topo_info->nodes_per_pkg, 1); int shift; =20 - build_core_topology(cs->nr_cores, cpu->core_id, &topo); + x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids); + *eax =3D cpu->apic_id; /* * CPUID_Fn8000001E_EBX @@ -496,12 +408,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X8= 6CPU *cpu, * 3 Core complex id * 1:0 Core id */ - if (cs->nr_threads - 1) { - *ebx =3D ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | - (topo.ccx_id << 2) | topo.core_id; - } else { - *ebx =3D (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; - } + *ebx =3D ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id = << 3) | + (topo_ids.core_id); /* * CPUID_Fn8000001E_ECX * 31:11 Reserved @@ -510,9 +418,9 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86= CPU *cpu, * 2 Socket id * 1:0 Node id */ - if (topo.num_nodes <=3D 4) { - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | - topo.node_id; + + if (nodes <=3D 4) { + *ecx =3D ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.no= de_id; } else { /* * Node id fix up. Actual hardware supports up to 4 nodes. But with @@ -527,10 +435,10 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X= 86CPU *cpu, * number of nodes. find_last_bit returns last set bit(0 based). L= eft * shift(+1) the socket id to represent all the nodes. */ - nodes =3D topo.num_nodes - 1; + nodes -=3D 1; shift =3D find_last_bit(&nodes, 8); - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift += 1)) | - topo.node_id; + *ecx =3D (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) | + topo_ids.node_id; } *edx =3D 0; } @@ -5318,6 +5226,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, uint32_t signature[3]; X86CPUTopoInfo topo_info; =20 + topo_info.nodes_per_pkg =3D env->nr_nodes; topo_info.dies_per_pkg =3D env->nr_dies; topo_info.cores_per_die =3D cs->nr_cores; topo_info.threads_per_core =3D cs->nr_threads; @@ -5737,20 +5646,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, + &topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ *eax =3D *ebx =3D *ecx =3D *edx =3D 0; @@ -5759,8 +5668,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x8000001E: assert(cpu->core_id <=3D 255); - encode_topo_cpuid8000001e(cs, cpu, - eax, ebx, ecx, edx); + encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx); break; case 0xC0000000: *eax =3D env->cpuid_xlevel2; From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Subject: [PATCH v4 10/16] hw/i386: Introduce apicid functions inside X86MachineState From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Thu, 13 Feb 2020 12:17:32 -0600 Message-ID: <158161785243.48948.11368379114010493667.stgit@naples-babu.amd.com> In-Reply-To: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> References: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: DM6PR06CA0053.namprd06.prod.outlook.com (2603:10b6:5:54::30) To CY4PR12MB1574.namprd12.prod.outlook.com (2603:10b6:910:e::23) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 6b144d26-e2ae-43d8-94a4-08d7b0b0ff5d X-MS-TrafficTypeDiagnostic: CY4PR12MB1318:|CY4PR12MB1318: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:4125; 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These functions will be loaded from X86CPUDefinition. Signed-off-by: Babu Moger --- include/hw/i386/x86.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 38c2d27910..75c2462770 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -79,6 +79,15 @@ typedef struct { uint16_t boot_cpus; unsigned smp_dies; =20 + /* Apic id specific handlers */ + uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, + unsigned cpu_index); + void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_in= fo, + X86CPUTopoIDs *topo_ids); + apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids); + uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info); + /* * Address space used by IOAPIC device. All IOAPIC interrupts * will be translated to MSI messages in the address space. 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Add the model specific handlers if apicid decoding differs from the standard sequential numbering. Signed-off-by: Babu Moger --- target/i386/cpu.c | 38 ++++++++++++++++++++++++++++++++++++++ target/i386/cpu.h | 1 + 2 files changed, 39 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 19675eb696..389b68d765 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1614,6 +1614,16 @@ typedef struct X86CPUDefinition { FeatureWordArray features; const char *model_id; CPUCaches *cache_info; + + /* Apic id specific handlers */ + uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, + unsigned cpu_index); + void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_in= fo, + X86CPUTopoIDs *topo_ids); + apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids); + uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info); + /* * Definitions for alternative versions of CPU model. * List is terminated by item with version =3D=3D 0. @@ -1654,6 +1664,34 @@ static const X86CPUVersionDefinition *x86_cpu_def_ge= t_versions(X86CPUDefinition return def->versions ?: default_version_list; } =20 +void cpu_x86_init_apicid_fns(MachineState *machine) +{ + X86CPUClass *xcc =3D X86_CPU_CLASS(object_class_by_name(machine->cpu_t= ype)); + X86CPUModel *model =3D xcc->model; + X86CPUDefinition *def =3D model->cpudef; + X86MachineState *x86ms =3D X86_MACHINE(machine); + + if (def) { + if (def->apicid_from_cpu_idx) { + x86ms->apicid_from_cpu_idx =3D def->apicid_from_cpu_idx; + } + if (def->topo_ids_from_apicid) { + x86ms->topo_ids_from_apicid =3D def->topo_ids_from_apicid; + } + if (def->apicid_from_topo_ids) { + x86ms->apicid_from_topo_ids =3D def->apicid_from_topo_ids; + } + if (def->apicid_pkg_offset) { + x86ms->apicid_pkg_offset =3D def->apicid_pkg_offset; + } + } else { + x86ms->apicid_from_cpu_idx =3D x86_apicid_from_cpu_idx; + x86ms->topo_ids_from_apicid =3D x86_topo_ids_from_apicid; + x86ms->apicid_from_topo_ids =3D x86_apicid_from_topo_ids; + x86ms->apicid_pkg_offset =3D apicid_pkg_offset; + } +} + static CPUCaches epyc_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 627a8cb9be..64a1cca690 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1889,6 +1889,7 @@ void cpu_clear_apic_feature(CPUX86State *env); void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); +void cpu_x86_init_apicid_fns(MachineState *machine); =20 /* helper.c */ bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=amd.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158161859726027.329004440811218; Thu, 13 Feb 2020 10:29:57 -0800 (PST) Received: from localhost ([::1]:57762 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2JFL-00029V-Um for importer@patchew.org; Thu, 13 Feb 2020 13:29:55 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:42610) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2J3f-0003Cy-8t for qemu-devel@nongnu.org; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ec72NGd/irsb4CpFCsmxAS5eAQdO+3BpsIojkIaBB70VNc+Wskn0eSkg8rxNfYyW3Pl/ebdkoYm4zSH6izaggYlfi0FhwXBKDIR3dmu4K3VGPHBahrf/5rnJcZQWPt6o0VOuFxHZ9MaL3V+lMjOTyMZlWmauN6lbQ//jk+03GCyFWBsGWG1ee7gh+41x2Uam5Uk557dQcTnFshCaVuFVEhOz76zcTUhWxTV8B/yzGRVgLSJ27ETL3fv4ubrTcJ8EVL36DOXcsKoWgZgRulLHPFc0ccli8gYA+/BnBmEE9hqATCbM5iU2AFkPVMlVXytYYmw5eGJGWOQWj5sRzX54mxe9KmSjTMBnRnNpf5UzaPVKr3yRPKzj6yRd0ed7k0EajmfoqYnQW+AXKzsXiA/DxgPQpJA9oOj6rfu1TOYTCFdFwMGKEW5AqhtQpQURuRUB X-MS-Exchange-AntiSpam-MessageData: 1Q6up3qYwaQ/9ebFw9o4Eax8QSdMzSyZL29nMa0SSoCwIQPumWDt/dRR9IUo1ssCCU1nx/2xGuXb3WNbSiBPwCdg5yuKETDN/lIAdtm/iTvz1xqVKApA4K/9R1mJMVmMea3315K5Ror0VJi7Rvq/Gw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: a4e6373a-40e4-423f-e63a-08d7b0b10771 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:17:47.8778 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: mI9hh4xq1X56NW3ZILSGYVmmWTWLQ2p+ftfAIsMXLucblcDH+qDmo0Z4RkDK4WBQ X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1222 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.223.43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) Check and Load the apicid handlers from X86CPUDefinition if available. Update the calling convention for the apicid handlers. Signed-off-by: Babu Moger --- hw/i386/pc.c | 6 +++--- hw/i386/x86.c | 27 +++++++++++++++++++++++---- 2 files changed, 26 insertions(+), 7 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index be72a49716..93063af6a8 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1808,14 +1808,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; - cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); + cpu->apic_id =3D x86ms->apicid_from_topo_ids(&topo_info, &topo_ids= ); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms =3D MACHINE(pcms); =20 - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -1836,7 +1836,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizef= n() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, topo_id= s.pkg_id); diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 3d944f68e6..b825861b85 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -52,6 +52,22 @@ /* Physical Address of PVH entry point read from kernel ELF NOTE */ static size_t pvh_start_addr; =20 +/* + * Check for apicid handlers in X86MachineState. Load them if + * not loaded already. These handlers are loaded from X86CPUDefinition. + */ +static void x86_check_apicid_handlers(MachineState *ms) +{ + X86MachineState *x86ms =3D X86_MACHINE(ms); + + if (!x86ms->apicid_from_cpu_idx || + !x86ms->topo_ids_from_apicid || + !x86ms->apicid_from_topo_ids || + !x86ms->apicid_pkg_offset) { + cpu_x86_init_apicid_fns(ms); + } +} + /* * Calculates initial APIC ID for a specific CPU index * @@ -70,7 +86,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86m= s, =20 init_topo_info(&topo_info, x86ms); =20 - correct_id =3D x86_apicid_from_cpu_idx(&topo_info, cpu_index); + correct_id =3D x86ms->apicid_from_cpu_idx(&topo_info, cpu_index); if (x86mc->compat_apic_id_mode) { if (cpu_index !=3D correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -148,8 +164,8 @@ int64_t x86_get_default_cpu_node_id(const MachineState = *ms, int idx) init_topo_info(&topo_info, x86ms); =20 assert(idx < ms->possible_cpus->len); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - &topo_info, &topo_ids); + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, + &topo_info, &topo_ids); return topo_ids.pkg_id % ms->numa_state->num_nodes; } =20 @@ -169,6 +185,9 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineS= tate *ms) return ms->possible_cpus; } =20 + /* Initialize apicid handlers */ + x86_check_apicid_handlers(ms); + ms->possible_cpus =3D g_malloc0(sizeof(CPUArchIdList) + sizeof(CPUArchId) * max_cpus); ms->possible_cpus->len =3D max_cpus; @@ -182,7 +201,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(MachineS= tate *ms) ms->possible_cpus->cpus[i].vcpus_count =3D 1; ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(x86ms, i); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, + x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, &topo_info, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo_ids.pkg_id; From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Subject: [PATCH v4 13/16] target/i386: Add EPYC model specific handlers From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Thu, 13 Feb 2020 12:17:53 -0600 Message-ID: <158161787313.48948.4764091270796216726.stgit@naples-babu.amd.com> In-Reply-To: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> References: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: DM6PR17CA0003.namprd17.prod.outlook.com (2603:10b6:5:1b3::16) To CY4PR12MB1574.namprd12.prod.outlook.com (2603:10b6:910:e::23) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: d032832e-a91f-47dd-8b1f-08d7b0b10b70 X-MS-TrafficTypeDiagnostic: CY4PR12MB1222:|CY4PR12MB1222: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:10000; X-Forefront-PRVS: 031257FE13 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(366004)(39860400002)(346002)(136003)(376002)(396003)(189003)(199004)(52116002)(66946007)(66556008)(66476007)(7696005)(26005)(5660300002)(103116003)(956004)(55016002)(4326008)(86362001)(2906002)(44832011)(186003)(16526019)(478600001)(316002)(81156014)(81166006)(966005)(8936002)(8676002); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR12MB1222; H:CY4PR12MB1574.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nAaiWZu3+yY4n4HLrHI13OqQq0MOr+oSB/MNINHe+pVnpTNZTpQ55VNw3ztcm4L/hRRvyP7MFdakxY2sUfnkIt3M6ryTbjyfkmcsy1UU3EVxjLHLohiBEBolC8xP8Z3Ry+iN+Pp8aE0zgCnE/CNPXV327yy+9Xn1xL1sOjiC6YpKmzsdiGztAOEWjpElE+3sFBCL8NLS3TpkGXmS9O0eqrt4aHGZzc0foNJ8ve7NuvIY6ioum+mZaKiyh2ZlCxHip57CjezhCV88fElC/vtmSZTSXszspTs3N9JE2EZ5KdSqewZGpcs+pa/Sia9igxmwpbjeoUOWtHAGtJ7uQH//N3fT98rdsHLWNkA5XSt4quEkoWiX02Falwr3m2gtZl+3baqRkMK2Q0imSgtWJpklEYd/KN1dCLW2LhhxH7woFqc/e4C2IU8+TGmAmTkLU9cYDwNyftRTiKq+QSUqK2Nyzdng0zTHDxBHCudqhRkFCWMDFI8RjfiYWoohirsH+f7Lua1tJ8DrATcZ5tDWFoPI/g== X-MS-Exchange-AntiSpam-MessageData: rcJf30jdMgy1Z2JIm+YxUbwomu1Bxknty1+EUp2vIIQSAp2n/yMOKAgrnayDHOprwCXg9vZpdXNG0s6B69ecetOL2iZ+5bpl/Q5OEpl8fGQQvmBMwYg4zE0fabmSL+xMrq3OJyLdyJyK8zloUxmduQ== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: d032832e-a91f-47dd-8b1f-08d7b0b10b70 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:17:54.5928 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: BN7TGUCiwfxFzB6MpA4+WTmsAIGN15AnYV8FfdUfccUrlvUDk51QmoziKvgURsrH X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1222 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.223.70 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Computed bodyhash is different from the expected one) Add the new EPYC model specific handlers to fix the apicid decoding. The APIC ID is decoded based on the sequence sockets->dies->cores->threads. This works fine for most standard AMD and other vendors' configurations, but this decoding sequence does not follow that of AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology inconsistency. When booting a guest VM, the kernel tries to validate the topology, and fin= ds it inconsistent with the enumeration of EPYC cpu models. The more details a= re in the bug https://bugzilla.redhat.com/show_bug.cgi?id=3D1728166. To fix the problem we need to build the topology as per the Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. It is available at https://www.amd.com/system/files/TechDocs/55570-B1_PUB.z= ip Here is the text from the PPR. Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize],= the number of least significant bits in the Initial APIC ID that indicate core = ID within a processor, in constructing per-core CPUID masks. Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores (MNC) that the processor could theoretically support, not the actual number= of cores that are actually implemented or enabled on the processor, as indicat= ed by Core::X86::Cpuid::SizeId[NC]. Each Core::X86::Apic::ApicId[ApicId] register is preset as follows: =E2=80=A2 ApicId[6] =3D Socket ID. =E2=80=A2 ApicId[5:4] =3D Node ID. =E2=80=A2 ApicId[3] =3D Logical CCX L3 complex ID =E2=80=A2 ApicId[2:0]=3D (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,Logi= calCoreID[1:0]} Signed-off-by: Babu Moger --- target/i386/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 389b68d765..082865d72b 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3835,6 +3835,10 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x8000001E, .model_id =3D "AMD EPYC Processor", .cache_info =3D &epyc_cache_info, + .apicid_from_cpu_idx =3D x86_apicid_from_cpu_idx_epyc, + .topo_ids_from_apicid =3D x86_topo_ids_from_apicid_epyc, + .apicid_from_topo_ids =3D x86_apicid_from_topo_ids_epyc, + .apicid_pkg_offset =3D apicid_pkg_offset_epyc, .versions =3D (X86CPUVersionDefinition[]) { { .version =3D 1 }, { From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Subject: [PATCH v4 14/16] hw/i386: Move arch_id decode inside x86_cpus_init From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Thu, 13 Feb 2020 12:17:59 -0600 Message-ID: <158161787984.48948.11401269513856632633.stgit@naples-babu.amd.com> In-Reply-To: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> References: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: DM6PR17CA0032.namprd17.prod.outlook.com (2603:10b6:5:1b3::45) To CY4PR12MB1574.namprd12.prod.outlook.com (2603:10b6:910:e::23) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: 662c555e-a083-4921-e5e5-08d7b0b10fe8 X-MS-TrafficTypeDiagnostic: CY4PR12MB1222:|CY4PR12MB1222: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2958; X-Forefront-PRVS: 031257FE13 X-Forefront-Antispam-Report: SFV:NSPM; SFS:(10009020)(4636009)(366004)(39860400002)(346002)(136003)(376002)(396003)(189003)(199004)(52116002)(66946007)(66556008)(66476007)(7696005)(26005)(5660300002)(103116003)(956004)(55016002)(4326008)(86362001)(2906002)(44832011)(186003)(16526019)(478600001)(316002)(81156014)(81166006)(8936002)(8676002); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR12MB1222; H:CY4PR12MB1574.namprd12.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: vJ44Y/Y1k6ETRHolTONzcOcz3MDlvzyEL9/IuBVZn0uK5+s8Z6YqjjEgFZZtlWY6Yyy/5I+tAvD7RtpJ3jAHsMZN7kteAS58aDRXPUj0qT3I2jo8s1wj/Imk1C//wWp6WE8aW09oLEjdkXjwmRnsnwyLb0qj8FCNkzUuqAHp07HUrwhuvOUPT30py5iyoErAdw/BgjM4I5XAheYYnOArh/AThnjxM8yZ08bzL2dSggQlejFS4P+0pkzb8cK0Nu1ZjAA/iiyr/meu8E6UPRklL3+XqjCbSeayMUvf3mbNdZY7yt/YencglIsXDttpInpPkUyn96NGupquUg6TXJFF6I8lEDDIiIts8ZweY57of8FB0v1omGo2zCXwcles2Stz5XXr2FXvlCkiiBAZQAHFhipUNT1WePj8XekztVfPbcXwOGwjPygg/yoVibxZYghG X-MS-Exchange-AntiSpam-MessageData: rDPsLegkW6VVKhnLo+VY43Zvx47DkSFblIpHznnKiu/2cRU8kOo2STbhHN8ogAvDn4Pp+zLxg8u7EB/PPjBoP7nPcmnAzpbAy/HAd5e4Op2Hx5dGPEbDGa6ekpmUy9e0yeRtbRlch+cZY+aBMHNkQw== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 662c555e-a083-4921-e5e5-08d7b0b10fe8 X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:18:02.0105 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: sapVXe9pWq77rVbWB2A54LHhjSBBeq9Edl0Lj7sAtXXbkN5pO+M6LlhMsWb7p26X X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1222 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.223.54 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) Apicid calculation depends on knowing the total number of numa nodes for EPYC cpu models. Right now, we are calculating the arch_id while parsing the numa(parse_numa). At this time, it is not known how many total numa nodes are configured in the system. Move the arch_id inside x86_cpus_init. At this time smp parameter is already completed and numa node information is available. Signed-off-by: Babu Moger --- hw/i386/x86.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index b825861b85..472dc3eb77 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -127,6 +127,9 @@ void x86_cpus_init(X86MachineState *x86ms, int default_= cpu_version) MachineState *ms =3D MACHINE(x86ms); MachineClass *mc =3D MACHINE_GET_CLASS(x86ms); =20 + /* Initialize apicid handlers first */ + x86_check_apicid_handlers(ms); + x86_cpu_set_default_version(default_cpu_version); =20 /* @@ -140,6 +143,11 @@ void x86_cpus_init(X86MachineState *x86ms, int default= _cpu_version) x86ms->apic_id_limit =3D x86_cpu_apic_id_from_index(x86ms, ms->smp.max_cpus - 1= ) + 1; possible_cpus =3D mc->possible_cpu_arch_ids(ms); + + for (i =3D 0; i < ms->smp.cpus; i++) { + ms->possible_cpus->cpus[i].arch_id =3D x86_cpu_apic_id_from_index(= x86ms, i); + } + for (i =3D 0; i < ms->smp.cpus; i++) { x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); } @@ -164,8 +172,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState = *ms, int idx) init_topo_info(&topo_info, x86ms); =20 assert(idx < ms->possible_cpus->len); - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - &topo_info, &topo_ids); + x86_topo_ids_from_idx(&topo_info, idx, &topo_ids); return topo_ids.pkg_id % ms->numa_state->num_nodes; } =20 @@ -199,10 +206,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(Machine= State *ms) =20 ms->possible_cpus->cpus[i].type =3D ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count =3D 1; - ms->possible_cpus->cpus[i].arch_id =3D - x86_cpu_apic_id_from_index(x86ms, i); - x86ms->topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - &topo_info, &topo_ids); + x86_topo_ids_from_idx(&topo_info, i, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo_ids.pkg_id; if (x86ms->smp_dies > 1) { From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Subject: [PATCH v4 15/16] i386: Fix pkg_id offset for EPYC cpu models From: Babu Moger To: ehabkost@redhat.com, marcel.apfelbaum@gmail.com, pbonzini@redhat.com, rth@twiddle.net, mst@redhat.com, imammedo@redhat.com Date: Thu, 13 Feb 2020 12:18:07 -0600 Message-ID: <158161788726.48948.3019001029706753681.stgit@naples-babu.amd.com> In-Reply-To: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> References: <158161767653.48948.10578064482878399556.stgit@naples-babu.amd.com> User-Agent: StGit/unknown-version Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: DM6PR17CA0019.namprd17.prod.outlook.com (2603:10b6:5:1b3::32) To CY4PR12MB1574.namprd12.prod.outlook.com (2603:10b6:910:e::23) MIME-Version: 1.0 X-Originating-IP: [165.204.78.2] X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-HT: Tenant X-MS-Office365-Filtering-Correlation-Id: be8cc7bd-c08e-48f8-eefb-08d7b0b113dd X-MS-TrafficTypeDiagnostic: CY4PR12MB1222:|CY4PR12MB1222: X-MS-Exchange-Transport-Forked: True X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2449; 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Fix it calling the model specific handler. Signed-off-by: Babu Moger --- hw/i386/pc.c | 1 + hw/i386/x86.c | 4 ++++ target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 1 + 4 files changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 93063af6a8..e56780b1f0 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1754,6 +1754,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, =20 env->nr_dies =3D x86ms->smp_dies; env->nr_nodes =3D ms->numa_state->num_nodes / ms->smp.sockets; + env->pkg_offset =3D x86ms->apicid_pkg_offset(&topo_info); =20 /* * If APIC ID is not set, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 472dc3eb77..99f2a67d69 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -106,12 +106,16 @@ void x86_cpu_new(X86MachineState *x86ms, int64_t apic= _id, Error **errp) Error *local_err =3D NULL; CPUX86State *env =3D NULL; MachineState *ms =3D MACHINE(x86ms); + X86CPUTopoInfo topo_info; + + init_topo_info(&topo_info, x86ms); =20 cpu =3D object_new(MACHINE(x86ms)->cpu_type); =20 env =3D &X86_CPU(cpu)->env; env->nr_dies =3D x86ms->smp_dies; env->nr_nodes =3D ms->numa_state->num_nodes / ms->smp.sockets; + env->pkg_offset =3D x86ms->apicid_pkg_offset(&topo_info); =20 object_property_set_uint(cpu, apic_id, "apic-id", &local_err); object_property_set_bool(cpu, true, "realized", &local_err); diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 082865d72b..b793da7c6e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5454,7 +5454,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_pkg_offset(&topo_info); + *eax =3D env->pkg_offset; *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -5488,7 +5488,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: - *eax =3D apicid_pkg_offset(&topo_info); + *eax =3D env->pkg_offset; *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; break; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 64a1cca690..641e1cacdf 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1604,6 +1604,7 @@ typedef struct CPUX86State { =20 unsigned nr_dies; unsigned nr_nodes; + unsigned pkg_offset; } CPUX86State; =20 struct kvm_msrs; From nobody Tue Apr 23 07:14:40 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=pass (i=1dmarc=pass fromdomain=amd.com) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581618874633712.1757308063021; Thu, 13 Feb 2020 10:34:34 -0800 (PST) Received: from localhost ([::1]:57852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2JJp-0007py-9L for importer@patchew.org; Thu, 13 Feb 2020 13:34:33 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:43554) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j2J4A-0003tw-Nh for qemu-devel@nongnu.org; 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FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: G4bZEH4uW9TifjN0qGJxZ0WTdB4jA9ndLj0sD2ubutdRI7v+nY6bOfzIrQ3speyK85MpiRY7R8tC2KFcs0yLzDPGechR579KMnGfCq/4L5Kk/V/xg4Ei1y0M2b3ZXlVEsmiB4IneCuL/1oQ9fMYW9yiAtL2/NOIyhVJpVybcTPb+Td7vFxZEETFxZwGPyjDmS5+nHqae3pxsEVpRQfI2gLE3in8Uea2euYTDtsMiBQsARpcX32Kt2e5heXGVDcFwKx0BvT8zESV0hTs9GN+nXlJ0ihDD6Pk+BhUiCGuFheFiuhUPcz/D9ZLx7MBeoGLe1WhdQp4Tl/oi9nN3V9MWUz8tRcmkXqdmMOT9FnjsJ7Qm8G67GQ+xF0Ap3gUUHOLdYL34DxxH0K0TShdz5SCPMI5xZskbdHW7LRf4hDy+iGsIdOojzJnnzKaquky/a2hz X-MS-Exchange-AntiSpam-MessageData: xAMnkc3zHoWg8j+R5s9fjyqvimAWyZmQUfKrkBxcoNEHSKn7GsalK9mfJpkKg/BRSzMhNxJV1hXZhD3GQqa2048mmSz0wmuhA4Yjb/K29VklrHxTAfGPQIO+C9tSVaERa4/gV4oK6dllBuHsJKlr6w== X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 86d994ab-6d59-41a8-9ee5-08d7b0b117ee X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Feb 2020 18:18:15.5857 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: +E+ta8rPzafVP9XwrQsvG6Z59ZhoRBQPgRTv1yI/3Yi/IxBU7VzOzKF+CFo0FyrB X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR12MB1222 X-detected-operating-system: by eggs.gnu.org: Windows 7 or 8 [fuzzy] X-Received-From: 40.107.223.67 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @amdcloud.onmicrosoft.com) Since the topology routines have changed, update the unit tests to use the new APIs. Signed-off-by: Babu Moger --- tests/test-x86-cpuid.c | 115 ++++++++++++++++++++++++++++----------------= ---- 1 file changed, 68 insertions(+), 47 deletions(-) diff --git a/tests/test-x86-cpuid.c b/tests/test-x86-cpuid.c index 1942287f33..00553c1d77 100644 --- a/tests/test-x86-cpuid.c +++ b/tests/test-x86-cpuid.c @@ -28,79 +28,100 @@ =20 static void test_topo_bits(void) { + X86CPUTopoInfo topo_info =3D {0}; + /* simple tests for 1 thread per core, 1 core per die, 1 die per packa= ge */ - g_assert_cmpuint(apicid_smt_width(1, 1, 1), =3D=3D, 0); - g_assert_cmpuint(apicid_core_width(1, 1, 1), =3D=3D, 0); - g_assert_cmpuint(apicid_die_width(1, 1, 1), =3D=3D, 0); + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 1}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 0); + g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 0); + g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 0), =3D=3D, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 1), =3D=3D, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 2), =3D=3D, 2); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 1, 1, 3), =3D=3D, 3); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 3), =3D=3D, 3); =20 =20 /* Test field width calculation for multiple values */ - g_assert_cmpuint(apicid_smt_width(1, 1, 2), =3D=3D, 1); - g_assert_cmpuint(apicid_smt_width(1, 1, 3), =3D=3D, 2); - g_assert_cmpuint(apicid_smt_width(1, 1, 4), =3D=3D, 2); - - g_assert_cmpuint(apicid_smt_width(1, 1, 14), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 1, 15), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 1, 16), =3D=3D, 4); - g_assert_cmpuint(apicid_smt_width(1, 1, 17), =3D=3D, 5); - - - g_assert_cmpuint(apicid_core_width(1, 30, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(1, 31, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(1, 32, 2), =3D=3D, 5); - g_assert_cmpuint(apicid_core_width(1, 33, 2), =3D=3D, 6); - - g_assert_cmpuint(apicid_die_width(1, 30, 2), =3D=3D, 0); - g_assert_cmpuint(apicid_die_width(2, 30, 2), =3D=3D, 1); - g_assert_cmpuint(apicid_die_width(3, 30, 2), =3D=3D, 2); - g_assert_cmpuint(apicid_die_width(4, 30, 2), =3D=3D, 2); + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 2}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 1); + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 3}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 4}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); + + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 14}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 15}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 16}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 4); + topo_info =3D (X86CPUTopoInfo) {0, 1, 1, 17}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 5); + + + topo_info =3D (X86CPUTopoInfo) {0, 1, 30, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); + topo_info =3D (X86CPUTopoInfo) {0, 1, 31, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); + topo_info =3D (X86CPUTopoInfo) {0, 1, 32, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 5); + topo_info =3D (X86CPUTopoInfo) {0, 1, 33, 2}; + g_assert_cmpuint(apicid_core_width(&topo_info), =3D=3D, 6); + + topo_info =3D (X86CPUTopoInfo) {0, 1, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 0); + topo_info =3D (X86CPUTopoInfo) {0, 2, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 1); + topo_info =3D (X86CPUTopoInfo) {0, 3, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); + topo_info =3D (X86CPUTopoInfo) {0, 4, 30, 2}; + g_assert_cmpuint(apicid_die_width(&topo_info), =3D=3D, 2); =20 /* build a weird topology and see if IDs are calculated correctly */ =20 /* This will use 2 bits for thread ID and 3 bits for core ID */ - g_assert_cmpuint(apicid_smt_width(1, 6, 3), =3D=3D, 2); - g_assert_cmpuint(apicid_core_offset(1, 6, 3), =3D=3D, 2); - g_assert_cmpuint(apicid_die_offset(1, 6, 3), =3D=3D, 5); - g_assert_cmpuint(apicid_pkg_offset(1, 6, 3), =3D=3D, 5); - - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 0), =3D=3D, 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1), =3D=3D, 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2), =3D=3D, 2); - - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 0), =3D=3D, + topo_info =3D (X86CPUTopoInfo) {0, 1, 6, 3}; + g_assert_cmpuint(apicid_smt_width(&topo_info), =3D=3D, 2); + g_assert_cmpuint(apicid_core_offset(&topo_info), =3D=3D, 2); + g_assert_cmpuint(apicid_die_offset(&topo_info), =3D=3D, 5); + g_assert_cmpuint(apicid_pkg_offset(&topo_info), =3D=3D, 5); + + topo_info =3D (X86CPUTopoInfo) {0, 1, 6, 3}; + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 0), =3D=3D, 0); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1), =3D=3D, 1); + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2), =3D=3D, 2); + + topo_info =3D (X86CPUTopoInfo) {0, 1, 6, 3}; + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 0), =3D= =3D, (1 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 1), =3D= =3D, (1 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 1 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 3 + 2), =3D= =3D, (1 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 0), =3D= =3D, (2 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 1), =3D= =3D, (2 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 2 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 2 * 3 + 2), =3D= =3D, (2 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 0), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 0), =3D= =3D, (5 << 2) | 0); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 1), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 1), =3D= =3D, (5 << 2) | 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, 5 * 3 + 2), =3D=3D, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 5 * 3 + 2), =3D= =3D, (5 << 2) | 2); =20 - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 6 * 3 + 0 * 3 + 0), =3D=3D, (1 << 5)); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 1 * 6 * 3 + 1 * 3 + 1), =3D=3D, (1 << 5) | (1 << 2) |= 1); - g_assert_cmpuint(x86_apicid_from_cpu_idx(1, 6, 3, + g_assert_cmpuint(x86_apicid_from_cpu_idx(&topo_info, 3 * 6 * 3 + 5 * 3 + 2), =3D=3D, (3 << 5) | (5 << 2) |= 2); } =20