From nobody Mon Feb 9 16:53:58 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1581384160227874.1136340449817; Mon, 10 Feb 2020 17:22:40 -0800 (PST) Received: from localhost ([::1]:42114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1KG6-0004uv-Jg for importer@patchew.org; Mon, 10 Feb 2020 20:22:38 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34969) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1j1JdB-00037Y-O6 for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:42:27 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1j1Jd9-0004pM-8Z for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:42:25 -0500 Received: from alexa-out-sd-02.qualcomm.com ([199.106.114.39]:59208) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1j1Jd8-0004uP-OY for qemu-devel@nongnu.org; Mon, 10 Feb 2020 19:42:23 -0500 Received: from unknown (HELO ironmsg02-sd.qualcomm.com) ([10.53.140.142]) by alexa-out-sd-02.qualcomm.com with ESMTP; 10 Feb 2020 16:41:04 -0800 Received: from vu-tsimpson-aus.qualcomm.com (HELO vu-tsimpson1-aus.qualcomm.com) ([10.222.150.1]) by ironmsg02-sd.qualcomm.com with ESMTP; 10 Feb 2020 16:41:03 -0800 Received: by vu-tsimpson1-aus.qualcomm.com (Postfix, from userid 47164) id 829AB1B53; Mon, 10 Feb 2020 18:41:03 -0600 (CST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1581381742; x=1612917742; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=x0XSBMjxTb1gtluq1c5B274z2BS3s/lKrvi/e+6IlPk=; b=fF771ICl85WlZlF/+7NLRn8fMl8VnxLs+cMcSP1666E9NB5BQxSp7oOU 9RcXHkQrVroc1MWZ8+dfWvJrU8B4RbHyPwiUOzoUqo1AlEfeJwdZM8vtb hU8paVqeK/Vgtm7DfF+xMzJohcesDr8PHDgkzftimWjkQo0YNonlbHKGM g=; From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [RFC PATCH 61/66] Hexagon HVX macros to interface with the generator Date: Mon, 10 Feb 2020 18:40:39 -0600 Message-Id: <1581381644-13678-62-git-send-email-tsimpson@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> References: <1581381644-13678-1-git-send-email-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 199.106.114.39 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: riku.voipio@iki.fi, richard.henderson@linaro.org, laurent@vivier.eu, Taylor Simpson , philmd@redhat.com, aleksandar.m.mail@gmail.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Various forms of declare, read, write, free for HVX operands Signed-off-by: Taylor Simpson --- target/hexagon/mmvec/macros.h | 232 ++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 232 insertions(+) create mode 100644 target/hexagon/mmvec/macros.h diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h new file mode 100644 index 0000000..80adb83 --- /dev/null +++ b/target/hexagon/mmvec/macros.h @@ -0,0 +1,232 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserve= d. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#ifndef MMVEC_MACROS_H +#define MMVEC_MACROS_H + +#include "mmvec/system_ext_mmvec.h" + +#ifdef QEMU_GENERATE +#else +#define VdV (*(mmvector_t *)(VdV_void)) +#define VsV (*(mmvector_t *)(VsV_void)) +#define VuV (*(mmvector_t *)(VuV_void)) +#define VvV (*(mmvector_t *)(VvV_void)) +#define VwV (*(mmvector_t *)(VwV_void)) +#define VxV (*(mmvector_t *)(VxV_void)) +#define VyV (*(mmvector_t *)(VyV_void)) + +#define VddV (*(mmvector_pair_t *)(VddV_void)) +#define VuuV (*(mmvector_pair_t *)(VuuV_void)) +#define VvvV (*(mmvector_pair_t *)(VvvV_void)) +#define VxxV (*(mmvector_pair_t *)(VxxV_void)) + +#define QeV (*(mmqreg_t *)(QeV_void)) +#define QdV (*(mmqreg_t *)(QdV_void)) +#define QsV (*(mmqreg_t *)(QsV_void)) +#define QtV (*(mmqreg_t *)(QtV_void)) +#define QuV (*(mmqreg_t *)(QuV_void)) +#define QvV (*(mmqreg_t *)(QvV_void)) +#define QxV (*(mmqreg_t *)(QxV_void)) +#endif + +#ifdef QEMU_GENERATE +#define DECL_VREG(VAR, NUM, X, OFF) \ + TCGv_ptr VAR =3D tcg_temp_local_new_ptr(); \ + size1u_t NUM =3D REGNO(X) + OFF; \ + do { \ + uint32_t __offset =3D new_temp_vreg_offset(ctx, 1); \ + tcg_gen_addi_ptr(VAR, cpu_env, __offset); \ + } while (0) + +#define DECL_VREG_d(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_s(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_t(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_u(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_v(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_w(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_x(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) +#define DECL_VREG_y(VAR, NUM, X, OFF) \ + DECL_VREG(VAR, NUM, X, OFF) + +#define DECL_VREG_PAIR(VAR, NUM, X, OFF) \ + TCGv_ptr VAR =3D tcg_temp_local_new_ptr(); \ + size1u_t NUM =3D REGNO(X) + OFF; \ + do { \ + uint32_t __offset =3D new_temp_vreg_offset(ctx, 2); \ + tcg_gen_addi_ptr(VAR, cpu_env, __offset); \ + } while (0) + +#define DECL_VREG_dd(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) +#define DECL_VREG_uu(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) +#define DECL_VREG_vv(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) +#define DECL_VREG_xx(VAR, NUM, X, OFF) \ + DECL_VREG_PAIR(VAR, NUM, X, OFF) + +#define DECL_QREG(VAR, NUM, X, OFF) \ + TCGv_ptr VAR =3D tcg_temp_local_new_ptr(); \ + size1u_t NUM =3D REGNO(X) + OFF; \ + do { \ + uint32_t __offset =3D new_temp_qreg_offset(ctx); \ + tcg_gen_addi_ptr(VAR, cpu_env, __offset); \ + } while (0) + +#define DECL_QREG_d(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_e(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_s(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_t(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_u(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_v(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) +#define DECL_QREG_x(VAR, NUM, X, OFF) \ + DECL_QREG(VAR, NUM, X, OFF) + +#define FREE_VREG(VAR) tcg_temp_free_ptr(VAR) +#define FREE_VREG_d(VAR) FREE_VREG(VAR) +#define FREE_VREG_s(VAR) FREE_VREG(VAR) +#define FREE_VREG_u(VAR) FREE_VREG(VAR) +#define FREE_VREG_v(VAR) FREE_VREG(VAR) +#define FREE_VREG_w(VAR) FREE_VREG(VAR) +#define FREE_VREG_x(VAR) FREE_VREG(VAR) +#define FREE_VREG_y(VAR) FREE_VREG(VAR) + +#define FREE_VREG_PAIR(VAR) tcg_temp_free_ptr(VAR) +#define FREE_VREG_dd(VAR) FREE_VREG_PAIR(VAR) +#define FREE_VREG_uu(VAR) FREE_VREG_PAIR(VAR) +#define FREE_VREG_vv(VAR) FREE_VREG_PAIR(VAR) +#define FREE_VREG_xx(VAR) FREE_VREG_PAIR(VAR) + +#define FREE_QREG(VAR) tcg_temp_free_ptr(VAR) +#define FREE_QREG_d(VAR) FREE_QREG(VAR) +#define FREE_QREG_e(VAR) FREE_QREG(VAR) +#define FREE_QREG_s(VAR) FREE_QREG(VAR) +#define FREE_QREG_t(VAR) FREE_QREG(VAR) +#define FREE_QREG_u(VAR) FREE_QREG(VAR) +#define FREE_QREG_v(VAR) FREE_QREG(VAR) +#define FREE_QREG_x(VAR) FREE_QREG(VAR) + +#define READ_VREG(VAR, NUM) \ + gen_read_vreg(VAR, NUM, 0) +#define READ_VREG_s(VAR, NUM) READ_VREG(VAR, NUM) +#define READ_VREG_u(VAR, NUM) READ_VREG(VAR, NUM) +#define READ_VREG_v(VAR, NUM) READ_VREG(VAR, NUM) +#define READ_VREG_w(VAR, NUM) READ_VREG(VAR, NUM) +#define READ_VREG_x(VAR, NUM) READ_VREG(VAR, NUM) +#define READ_VREG_y(VAR, NUM) READ_VREG(VAR, NUM) + +#define READ_VREG_PAIR(VAR, NUM) \ + gen_read_vreg_pair(VAR, NUM, 0) +#define READ_VREG_uu(VAR, NUM) READ_VREG_PAIR(VAR, NUM) +#define READ_VREG_vv(VAR, NUM) READ_VREG_PAIR(VAR, NUM) +#define READ_VREG_xx(VAR, NUM) READ_VREG_PAIR(VAR, NUM) + +#define READ_QREG(VAR, NUM) \ + gen_read_qreg(VAR, NUM, 0) +#define READ_QREG_s(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_t(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_u(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_v(VAR, NUM) READ_QREG(VAR, NUM) +#define READ_QREG_x(VAR, NUM) READ_QREG(VAR, NUM) + +#define DECL_NEW_OREG(TYPE, NAME, NUM, X, OFF) \ + TYPE NAME; \ + int NUM =3D REGNO(X) + OFF + +#define READ_NEW_OREG(tmp, i) (tmp =3D tcg_const_tl(i)) + +#define FREE_NEW_OREG(NAME) \ + tcg_temp_free(NAME) + +#define LOG_VREG_WRITE(NUM, VAR, VNEW) \ + do { \ + int is_predicated =3D GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_vreg_write(VAR, NUM, VNEW, insn->slot); \ + ctx_log_vreg_write(ctx, (NUM), is_predicated); \ + } while (0) + +#define LOG_VREG_WRITE_PAIR(NUM, VAR, VNEW) \ + do { \ + int is_predicated =3D GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_vreg_write_pair(VAR, NUM, VNEW, insn->slot); \ + ctx_log_vreg_write(ctx, (NUM) ^ 0, is_predicated); \ + ctx_log_vreg_write(ctx, (NUM) ^ 1, is_predicated); \ + } while (0) + +#define LOG_QREG_WRITE(NUM, VAR, VNEW) \ + do { \ + int is_predicated =3D GET_ATTRIB(insn->opcode, A_CONDEXEC); \ + gen_log_qreg_write(VAR, NUM, VNEW, insn->slot); \ + ctx_log_qreg_write(ctx, (NUM), is_predicated); \ + } while (0) +#else +#define NEW_WRITTEN(NUM) ((env->VRegs_select >> (NUM)) & 1) +#define TMP_WRITTEN(NUM) ((env->VRegs_updated_tmp >> (NUM)) & 1) + +#define LOG_VREG_WRITE_FUNC(X) \ + _Generic((X), void * : log_vreg_write, mmvector_t : log_mmvector_write) +#define LOG_VREG_WRITE(NUM, VAR, VNEW) \ + LOG_VREG_WRITE_FUNC(VAR)(env, NUM, VAR, VNEW, slot) + +#define READ_EXT_VREG(NUM, VAR, VTMP) \ + do { \ + VAR =3D ((NEW_WRITTEN(NUM)) ? env->future_VRegs[NUM] \ + : env->VRegs[NUM]); \ + VAR =3D ((TMP_WRITTEN(NUM)) ? env->tmp_VRegs[NUM] : VAR); \ + if (VTMP =3D=3D EXT_TMP) { \ + if (env->VRegs_updated & ((VRegMask)1) << (NUM)) { \ + VAR =3D env->future_VRegs[NUM]; \ + env->VRegs_updated ^=3D ((VRegMask)1) << (NUM); \ + } \ + } \ + } while (0) + +#define READ_EXT_VREG_PAIR(NUM, VAR, VTMP) \ + do { \ + READ_EXT_VREG((NUM) ^ 0, VAR.v[0], VTMP); \ + READ_EXT_VREG((NUM) ^ 1, VAR.v[1], VTMP) \ + } while (0) +#endif + +#define WRITE_EXT_VREG(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) +#define WRITE_VREG_d(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) +#define WRITE_VREG_x(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) +#define WRITE_VREG_y(NUM, VAR, VNEW) LOG_VREG_WRITE(NUM, VAR, VNEW) + +#define WRITE_VREG_dd(NUM, VAR, VNEW) LOG_VREG_WRITE_PAIR(NUM, VAR, VNE= W) +#define WRITE_VREG_xx(NUM, VAR, VNEW) LOG_VREG_WRITE_PAIR(NUM, VAR, VNE= W) +#define WRITE_VREG_yy(NUM, VAR, VNEW) LOG_VREG_WRITE_PAIR(NUM, VAR, VNE= W) + +#define WRITE_QREG_d(NUM, VAR, VNEW) LOG_QREG_WRITE(NUM, VAR, VNEW) +#define WRITE_QREG_e(NUM, VAR, VNEW) LOG_QREG_WRITE(NUM, VAR, VNEW) +#define WRITE_QREG_x(NUM, VAR, VNEW) LOG_QREG_WRITE(NUM, VAR, VNEW) + +#endif --=20 2.7.4