From nobody Fri May 17 10:44:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580803415963670.6410662322279; Tue, 4 Feb 2020 00:03:35 -0800 (PST) Received: from localhost ([::1]:54204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iytBG-0003u1-Kp for importer@patchew.org; Tue, 04 Feb 2020 03:03:34 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38755) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iytA8-0002fJ-8k for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:25 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iytA4-000171-8G for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:24 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42498 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iytA3-00012U-Tq for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:20 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 8EC141A1D19; Tue, 4 Feb 2020 09:02:17 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 6DCF21A0F0A; Tue, 4 Feb 2020 09:02:17 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL v2 1/3] target/mips: Fix handling of LL/SC instructions after 7dd547e5ab Date: Tue, 4 Feb 2020 09:01:55 +0100 Message-Id: <1580803317-4422-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580803317-4422-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1580803317-4422-1-git-send-email-aleksandar.markovic@rt-rk.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com, Richard Henderson , Alex Richardson , Aleksandar Rikalo , James Clarke , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Alex Richardson After 7dd547e5ab6b31e7a0cfc182d3ad131dd55a948f the env->llval value is loaded as an unsigned value (instead of sign-extended as before). Therefore, the CMPXCHG in gen_st_cond() in translate.c fails if the sign bit is set in the loaded value. Fix this by sign-extending the llval value for the 32-bit case. I discovered this issue because FreeBSD MIPS64 was looping forever in an atomic helper function when trying to start /sbin/init. Signed-off-by: Alex Richardson Fixes: 7dd547e5ab ("target/mips: Use cpu_*_mmuidx_ra instead of MMU_MODE*_S= UFFIX") Buglink: https://bugs.launchpad.net/qemu/+bug/1861605 Cc: Aurelien Jarno Cc: Aleksandar Markovic Cc: Aleksandar Rikalo Cc: Richard Henderson Signed-off-by: James Clarke Signed-off-by: Aleksandar Markovic Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20200202153409.28534-1-jrtc27@jrtc27.com> --- target/mips/op_helper.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 15d05a5..467914d 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -305,7 +305,7 @@ static inline hwaddr do_translate_address(CPUMIPSState = *env, } } =20 -#define HELPER_LD_ATOMIC(name, insn, almask) = \ +#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) = \ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_id= x) \ { = \ if (arg & almask) { = \ @@ -316,12 +316,12 @@ target_ulong helper_##name(CPUMIPSState *env, target_= ulong arg, int mem_idx) \ } = \ env->CP0_LLAddr =3D do_translate_address(env, arg, 0, GETPC()); = \ env->lladdr =3D arg; = \ - env->llval =3D cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); = \ + env->llval =3D do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC= ()); \ return env->llval; = \ } -HELPER_LD_ATOMIC(ll, ldl, 0x3) +HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) #ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ldq, 0x7) +HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) #endif #undef HELPER_LD_ATOMIC #endif --=20 2.7.4 From nobody Fri May 17 10:44:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158080345021827.813129326825447; Tue, 4 Feb 2020 00:04:10 -0800 (PST) Received: from localhost ([::1]:54206 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iytBo-0004dX-Gw for importer@patchew.org; Tue, 04 Feb 2020 03:04:08 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38962) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iytAH-0002qf-SW for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:43 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iytA8-0001By-7H for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:33 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42550 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iytA4-00013s-62 for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:20 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id D948E1A1D3B; Tue, 4 Feb 2020 09:02:17 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 7DFB51A152E; Tue, 4 Feb 2020 09:02:17 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL v2 2/3] target/mips: Separate CP0-related helpers into their own file Date: Tue, 4 Feb 2020 09:01:56 +0100 Message-Id: <1580803317-4422-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580803317-4422-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1580803317-4422-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic For clarity and easier maintenence, create target/mips/cp0_helper.c, and move all CP0-related content form target/mips/op_helper.c to that file. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1580745443-24650-2-git-send-email-aleksandar.markovic@rt-rk.co= m> --- target/mips/Makefile.objs | 5 +- target/mips/cp0_helper.c | 1678 +++++++++++++++++++++++++++++++++++++++++= +++ target/mips/op_helper.c | 1705 +----------------------------------------= ---- 3 files changed, 1713 insertions(+), 1675 deletions(-) create mode 100644 target/mips/cp0_helper.c diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs index 3448ad5..3ca2bde 100644 --- a/target/mips/Makefile.objs +++ b/target/mips/Makefile.objs @@ -1,5 +1,6 @@ -obj-y +=3D translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o -obj-y +=3D gdbstub.o msa_helper.o +obj-y +=3D translate.o cpu.o gdbstub.o helper.o +obj-y +=3D op_helper.o cp0_helper.o +obj-y +=3D dsp_helper.o lmi_helper.o msa_helper.o obj-$(CONFIG_SOFTMMU) +=3D mips-semi.o obj-$(CONFIG_SOFTMMU) +=3D machine.o cp0_timer.o obj-$(CONFIG_KVM) +=3D kvm.o diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c new file mode 100644 index 0000000..bbf12e4 --- /dev/null +++ b/target/mips/cp0_helper.c @@ -0,0 +1,1678 @@ +/* + * Helpers for emulation of CP0-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * Copyright (C) 2020 Wave Computing, Inc. + * Copyright (C) 2020 Aleksandar Markovic + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "internal.h" +#include "qemu/host-utils.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/memop.h" +#include "sysemu/kvm.h" + + +#ifndef CONFIG_USER_ONLY +/* SMP helpers. */ +static bool mips_vpe_is_wfi(MIPSCPU *c) +{ + CPUState *cpu =3D CPU(c); + CPUMIPSState *env =3D &c->env; + + /* + * If the VPE is halted but otherwise active, it means it's waiting for + * an interrupt.\ + */ + return cpu->halted && mips_vpe_active(env); +} + +static bool mips_vp_is_wfi(MIPSCPU *c) +{ + CPUState *cpu =3D CPU(c); + CPUMIPSState *env =3D &c->env; + + return cpu->halted && mips_vp_active(env); +} + +static inline void mips_vpe_wake(MIPSCPU *c) +{ + /* + * Don't set ->halted =3D 0 directly, let it be done via cpu_has_work + * because there might be other conditions that state that c should + * be sleeping. + */ + qemu_mutex_lock_iothread(); + cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); + qemu_mutex_unlock_iothread(); +} + +static inline void mips_vpe_sleep(MIPSCPU *cpu) +{ + CPUState *cs =3D CPU(cpu); + + /* + * The VPE was shut off, really go to bed. + * Reset any old _WAKE requests. + */ + cs->halted =3D 1; + cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); +} + +static inline void mips_tc_wake(MIPSCPU *cpu, int tc) +{ + CPUMIPSState *c =3D &cpu->env; + + /* FIXME: TC reschedule. */ + if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) { + mips_vpe_wake(cpu); + } +} + +static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) +{ + CPUMIPSState *c =3D &cpu->env; + + /* FIXME: TC reschedule. */ + if (!mips_vpe_active(c)) { + mips_vpe_sleep(cpu); + } +} + +/** + * mips_cpu_map_tc: + * @env: CPU from which mapping is performed. + * @tc: Should point to an int with the value of the global TC index. + * + * This function will transform @tc into a local index within the + * returned #CPUMIPSState. + */ + +/* + * FIXME: This code assumes that all VPEs have the same number of TCs, + * which depends on runtime setup. Can probably be fixed by + * walking the list of CPUMIPSStates. + */ +static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) +{ + MIPSCPU *cpu; + CPUState *cs; + CPUState *other_cs; + int vpe_idx; + int tc_idx =3D *tc; + + if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { + /* Not allowed to address other CPUs. */ + *tc =3D env->current_tc; + return env; + } + + cs =3D env_cpu(env); + vpe_idx =3D tc_idx / cs->nr_threads; + *tc =3D tc_idx % cs->nr_threads; + other_cs =3D qemu_get_cpu(vpe_idx); + if (other_cs =3D=3D NULL) { + return env; + } + cpu =3D MIPS_CPU(other_cs); + return &cpu->env; +} + +/* + * The per VPE CP0_Status register shares some fields with the per TC + * CP0_TCStatus registers. These fields are wired to the same registers, + * so changes to either of them should be reflected on both registers. + * + * Also, EntryHi shares the bottom 8 bit ASID with TCStauts. + * + * These helper call synchronizes the regs for a given cpu. + */ + +/* + * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. + * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, + * int tc); + */ + +/* Called for updates to CP0_TCStatus. */ +static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, + target_ulong v) +{ + uint32_t status; + uint32_t tcu, tmx, tasid, tksu; + uint32_t mask =3D ((1U << CP0St_CU3) + | (1 << CP0St_CU2) + | (1 << CP0St_CU1) + | (1 << CP0St_CU0) + | (1 << CP0St_MX) + | (3 << CP0St_KSU)); + + tcu =3D (v >> CP0TCSt_TCU0) & 0xf; + tmx =3D (v >> CP0TCSt_TMX) & 0x1; + tasid =3D v & cpu->CP0_EntryHi_ASID_mask; + tksu =3D (v >> CP0TCSt_TKSU) & 0x3; + + status =3D tcu << CP0St_CU0; + status |=3D tmx << CP0St_MX; + status |=3D tksu << CP0St_KSU; + + cpu->CP0_Status &=3D ~mask; + cpu->CP0_Status |=3D status; + + /* Sync the TASID with EntryHi. */ + cpu->CP0_EntryHi &=3D ~cpu->CP0_EntryHi_ASID_mask; + cpu->CP0_EntryHi |=3D tasid; + + compute_hflags(cpu); +} + +/* Called for updates to CP0_EntryHi. */ +static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) +{ + int32_t *tcst; + uint32_t asid, v =3D cpu->CP0_EntryHi; + + asid =3D v & cpu->CP0_EntryHi_ASID_mask; + + if (tc =3D=3D cpu->current_tc) { + tcst =3D &cpu->active_tc.CP0_TCStatus; + } else { + tcst =3D &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &=3D ~cpu->CP0_EntryHi_ASID_mask; + *tcst |=3D asid; +} + +/* CP0 helpers */ +target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) +{ + return env->mvp->CP0_MVPControl; +} + +target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) +{ + return env->mvp->CP0_MVPConf0; +} + +target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) +{ + return env->mvp->CP0_MVPConf1; +} + +target_ulong helper_mfc0_random(CPUMIPSState *env) +{ + return (int32_t)cpu_mips_get_random(env); +} + +target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCStatus; +} + +target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.CP0_TCStatus; + } else { + return other->tcs[other_tc].CP0_TCStatus; + } +} + +target_ulong helper_mfc0_tcbind(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCBind; +} + +target_ulong helper_mftc0_tcbind(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.CP0_TCBind; + } else { + return other->tcs[other_tc].CP0_TCBind; + } +} + +target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) +{ + return env->active_tc.PC; +} + +target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.PC; + } else { + return other->tcs[other_tc].PC; + } +} + +target_ulong helper_mfc0_tchalt(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCHalt; +} + +target_ulong helper_mftc0_tchalt(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.CP0_TCHalt; + } else { + return other->tcs[other_tc].CP0_TCHalt; + } +} + +target_ulong helper_mfc0_tccontext(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCContext; +} + +target_ulong helper_mftc0_tccontext(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.CP0_TCContext; + } else { + return other->tcs[other_tc].CP0_TCContext; + } +} + +target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCSchedule; +} + +target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.CP0_TCSchedule; + } else { + return other->tcs[other_tc].CP0_TCSchedule; + } +} + +target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCScheFBack; +} + +target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.CP0_TCScheFBack; + } else { + return other->tcs[other_tc].CP0_TCScheFBack; + } +} + +target_ulong helper_mfc0_count(CPUMIPSState *env) +{ + return (int32_t)cpu_mips_get_count(env); +} + +target_ulong helper_mfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} + +target_ulong helper_mfhc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; + } + return 0; +} + +target_ulong helper_mftc0_entryhi(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + return other->CP0_EntryHi; +} + +target_ulong helper_mftc0_cause(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tccause; + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + tccause =3D other->CP0_Cause; + } else { + tccause =3D other->CP0_Cause; + } + + return tccause; +} + +target_ulong helper_mftc0_status(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + return other->CP0_Status; +} + +target_ulong helper_mfc0_lladdr(CPUMIPSState *env) +{ + return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift); +} + +target_ulong helper_mfc0_maar(CPUMIPSState *env) +{ + return (int32_t) env->CP0_MAAR[env->CP0_MAARI]; +} + +target_ulong helper_mfhc0_maar(CPUMIPSState *env) +{ + return env->CP0_MAAR[env->CP0_MAARI] >> 32; +} + +target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) +{ + return (int32_t)env->CP0_WatchLo[sel]; +} + +target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return (int32_t) env->CP0_WatchHi[sel]; +} + +target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel] >> 32; +} + +target_ulong helper_mfc0_debug(CPUMIPSState *env) +{ + target_ulong t0 =3D env->CP0_Debug; + if (env->hflags & MIPS_HFLAG_DM) { + t0 |=3D 1 << CP0DB_DM; + } + + return t0; +} + +target_ulong helper_mftc0_debug(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + int32_t tcstatus; + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + tcstatus =3D other->active_tc.CP0_Debug_tcstatus; + } else { + tcstatus =3D other->tcs[other_tc].CP0_Debug_tcstatus; + } + + /* XXX: Might be wrong, check with EJTAG spec. */ + return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) +{ + return env->active_tc.PC; +} + +target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCHalt; +} + +target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCContext; +} + +target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCSchedule; +} + +target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) +{ + return env->active_tc.CP0_TCScheFBack; +} + +target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) +{ + return env->CP0_LLAddr >> env->CP0_LLAddr_shift; +} + +target_ulong helper_dmfc0_maar(CPUMIPSState *env) +{ + return env->CP0_MAAR[env->CP0_MAARI]; +} + +target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchLo[sel]; +} + +target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) +{ + return env->CP0_WatchHi[sel]; +} + +target_ulong helper_dmfc0_saar(CPUMIPSState *env) +{ + if ((env->CP0_SAARI & 0x3f) < 2) { + return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + } + return 0; +} +#endif /* TARGET_MIPS64 */ + +void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t index_p =3D env->CP0_Index & 0x80000000; + uint32_t tlb_index =3D arg1 & 0x7fffffff; + if (tlb_index < env->tlb->nb_tlb) { + if (env->insn_flags & ISA_MIPS32R6) { + index_p |=3D arg1 & 0x80000000; + } + env->CP0_Index =3D index_p | tlb_index; + } +} + +void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask =3D 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + mask |=3D (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | + (1 << CP0MVPCo_EVP); + } + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { + mask |=3D (1 << CP0MVPCo_STLB); + } + newval =3D (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); + + /* TODO: Enable/disable shared TLB, enable/disable VPEs. */ + + env->mvp->CP0_MVPControl =3D newval; +} + +void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask; + uint32_t newval; + + mask =3D (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | + (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); + newval =3D (env->CP0_VPEControl & ~mask) | (arg1 & mask); + + /* + * Yield scheduler intercept not implemented. + * Gating storage scheduler intercept not implemented. + */ + + /* TODO: Enable/disable TCs. */ + + env->CP0_VPEControl =3D newval; +} + +void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + uint32_t mask; + uint32_t newval; + + mask =3D (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | + (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); + newval =3D (other->CP0_VPEControl & ~mask) | (arg1 & mask); + + /* TODO: Enable/disable TCs. */ + + other->CP0_VPEControl =3D newval; +} + +target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + /* FIXME: Mask away return zero on read bits. */ + return other->CP0_VPEControl; +} + +target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + return other->CP0_VPEConf0; +} + +void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask =3D 0; + uint32_t newval; + + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { + if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { + mask |=3D (0xff << CP0VPEC0_XTC); + } + mask |=3D (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + } + newval =3D (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); + + /* TODO: TC exclusive handling due to ERL/EXL. */ + + env->CP0_VPEConf0 =3D newval; +} + +void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + uint32_t mask =3D 0; + uint32_t newval; + + mask |=3D (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); + newval =3D (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); + + /* TODO: TC exclusive handling due to ERL/EXL. */ + other->CP0_VPEConf0 =3D newval; +} + +void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask =3D 0; + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) + mask |=3D (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | + (0xff << CP0VPEC1_NCP1); + newval =3D (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); + + /* UDI not implemented. */ + /* CP2 not implemented. */ + + /* TODO: Handle FPU (CP1) binding. */ + + env->CP0_VPEConf1 =3D newval; +} + +void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) +{ + /* Yield qualifier inputs not implemented. */ + env->CP0_YQMask =3D 0x00000000; +} + +void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_VPEOpt =3D arg1 & 0x0000ffff; +} + +#define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF) + +void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) +{ + /* 1k pages not implemented */ + target_ulong rxi =3D arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); + env->CP0_EntryLo0 =3D (arg1 & MTC0_ENTRYLO_MASK(env)) + | (rxi << (CP0EnLo_XI - 30)); +} + +#if defined(TARGET_MIPS64) +#define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6) + +void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1) +{ + uint64_t rxi =3D arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) <<= 32); + env->CP0_EntryLo0 =3D (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; +} +#endif + +void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask =3D env->CP0_TCStatus_rw_bitmask; + uint32_t newval; + + newval =3D (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); + + env->active_tc.CP0_TCStatus =3D newval; + sync_c0_tcstatus(env, env->current_tc, newval); +} + +void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.CP0_TCStatus =3D arg1; + } else { + other->tcs[other_tc].CP0_TCStatus =3D arg1; + } + sync_c0_tcstatus(other, other_tc, arg1); +} + +void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask =3D (1 << CP0TCBd_TBE); + uint32_t newval; + + if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { + mask |=3D (1 << CP0TCBd_CurVPE); + } + newval =3D (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); + env->active_tc.CP0_TCBind =3D newval; +} + +void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask =3D (1 << CP0TCBd_TBE); + uint32_t newval; + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { + mask |=3D (1 << CP0TCBd_CurVPE); + } + if (other_tc =3D=3D other->current_tc) { + newval =3D (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); + other->active_tc.CP0_TCBind =3D newval; + } else { + newval =3D (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mas= k); + other->tcs[other_tc].CP0_TCBind =3D newval; + } +} + +void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) +{ + env->active_tc.PC =3D arg1; + env->active_tc.CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); + env->CP0_LLAddr =3D 0; + env->lladdr =3D 0; + /* MIPS16 not implemented. */ +} + +void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.PC =3D arg1; + other->active_tc.CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); + other->CP0_LLAddr =3D 0; + other->lladdr =3D 0; + /* MIPS16 not implemented. */ + } else { + other->tcs[other_tc].PC =3D arg1; + other->tcs[other_tc].CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); + other->CP0_LLAddr =3D 0; + other->lladdr =3D 0; + /* MIPS16 not implemented. */ + } +} + +void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) +{ + MIPSCPU *cpu =3D env_archcpu(env); + + env->active_tc.CP0_TCHalt =3D arg1 & 0x1; + + /* TODO: Halt TC / Restart (if allocated+active) TC. */ + if (env->active_tc.CP0_TCHalt & 1) { + mips_tc_sleep(cpu, env->current_tc); + } else { + mips_tc_wake(cpu, env->current_tc); + } +} + +void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + MIPSCPU *other_cpu =3D env_archcpu(other); + + /* TODO: Halt TC / Restart (if allocated+active) TC. */ + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.CP0_TCHalt =3D arg1; + } else { + other->tcs[other_tc].CP0_TCHalt =3D arg1; + } + + if (arg1 & 1) { + mips_tc_sleep(other_cpu, other_tc); + } else { + mips_tc_wake(other_cpu, other_tc); + } +} + +void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) +{ + env->active_tc.CP0_TCContext =3D arg1; +} + +void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.CP0_TCContext =3D arg1; + } else { + other->tcs[other_tc].CP0_TCContext =3D arg1; + } +} + +void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) +{ + env->active_tc.CP0_TCSchedule =3D arg1; +} + +void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.CP0_TCSchedule =3D arg1; + } else { + other->tcs[other_tc].CP0_TCSchedule =3D arg1; + } +} + +void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) +{ + env->active_tc.CP0_TCScheFBack =3D arg1; +} + +void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.CP0_TCScheFBack =3D arg1; + } else { + other->tcs[other_tc].CP0_TCScheFBack =3D arg1; + } +} + +void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) +{ + /* 1k pages not implemented */ + target_ulong rxi =3D arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); + env->CP0_EntryLo1 =3D (arg1 & MTC0_ENTRYLO_MASK(env)) + | (rxi << (CP0EnLo_XI - 30)); +} + +#if defined(TARGET_MIPS64) +void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1) +{ + uint64_t rxi =3D arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) <<= 32); + env->CP0_EntryLo1 =3D (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; +} +#endif + +void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_Context =3D (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007F= FFFF); +} + +void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) +{ + int32_t old; + old =3D env->CP0_MemoryMapID; + env->CP0_MemoryMapID =3D (int32_t) arg1; + /* If the MemoryMapID changes, flush qemu's TLB. */ + if (old !=3D env->CP0_MemoryMapID) { + cpu_mips_tlb_flush(env); + } +} + +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk) +{ + uint64_t mask =3D arg1 >> (TARGET_PAGE_BITS + 1); + if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 =3D=3D ~0) || + (mask =3D=3D 0x0000 || mask =3D=3D 0x0003 || mask =3D=3D 0x000F || + mask =3D=3D 0x003F || mask =3D=3D 0x00FF || mask =3D=3D 0x03FF || + mask =3D=3D 0x0FFF || mask =3D=3D 0x3FFF || mask =3D=3D 0xFFFF)) { + env->CP0_PageMask =3D arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)= ); + } +} + +void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) +{ + update_pagemask(env, arg1, &env->CP0_PageMask); +} + +void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) +{ + /* SmartMIPS not implemented */ + /* 1k pages not implemented */ + env->CP0_PageGrain =3D (arg1 & env->CP0_PageGrain_rw_bitmask) | + (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitm= ask); + compute_hflags(env); + restore_pamask(env); +} + +void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) +{ + CPUState *cs =3D env_cpu(env); + + env->CP0_SegCtl0 =3D arg1 & CP0SC0_MASK; + tlb_flush(cs); +} + +void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) +{ + CPUState *cs =3D env_cpu(env); + + env->CP0_SegCtl1 =3D arg1 & CP0SC1_MASK; + tlb_flush(cs); +} + +void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) +{ + CPUState *cs =3D env_cpu(env); + + env->CP0_SegCtl2 =3D arg1 & CP0SC2_MASK; + tlb_flush(cs); +} + +void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) +{ +#if defined(TARGET_MIPS64) + uint64_t mask =3D 0x3F3FFFFFFFULL; + uint32_t old_ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; + uint32_t new_ptei =3D (arg1 >> CP0PF_PTEI) & 0x3FULL; + + if ((env->insn_flags & ISA_MIPS32R6)) { + if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) { + mask &=3D ~(0x3FULL << CP0PF_BDI); + } + if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) { + mask &=3D ~(0x3FULL << CP0PF_GDI); + } + if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) { + mask &=3D ~(0x3FULL << CP0PF_UDI); + } + if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) { + mask &=3D ~(0x3FULL << CP0PF_MDI); + } + if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) { + mask &=3D ~(0x3FULL << CP0PF_PTI); + } + } + env->CP0_PWField =3D arg1 & mask; + + if ((new_ptei >=3D 32) || + ((env->insn_flags & ISA_MIPS32R6) && + (new_ptei =3D=3D 0 || new_ptei =3D=3D 1))) { + env->CP0_PWField =3D (env->CP0_PWField & ~0x3FULL) | + (old_ptei << CP0PF_PTEI); + } +#else + uint32_t mask =3D 0x3FFFFFFF; + uint32_t old_ptew =3D (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; + uint32_t new_ptew =3D (arg1 >> CP0PF_PTEW) & 0x3F; + + if ((env->insn_flags & ISA_MIPS32R6)) { + if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_GDW); + } + if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_UDW); + } + if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_MDW); + } + if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) { + mask &=3D ~(0x3F << CP0PF_PTW); + } + } + env->CP0_PWField =3D arg1 & mask; + + if ((new_ptew >=3D 32) || + ((env->insn_flags & ISA_MIPS32R6) && + (new_ptew =3D=3D 0 || new_ptew =3D=3D 1))) { + env->CP0_PWField =3D (env->CP0_PWField & ~0x3F) | + (old_ptew << CP0PF_PTEW); + } +#endif +} + +void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1) +{ +#if defined(TARGET_MIPS64) + env->CP0_PWSize =3D arg1 & 0x3F7FFFFFFFULL; +#else + env->CP0_PWSize =3D arg1 & 0x3FFFFFFF; +#endif +} + +void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) +{ + if (env->insn_flags & ISA_MIPS32R6) { + if (arg1 < env->tlb->nb_tlb) { + env->CP0_Wired =3D arg1; + } + } else { + env->CP0_Wired =3D arg1 % env->tlb->nb_tlb; + } +} + +void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1) +{ +#if defined(TARGET_MIPS64) + /* PWEn =3D 0. Hardware page table walking is not implemented. */ + env->CP0_PWCtl =3D (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F); +#else + env->CP0_PWCtl =3D (arg1 & 0x800000FF); +#endif +} + +void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_SRSConf0 |=3D arg1 & env->CP0_SRSConf0_rw_bitmask; +} + +void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_SRSConf1 |=3D arg1 & env->CP0_SRSConf1_rw_bitmask; +} + +void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_SRSConf2 |=3D arg1 & env->CP0_SRSConf2_rw_bitmask; +} + +void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_SRSConf3 |=3D arg1 & env->CP0_SRSConf3_rw_bitmask; +} + +void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_SRSConf4 |=3D arg1 & env->CP0_SRSConf4_rw_bitmask; +} + +void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask =3D 0x0000000F; + + if ((env->CP0_Config1 & (1 << CP0C1_PC)) && + (env->insn_flags & ISA_MIPS32R6)) { + mask |=3D (1 << 4); + } + if (env->insn_flags & ISA_MIPS32R6) { + mask |=3D (1 << 5); + } + if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { + mask |=3D (1 << 29); + + if (arg1 & (1 << 29)) { + env->hflags |=3D MIPS_HFLAG_HWRENA_ULR; + } else { + env->hflags &=3D ~MIPS_HFLAG_HWRENA_ULR; + } + } + + env->CP0_HWREna =3D arg1 & mask; +} + +void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) +{ + cpu_mips_store_count(env, arg1); +} + +void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D arg1 & 0x3f; + if (target <=3D 1) { + env->CP0_SAARI =3D target; + } +} + +void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } + } +} + +void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t target =3D env->CP0_SAARI & 0x3f; + if (target < 2) { + env->CP0_SAAR[target] =3D + (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | + (env->CP0_SAAR[target] & 0x00000000ffffffffULL); + switch (target) { + case 0: + if (env->itu) { + itc_reconfigure(env->itu); + } + break; + } + } +} + +void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) +{ + target_ulong old, val, mask; + mask =3D (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; + if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >=3D 2) { + mask |=3D 1 << CP0EnHi_EHINV; + } + + /* 1k pages not implemented */ +#if defined(TARGET_MIPS64) + if (env->insn_flags & ISA_MIPS32R6) { + int entryhi_r =3D extract64(arg1, 62, 2); + int config0_at =3D extract32(env->CP0_Config0, 13, 2); + bool no_supervisor =3D (env->CP0_Status_rw_bitmask & 0x8) =3D=3D 0; + if ((entryhi_r =3D=3D 2) || + (entryhi_r =3D=3D 1 && (no_supervisor || config0_at =3D=3D 1))= ) { + /* skip EntryHi.R field if new value is reserved */ + mask &=3D ~(0x3ull << 62); + } + } + mask &=3D env->SEGMask; +#endif + old =3D env->CP0_EntryHi; + val =3D (arg1 & mask) | (old & ~mask); + env->CP0_EntryHi =3D val; + if (env->CP0_Config3 & (1 << CP0C3_MT)) { + sync_c0_entryhi(env, env->current_tc); + } + /* If the ASID changes, flush qemu's TLB. */ + if ((old & env->CP0_EntryHi_ASID_mask) !=3D + (val & env->CP0_EntryHi_ASID_mask)) { + tlb_flush(env_cpu(env)); + } +} + +void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + other->CP0_EntryHi =3D arg1; + sync_c0_entryhi(other, other_tc); +} + +void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) +{ + cpu_mips_store_compare(env, arg1); +} + +void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t val, old; + + old =3D env->CP0_Status; + cpu_mips_store_status(env, arg1); + val =3D env->CP0_Status; + + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("Status %08x (%08x) =3D> %08x (%08x) Cause %08x", + old, old & env->CP0_Cause & CP0Ca_IP_mask, + val, val & env->CP0_Cause & CP0Ca_IP_mask, + env->CP0_Cause); + switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; + default: + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); + break; + } + } +} + +void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t mask =3D env->CP0_Status_rw_bitmask & ~0xf1000018; + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + other->CP0_Status =3D (other->CP0_Status & ~mask) | (arg1 & mask); + sync_c0_status(env, other, other_tc); +} + +void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_IntCtl =3D (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003= e0); +} + +void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) +{ + uint32_t mask =3D (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); + env->CP0_SRSCtl =3D (env->CP0_SRSCtl & ~mask) | (arg1 & mask); +} + +void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) +{ + cpu_mips_store_cause(env, arg1); +} + +void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + cpu_mips_store_cause(other, arg1); +} + +target_ulong helper_mftc0_epc(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + return other->CP0_EPC; +} + +target_ulong helper_mftc0_ebase(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + return other->CP0_EBase; +} + +void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) +{ + target_ulong mask =3D 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; + if (arg1 & env->CP0_EBaseWG_rw_bitmask) { + mask |=3D ~0x3FFFFFFF; + } + env->CP0_EBase =3D (env->CP0_EBase & ~mask) | (arg1 & mask); +} + +void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + target_ulong mask =3D 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; + if (arg1 & env->CP0_EBaseWG_rw_bitmask) { + mask |=3D ~0x3FFFFFFF; + } + other->CP0_EBase =3D (other->CP0_EBase & ~mask) | (arg1 & mask); +} + +target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + switch (idx) { + case 0: return other->CP0_Config0; + case 1: return other->CP0_Config1; + case 2: return other->CP0_Config2; + case 3: return other->CP0_Config3; + /* 4 and 5 are reserved. */ + case 6: return other->CP0_Config6; + case 7: return other->CP0_Config7; + default: + break; + } + return 0; +} + +void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_Config0 =3D (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000= 007); +} + +void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) +{ + /* tertiary/secondary caches not implemented */ + env->CP0_Config2 =3D (env->CP0_Config2 & 0x8FFF0FFF); +} + +void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1) +{ + if (env->insn_flags & ASE_MICROMIPS) { + env->CP0_Config3 =3D (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC))= | + (arg1 & (1 << CP0C3_ISA_ON_EXC)); + } +} + +void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_Config4 =3D (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask= )) | + (arg1 & env->CP0_Config4_rw_bitmask); +} + +void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_Config5 =3D (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask= )) | + (arg1 & env->CP0_Config5_rw_bitmask); + env->CP0_EntryHi_ASID_mask =3D (env->CP0_Config5 & (1 << CP0C5_MI)) ? + 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; + compute_hflags(env); +} + +void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) +{ + target_long mask =3D env->CP0_LLAddr_rw_bitmask; + arg1 =3D arg1 << env->CP0_LLAddr_shift; + env->CP0_LLAddr =3D (env->CP0_LLAddr & ~mask) | (arg1 & mask); +} + +#define MTC0_MAAR_MASK(env) \ + ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3) + +void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_MAAR[env->CP0_MAARI] =3D arg1 & MTC0_MAAR_MASK(env); +} + +void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_MAAR[env->CP0_MAARI] =3D + (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) | + (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL); +} + +void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1) +{ + int index =3D arg1 & 0x3f; + if (index =3D=3D 0x3f) { + /* + * Software may write all ones to INDEX to determine the + * maximum value supported. + */ + env->CP0_MAARI =3D MIPS_MAAR_MAX - 1; + } else if (index < MIPS_MAAR_MAX) { + env->CP0_MAARI =3D index; + } + /* + * Other than the all ones, if the value written is not supported, + * then INDEX is unchanged from its previous value. + */ +} + +void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) +{ + /* + * Watch exceptions for instructions, data loads, data stores + * not implemented. + */ + env->CP0_WatchLo[sel] =3D (arg1 & ~0x7); +} + +void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) +{ + uint64_t mask =3D 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_AS= ID); + if ((env->CP0_Config5 >> CP0C5_MI) & 1) { + mask |=3D 0xFFFFFFFF00000000ULL; /* MMID */ + } + env->CP0_WatchHi[sel] =3D arg1 & mask; + env->CP0_WatchHi[sel] &=3D ~(env->CP0_WatchHi[sel] & arg1 & 0x7); +} + +void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t s= el) +{ + env->CP0_WatchHi[sel] =3D ((uint64_t) (arg1) << 32) | + (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL= ); +} + +void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) +{ + target_ulong mask =3D (1ULL << (env->SEGBITS - 7)) - 1; + env->CP0_XContext =3D (env->CP0_XContext & mask) | (arg1 & ~mask); +} + +void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_Framemask =3D arg1; /* XXX */ +} + +void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_Debug =3D (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); + if (arg1 & (1 << CP0DB_DM)) { + env->hflags |=3D MIPS_HFLAG_DM; + } else { + env->hflags &=3D ~MIPS_HFLAG_DM; + } +} + +void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + uint32_t val =3D arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + /* XXX: Might be wrong, check with EJTAG spec. */ + if (other_tc =3D=3D other->current_tc) { + other->active_tc.CP0_Debug_tcstatus =3D val; + } else { + other->tcs[other_tc].CP0_Debug_tcstatus =3D val; + } + other->CP0_Debug =3D (other->CP0_Debug & + ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | + (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); +} + +void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_Performance0 =3D arg1 & 0x000007ff; +} + +void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1) +{ + int32_t wst =3D arg1 & (1 << CP0EC_WST); + int32_t spr =3D arg1 & (1 << CP0EC_SPR); + int32_t itc =3D env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0; + + env->CP0_ErrCtl =3D wst | spr | itc; + + if (itc && !wst && !spr) { + env->hflags |=3D MIPS_HFLAG_ITC_CACHE; + } else { + env->hflags &=3D ~MIPS_HFLAG_ITC_CACHE; + } +} + +void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) +{ + if (env->hflags & MIPS_HFLAG_ITC_CACHE) { + /* + * If CACHE instruction is configured for ITC tags then make all + * CP0.TagLo bits writable. The actual write to ITC Configuration + * Tag will take care of the read-only bits. + */ + env->CP0_TagLo =3D arg1; + } else { + env->CP0_TagLo =3D arg1 & 0xFFFFFCF6; + } +} + +void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_DataLo =3D arg1; /* XXX */ +} + +void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_TagHi =3D arg1; /* XXX */ +} + +void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) +{ + env->CP0_DataHi =3D arg1; /* XXX */ +} + +/* MIPS MT functions */ +target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.gpr[sel]; + } else { + return other->tcs[other_tc].gpr[sel]; + } +} + +target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.LO[sel]; + } else { + return other->tcs[other_tc].LO[sel]; + } +} + +target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.HI[sel]; + } else { + return other->tcs[other_tc].HI[sel]; + } +} + +target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.ACX[sel]; + } else { + return other->tcs[other_tc].ACX[sel]; + } +} + +target_ulong helper_mftdsp(CPUMIPSState *env) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + return other->active_tc.DSPControl; + } else { + return other->tcs[other_tc].DSPControl; + } +} + +void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.gpr[sel] =3D arg1; + } else { + other->tcs[other_tc].gpr[sel] =3D arg1; + } +} + +void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.LO[sel] =3D arg1; + } else { + other->tcs[other_tc].LO[sel] =3D arg1; + } +} + +void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.HI[sel] =3D arg1; + } else { + other->tcs[other_tc].HI[sel] =3D arg1; + } +} + +void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.ACX[sel] =3D arg1; + } else { + other->tcs[other_tc].ACX[sel] =3D arg1; + } +} + +void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) +{ + int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); + CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); + + if (other_tc =3D=3D other->current_tc) { + other->active_tc.DSPControl =3D arg1; + } else { + other->tcs[other_tc].DSPControl =3D arg1; + } +} + +/* MIPS MT functions */ +target_ulong helper_dmt(void) +{ + /* TODO */ + return 0; +} + +target_ulong helper_emt(void) +{ + /* TODO */ + return 0; +} + +target_ulong helper_dvpe(CPUMIPSState *env) +{ + CPUState *other_cs =3D first_cpu; + target_ulong prev =3D env->mvp->CP0_MVPControl; + + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + /* Turn off all VPEs except the one executing the dvpe. */ + if (&other_cpu->env !=3D env) { + other_cpu->env.mvp->CP0_MVPControl &=3D ~(1 << CP0MVPCo_EVP); + mips_vpe_sleep(other_cpu); + } + } + return prev; +} + +target_ulong helper_evpe(CPUMIPSState *env) +{ + CPUState *other_cs =3D first_cpu; + target_ulong prev =3D env->mvp->CP0_MVPControl; + + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + + if (&other_cpu->env !=3D env + /* If the VPE is WFI, don't disturb its sleep. */ + && !mips_vpe_is_wfi(other_cpu)) { + /* Enable the VPE. */ + other_cpu->env.mvp->CP0_MVPControl |=3D (1 << CP0MVPCo_EVP); + mips_vpe_wake(other_cpu); /* And wake it up. */ + } + } + return prev; +} +#endif /* !CONFIG_USER_ONLY */ + +/* R6 Multi-threading */ +#ifndef CONFIG_USER_ONLY +target_ulong helper_dvp(CPUMIPSState *env) +{ + CPUState *other_cs =3D first_cpu; + target_ulong prev =3D env->CP0_VPControl; + + if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + /* Turn off all VPs except the one executing the dvp. */ + if (&other_cpu->env !=3D env) { + mips_vpe_sleep(other_cpu); + } + } + env->CP0_VPControl |=3D (1 << CP0VPCtl_DIS); + } + return prev; +} + +target_ulong helper_evp(CPUMIPSState *env) +{ + CPUState *other_cs =3D first_cpu; + target_ulong prev =3D env->CP0_VPControl; + + if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); + if ((&other_cpu->env !=3D env) && !mips_vp_is_wfi(other_cpu)) { + /* + * If the VP is WFI, don't disturb its sleep. + * Otherwise, wake it up. + */ + mips_vpe_wake(other_cpu); + } + } + env->CP0_VPControl &=3D ~(1 << CP0VPCtl_DIS); + } + return prev; +} +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 467914d..27c3963 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -15,7 +15,9 @@ * * You should have received a copy of the GNU Lesser General Public * License along with this library; if not, see . + * */ + #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" @@ -28,6 +30,7 @@ #include "sysemu/kvm.h" #include "fpu/softfloat.h" =20 + /*************************************************************************= ****/ /* Exceptions processing helpers */ =20 @@ -560,1689 +563,45 @@ void helper_sdm(CPUMIPSState *env, target_ulong add= r, target_ulong reglist, } #endif =20 -#ifndef CONFIG_USER_ONLY -/* SMP helpers. */ -static bool mips_vpe_is_wfi(MIPSCPU *c) -{ - CPUState *cpu =3D CPU(c); - CPUMIPSState *env =3D &c->env; - - /* - * If the VPE is halted but otherwise active, it means it's waiting for - * an interrupt.\ - */ - return cpu->halted && mips_vpe_active(env); -} - -static bool mips_vp_is_wfi(MIPSCPU *c) -{ - CPUState *cpu =3D CPU(c); - CPUMIPSState *env =3D &c->env; - - return cpu->halted && mips_vp_active(env); -} - -static inline void mips_vpe_wake(MIPSCPU *c) -{ - /* - * Don't set ->halted =3D 0 directly, let it be done via cpu_has_work - * because there might be other conditions that state that c should - * be sleeping. - */ - qemu_mutex_lock_iothread(); - cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE); - qemu_mutex_unlock_iothread(); -} =20 -static inline void mips_vpe_sleep(MIPSCPU *cpu) +void helper_fork(target_ulong arg1, target_ulong arg2) { - CPUState *cs =3D CPU(cpu); - /* - * The VPE was shut off, really go to bed. - * Reset any old _WAKE requests. + * arg1 =3D rt, arg2 =3D rs + * TODO: store to TC register */ - cs->halted =3D 1; - cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); -} - -static inline void mips_tc_wake(MIPSCPU *cpu, int tc) -{ - CPUMIPSState *c =3D &cpu->env; - - /* FIXME: TC reschedule. */ - if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) { - mips_vpe_wake(cpu); - } -} - -static inline void mips_tc_sleep(MIPSCPU *cpu, int tc) -{ - CPUMIPSState *c =3D &cpu->env; - - /* FIXME: TC reschedule. */ - if (!mips_vpe_active(c)) { - mips_vpe_sleep(cpu); - } -} - -/** - * mips_cpu_map_tc: - * @env: CPU from which mapping is performed. - * @tc: Should point to an int with the value of the global TC index. - * - * This function will transform @tc into a local index within the - * returned #CPUMIPSState. - */ - -/* - * FIXME: This code assumes that all VPEs have the same number of TCs, - * which depends on runtime setup. Can probably be fixed by - * walking the list of CPUMIPSStates. - */ -static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc) -{ - MIPSCPU *cpu; - CPUState *cs; - CPUState *other_cs; - int vpe_idx; - int tc_idx =3D *tc; - - if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) { - /* Not allowed to address other CPUs. */ - *tc =3D env->current_tc; - return env; - } - - cs =3D env_cpu(env); - vpe_idx =3D tc_idx / cs->nr_threads; - *tc =3D tc_idx % cs->nr_threads; - other_cs =3D qemu_get_cpu(vpe_idx); - if (other_cs =3D=3D NULL) { - return env; - } - cpu =3D MIPS_CPU(other_cs); - return &cpu->env; -} - -/* - * The per VPE CP0_Status register shares some fields with the per TC - * CP0_TCStatus registers. These fields are wired to the same registers, - * so changes to either of them should be reflected on both registers. - * - * Also, EntryHi shares the bottom 8 bit ASID with TCStauts. - * - * These helper call synchronizes the regs for a given cpu. - */ - -/* - * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. - * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, - * int tc); - */ - -/* Called for updates to CP0_TCStatus. */ -static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, - target_ulong v) -{ - uint32_t status; - uint32_t tcu, tmx, tasid, tksu; - uint32_t mask =3D ((1U << CP0St_CU3) - | (1 << CP0St_CU2) - | (1 << CP0St_CU1) - | (1 << CP0St_CU0) - | (1 << CP0St_MX) - | (3 << CP0St_KSU)); - - tcu =3D (v >> CP0TCSt_TCU0) & 0xf; - tmx =3D (v >> CP0TCSt_TMX) & 0x1; - tasid =3D v & cpu->CP0_EntryHi_ASID_mask; - tksu =3D (v >> CP0TCSt_TKSU) & 0x3; - - status =3D tcu << CP0St_CU0; - status |=3D tmx << CP0St_MX; - status |=3D tksu << CP0St_KSU; - - cpu->CP0_Status &=3D ~mask; - cpu->CP0_Status |=3D status; - - /* Sync the TASID with EntryHi. */ - cpu->CP0_EntryHi &=3D ~cpu->CP0_EntryHi_ASID_mask; - cpu->CP0_EntryHi |=3D tasid; - - compute_hflags(cpu); -} - -/* Called for updates to CP0_EntryHi. */ -static void sync_c0_entryhi(CPUMIPSState *cpu, int tc) -{ - int32_t *tcst; - uint32_t asid, v =3D cpu->CP0_EntryHi; - - asid =3D v & cpu->CP0_EntryHi_ASID_mask; - - if (tc =3D=3D cpu->current_tc) { - tcst =3D &cpu->active_tc.CP0_TCStatus; - } else { - tcst =3D &cpu->tcs[tc].CP0_TCStatus; - } - - *tcst &=3D ~cpu->CP0_EntryHi_ASID_mask; - *tcst |=3D asid; -} - -/* CP0 helpers */ -target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env) -{ - return env->mvp->CP0_MVPControl; -} - -target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env) -{ - return env->mvp->CP0_MVPConf0; -} - -target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env) -{ - return env->mvp->CP0_MVPConf1; -} - -target_ulong helper_mfc0_random(CPUMIPSState *env) -{ - return (int32_t)cpu_mips_get_random(env); -} - -target_ulong helper_mfc0_tcstatus(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCStatus; -} - -target_ulong helper_mftc0_tcstatus(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.CP0_TCStatus; - } else { - return other->tcs[other_tc].CP0_TCStatus; - } -} - -target_ulong helper_mfc0_tcbind(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCBind; -} - -target_ulong helper_mftc0_tcbind(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.CP0_TCBind; - } else { - return other->tcs[other_tc].CP0_TCBind; - } -} - -target_ulong helper_mfc0_tcrestart(CPUMIPSState *env) -{ - return env->active_tc.PC; -} - -target_ulong helper_mftc0_tcrestart(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.PC; - } else { - return other->tcs[other_tc].PC; - } -} - -target_ulong helper_mfc0_tchalt(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCHalt; -} - -target_ulong helper_mftc0_tchalt(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.CP0_TCHalt; - } else { - return other->tcs[other_tc].CP0_TCHalt; - } -} - -target_ulong helper_mfc0_tccontext(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCContext; -} - -target_ulong helper_mftc0_tccontext(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.CP0_TCContext; - } else { - return other->tcs[other_tc].CP0_TCContext; - } -} - -target_ulong helper_mfc0_tcschedule(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCSchedule; } =20 -target_ulong helper_mftc0_tcschedule(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.CP0_TCSchedule; - } else { - return other->tcs[other_tc].CP0_TCSchedule; - } -} - -target_ulong helper_mfc0_tcschefback(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCScheFBack; -} - -target_ulong helper_mftc0_tcschefback(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.CP0_TCScheFBack; - } else { - return other->tcs[other_tc].CP0_TCScheFBack; - } -} - -target_ulong helper_mfc0_count(CPUMIPSState *env) -{ - return (int32_t)cpu_mips_get_count(env); -} - -target_ulong helper_mfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return (int32_t) env->CP0_SAAR[env->CP0_SAARI & 0x3f]; - } - return 0; -} - -target_ulong helper_mfhc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f] >> 32; - } - return 0; -} - -target_ulong helper_mftc0_entryhi(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - return other->CP0_EntryHi; -} - -target_ulong helper_mftc0_cause(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - int32_t tccause; - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - tccause =3D other->CP0_Cause; - } else { - tccause =3D other->CP0_Cause; - } - - return tccause; -} - -target_ulong helper_mftc0_status(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - return other->CP0_Status; -} - -target_ulong helper_mfc0_lladdr(CPUMIPSState *env) -{ - return (int32_t)(env->CP0_LLAddr >> env->CP0_LLAddr_shift); -} - -target_ulong helper_mfc0_maar(CPUMIPSState *env) -{ - return (int32_t) env->CP0_MAAR[env->CP0_MAARI]; -} - -target_ulong helper_mfhc0_maar(CPUMIPSState *env) -{ - return env->CP0_MAAR[env->CP0_MAARI] >> 32; -} - -target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel) -{ - return (int32_t)env->CP0_WatchLo[sel]; -} - -target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel) -{ - return (int32_t) env->CP0_WatchHi[sel]; -} - -target_ulong helper_mfhc0_watchhi(CPUMIPSState *env, uint32_t sel) -{ - return env->CP0_WatchHi[sel] >> 32; -} - -target_ulong helper_mfc0_debug(CPUMIPSState *env) -{ - target_ulong t0 =3D env->CP0_Debug; - if (env->hflags & MIPS_HFLAG_DM) { - t0 |=3D 1 << CP0DB_DM; - } - - return t0; -} - -target_ulong helper_mftc0_debug(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - int32_t tcstatus; - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - tcstatus =3D other->active_tc.CP0_Debug_tcstatus; - } else { - tcstatus =3D other->tcs[other_tc].CP0_Debug_tcstatus; - } - - /* XXX: Might be wrong, check with EJTAG spec. */ - return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | - (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); -} - -#if defined(TARGET_MIPS64) -target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env) -{ - return env->active_tc.PC; -} - -target_ulong helper_dmfc0_tchalt(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCHalt; -} - -target_ulong helper_dmfc0_tccontext(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCContext; -} - -target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCSchedule; -} - -target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env) -{ - return env->active_tc.CP0_TCScheFBack; -} - -target_ulong helper_dmfc0_lladdr(CPUMIPSState *env) -{ - return env->CP0_LLAddr >> env->CP0_LLAddr_shift; -} - -target_ulong helper_dmfc0_maar(CPUMIPSState *env) -{ - return env->CP0_MAAR[env->CP0_MAARI]; -} - -target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel) -{ - return env->CP0_WatchLo[sel]; -} - -target_ulong helper_dmfc0_watchhi(CPUMIPSState *env, uint32_t sel) +target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) { - return env->CP0_WatchHi[sel]; -} + target_long arg1 =3D arg; =20 -target_ulong helper_dmfc0_saar(CPUMIPSState *env) -{ - if ((env->CP0_SAARI & 0x3f) < 2) { - return env->CP0_SAAR[env->CP0_SAARI & 0x3f]; + if (arg1 < 0) { + /* No scheduling policy implemented. */ + if (arg1 !=3D -2) { + if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && + env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { + env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |=3D 4 << CP0VPECo_EXCPT; + do_raise_exception(env, EXCP_THREAD, GETPC()); + } + } + } else if (arg1 =3D=3D 0) { + if (0) { + /* TODO: TC underflow */ + env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); + do_raise_exception(env, EXCP_THREAD, GETPC()); + } else { + /* TODO: Deallocate TC */ + } + } else if (arg1 > 0) { + /* Yield qualifier inputs not implemented. */ + env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |=3D 2 << CP0VPECo_EXCPT; + do_raise_exception(env, EXCP_THREAD, GETPC()); } - return 0; + return env->CP0_YQMask; } -#endif /* TARGET_MIPS64 */ - -void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t index_p =3D env->CP0_Index & 0x80000000; - uint32_t tlb_index =3D arg1 & 0x7fffffff; - if (tlb_index < env->tlb->nb_tlb) { - if (env->insn_flags & ISA_MIPS32R6) { - index_p |=3D arg1 & 0x80000000; - } - env->CP0_Index =3D index_p | tlb_index; - } -} - -void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask =3D 0; - uint32_t newval; - - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { - mask |=3D (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) | - (1 << CP0MVPCo_EVP); - } - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { - mask |=3D (1 << CP0MVPCo_STLB); - } - newval =3D (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask); - - /* TODO: Enable/disable shared TLB, enable/disable VPEs. */ - - env->mvp->CP0_MVPControl =3D newval; -} - -void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask; - uint32_t newval; - - mask =3D (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | - (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); - newval =3D (env->CP0_VPEControl & ~mask) | (arg1 & mask); - - /* - * Yield scheduler intercept not implemented. - * Gating storage scheduler intercept not implemented. - */ - - /* TODO: Enable/disable TCs. */ - - env->CP0_VPEControl =3D newval; -} - -void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - uint32_t mask; - uint32_t newval; - - mask =3D (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) | - (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC); - newval =3D (other->CP0_VPEControl & ~mask) | (arg1 & mask); - - /* TODO: Enable/disable TCs. */ - - other->CP0_VPEControl =3D newval; -} - -target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - /* FIXME: Mask away return zero on read bits. */ - return other->CP0_VPEControl; -} - -target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - return other->CP0_VPEConf0; -} - -void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask =3D 0; - uint32_t newval; - - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) { - if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) { - mask |=3D (0xff << CP0VPEC0_XTC); - } - mask |=3D (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); - } - newval =3D (env->CP0_VPEConf0 & ~mask) | (arg1 & mask); - - /* TODO: TC exclusive handling due to ERL/EXL. */ - - env->CP0_VPEConf0 =3D newval; -} - -void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - uint32_t mask =3D 0; - uint32_t newval; - - mask |=3D (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA); - newval =3D (other->CP0_VPEConf0 & ~mask) | (arg1 & mask); - - /* TODO: TC exclusive handling due to ERL/EXL. */ - other->CP0_VPEConf0 =3D newval; -} - -void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask =3D 0; - uint32_t newval; - - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) - mask |=3D (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) | - (0xff << CP0VPEC1_NCP1); - newval =3D (env->CP0_VPEConf1 & ~mask) | (arg1 & mask); - - /* UDI not implemented. */ - /* CP2 not implemented. */ - - /* TODO: Handle FPU (CP1) binding. */ - - env->CP0_VPEConf1 =3D newval; -} - -void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1) -{ - /* Yield qualifier inputs not implemented. */ - env->CP0_YQMask =3D 0x00000000; -} - -void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_VPEOpt =3D arg1 & 0x0000ffff; -} - -#define MTC0_ENTRYLO_MASK(env) ((env->PAMask >> 6) & 0x3FFFFFFF) - -void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1) -{ - /* 1k pages not implemented */ - target_ulong rxi =3D arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); - env->CP0_EntryLo0 =3D (arg1 & MTC0_ENTRYLO_MASK(env)) - | (rxi << (CP0EnLo_XI - 30)); -} - -#if defined(TARGET_MIPS64) -#define DMTC0_ENTRYLO_MASK(env) (env->PAMask >> 6) - -void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1) -{ - uint64_t rxi =3D arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) <<= 32); - env->CP0_EntryLo0 =3D (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; -} -#endif - -void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask =3D env->CP0_TCStatus_rw_bitmask; - uint32_t newval; - - newval =3D (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask); - - env->active_tc.CP0_TCStatus =3D newval; - sync_c0_tcstatus(env, env->current_tc, newval); -} - -void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.CP0_TCStatus =3D arg1; - } else { - other->tcs[other_tc].CP0_TCStatus =3D arg1; - } - sync_c0_tcstatus(other, other_tc, arg1); -} - -void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask =3D (1 << CP0TCBd_TBE); - uint32_t newval; - - if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { - mask |=3D (1 << CP0TCBd_CurVPE); - } - newval =3D (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); - env->active_tc.CP0_TCBind =3D newval; -} - -void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - uint32_t mask =3D (1 << CP0TCBd_TBE); - uint32_t newval; - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) { - mask |=3D (1 << CP0TCBd_CurVPE); - } - if (other_tc =3D=3D other->current_tc) { - newval =3D (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask); - other->active_tc.CP0_TCBind =3D newval; - } else { - newval =3D (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mas= k); - other->tcs[other_tc].CP0_TCBind =3D newval; - } -} - -void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1) -{ - env->active_tc.PC =3D arg1; - env->active_tc.CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); - env->CP0_LLAddr =3D 0; - env->lladdr =3D 0; - /* MIPS16 not implemented. */ -} - -void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.PC =3D arg1; - other->active_tc.CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); - other->CP0_LLAddr =3D 0; - other->lladdr =3D 0; - /* MIPS16 not implemented. */ - } else { - other->tcs[other_tc].PC =3D arg1; - other->tcs[other_tc].CP0_TCStatus &=3D ~(1 << CP0TCSt_TDS); - other->CP0_LLAddr =3D 0; - other->lladdr =3D 0; - /* MIPS16 not implemented. */ - } -} - -void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1) -{ - MIPSCPU *cpu =3D env_archcpu(env); - - env->active_tc.CP0_TCHalt =3D arg1 & 0x1; - - /* TODO: Halt TC / Restart (if allocated+active) TC. */ - if (env->active_tc.CP0_TCHalt & 1) { - mips_tc_sleep(cpu, env->current_tc); - } else { - mips_tc_wake(cpu, env->current_tc); - } -} - -void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - MIPSCPU *other_cpu =3D env_archcpu(other); - - /* TODO: Halt TC / Restart (if allocated+active) TC. */ - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.CP0_TCHalt =3D arg1; - } else { - other->tcs[other_tc].CP0_TCHalt =3D arg1; - } - - if (arg1 & 1) { - mips_tc_sleep(other_cpu, other_tc); - } else { - mips_tc_wake(other_cpu, other_tc); - } -} - -void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1) -{ - env->active_tc.CP0_TCContext =3D arg1; -} - -void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.CP0_TCContext =3D arg1; - } else { - other->tcs[other_tc].CP0_TCContext =3D arg1; - } -} - -void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1) -{ - env->active_tc.CP0_TCSchedule =3D arg1; -} - -void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.CP0_TCSchedule =3D arg1; - } else { - other->tcs[other_tc].CP0_TCSchedule =3D arg1; - } -} - -void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1) -{ - env->active_tc.CP0_TCScheFBack =3D arg1; -} - -void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.CP0_TCScheFBack =3D arg1; - } else { - other->tcs[other_tc].CP0_TCScheFBack =3D arg1; - } -} - -void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1) -{ - /* 1k pages not implemented */ - target_ulong rxi =3D arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE)); - env->CP0_EntryLo1 =3D (arg1 & MTC0_ENTRYLO_MASK(env)) - | (rxi << (CP0EnLo_XI - 30)); -} - -#if defined(TARGET_MIPS64) -void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1) -{ - uint64_t rxi =3D arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) <<= 32); - env->CP0_EntryLo1 =3D (arg1 & DMTC0_ENTRYLO_MASK(env)) | rxi; -} -#endif - -void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_Context =3D (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007F= FFFF); -} - -void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) -{ - int32_t old; - old =3D env->CP0_MemoryMapID; - env->CP0_MemoryMapID =3D (int32_t) arg1; - /* If the MemoryMapID changes, flush qemu's TLB. */ - if (old !=3D env->CP0_MemoryMapID) { - cpu_mips_tlb_flush(env); - } -} - -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagema= sk) -{ - uint64_t mask =3D arg1 >> (TARGET_PAGE_BITS + 1); - if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 =3D=3D ~0) || - (mask =3D=3D 0x0000 || mask =3D=3D 0x0003 || mask =3D=3D 0x000F || - mask =3D=3D 0x003F || mask =3D=3D 0x00FF || mask =3D=3D 0x03FF || - mask =3D=3D 0x0FFF || mask =3D=3D 0x3FFF || mask =3D=3D 0xFFFF)) { - env->CP0_PageMask =3D arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)= ); - } -} - -void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) -{ - update_pagemask(env, arg1, &env->CP0_PageMask); -} - -void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1) -{ - /* SmartMIPS not implemented */ - /* 1k pages not implemented */ - env->CP0_PageGrain =3D (arg1 & env->CP0_PageGrain_rw_bitmask) | - (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitm= ask); - compute_hflags(env); - restore_pamask(env); -} - -void helper_mtc0_segctl0(CPUMIPSState *env, target_ulong arg1) -{ - CPUState *cs =3D env_cpu(env); - - env->CP0_SegCtl0 =3D arg1 & CP0SC0_MASK; - tlb_flush(cs); -} - -void helper_mtc0_segctl1(CPUMIPSState *env, target_ulong arg1) -{ - CPUState *cs =3D env_cpu(env); - - env->CP0_SegCtl1 =3D arg1 & CP0SC1_MASK; - tlb_flush(cs); -} - -void helper_mtc0_segctl2(CPUMIPSState *env, target_ulong arg1) -{ - CPUState *cs =3D env_cpu(env); - - env->CP0_SegCtl2 =3D arg1 & CP0SC2_MASK; - tlb_flush(cs); -} - -void helper_mtc0_pwfield(CPUMIPSState *env, target_ulong arg1) -{ -#if defined(TARGET_MIPS64) - uint64_t mask =3D 0x3F3FFFFFFFULL; - uint32_t old_ptei =3D (env->CP0_PWField >> CP0PF_PTEI) & 0x3FULL; - uint32_t new_ptei =3D (arg1 >> CP0PF_PTEI) & 0x3FULL; - - if ((env->insn_flags & ISA_MIPS32R6)) { - if (((arg1 >> CP0PF_BDI) & 0x3FULL) < 12) { - mask &=3D ~(0x3FULL << CP0PF_BDI); - } - if (((arg1 >> CP0PF_GDI) & 0x3FULL) < 12) { - mask &=3D ~(0x3FULL << CP0PF_GDI); - } - if (((arg1 >> CP0PF_UDI) & 0x3FULL) < 12) { - mask &=3D ~(0x3FULL << CP0PF_UDI); - } - if (((arg1 >> CP0PF_MDI) & 0x3FULL) < 12) { - mask &=3D ~(0x3FULL << CP0PF_MDI); - } - if (((arg1 >> CP0PF_PTI) & 0x3FULL) < 12) { - mask &=3D ~(0x3FULL << CP0PF_PTI); - } - } - env->CP0_PWField =3D arg1 & mask; - - if ((new_ptei >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && - (new_ptei =3D=3D 0 || new_ptei =3D=3D 1))) { - env->CP0_PWField =3D (env->CP0_PWField & ~0x3FULL) | - (old_ptei << CP0PF_PTEI); - } -#else - uint32_t mask =3D 0x3FFFFFFF; - uint32_t old_ptew =3D (env->CP0_PWField >> CP0PF_PTEW) & 0x3F; - uint32_t new_ptew =3D (arg1 >> CP0PF_PTEW) & 0x3F; - - if ((env->insn_flags & ISA_MIPS32R6)) { - if (((arg1 >> CP0PF_GDW) & 0x3F) < 12) { - mask &=3D ~(0x3F << CP0PF_GDW); - } - if (((arg1 >> CP0PF_UDW) & 0x3F) < 12) { - mask &=3D ~(0x3F << CP0PF_UDW); - } - if (((arg1 >> CP0PF_MDW) & 0x3F) < 12) { - mask &=3D ~(0x3F << CP0PF_MDW); - } - if (((arg1 >> CP0PF_PTW) & 0x3F) < 12) { - mask &=3D ~(0x3F << CP0PF_PTW); - } - } - env->CP0_PWField =3D arg1 & mask; - - if ((new_ptew >=3D 32) || - ((env->insn_flags & ISA_MIPS32R6) && - (new_ptew =3D=3D 0 || new_ptew =3D=3D 1))) { - env->CP0_PWField =3D (env->CP0_PWField & ~0x3F) | - (old_ptew << CP0PF_PTEW); - } -#endif -} - -void helper_mtc0_pwsize(CPUMIPSState *env, target_ulong arg1) -{ -#if defined(TARGET_MIPS64) - env->CP0_PWSize =3D arg1 & 0x3F7FFFFFFFULL; -#else - env->CP0_PWSize =3D arg1 & 0x3FFFFFFF; -#endif -} - -void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1) -{ - if (env->insn_flags & ISA_MIPS32R6) { - if (arg1 < env->tlb->nb_tlb) { - env->CP0_Wired =3D arg1; - } - } else { - env->CP0_Wired =3D arg1 % env->tlb->nb_tlb; - } -} - -void helper_mtc0_pwctl(CPUMIPSState *env, target_ulong arg1) -{ -#if defined(TARGET_MIPS64) - /* PWEn =3D 0. Hardware page table walking is not implemented. */ - env->CP0_PWCtl =3D (env->CP0_PWCtl & 0x000000C0) | (arg1 & 0x5C00003F); -#else - env->CP0_PWCtl =3D (arg1 & 0x800000FF); -#endif -} - -void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_SRSConf0 |=3D arg1 & env->CP0_SRSConf0_rw_bitmask; -} - -void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_SRSConf1 |=3D arg1 & env->CP0_SRSConf1_rw_bitmask; -} - -void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_SRSConf2 |=3D arg1 & env->CP0_SRSConf2_rw_bitmask; -} - -void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_SRSConf3 |=3D arg1 & env->CP0_SRSConf3_rw_bitmask; -} - -void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_SRSConf4 |=3D arg1 & env->CP0_SRSConf4_rw_bitmask; -} - -void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask =3D 0x0000000F; - - if ((env->CP0_Config1 & (1 << CP0C1_PC)) && - (env->insn_flags & ISA_MIPS32R6)) { - mask |=3D (1 << 4); - } - if (env->insn_flags & ISA_MIPS32R6) { - mask |=3D (1 << 5); - } - if (env->CP0_Config3 & (1 << CP0C3_ULRI)) { - mask |=3D (1 << 29); - - if (arg1 & (1 << 29)) { - env->hflags |=3D MIPS_HFLAG_HWRENA_ULR; - } else { - env->hflags &=3D ~MIPS_HFLAG_HWRENA_ULR; - } - } - - env->CP0_HWREna =3D arg1 & mask; -} - -void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1) -{ - cpu_mips_store_count(env, arg1); -} - -void helper_mtc0_saari(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target =3D arg1 & 0x3f; - if (target <=3D 1) { - env->CP0_SAARI =3D target; - } -} - -void helper_mtc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target =3D env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] =3D arg1 & 0x00000ffffffff03fULL; - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - -void helper_mthc0_saar(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t target =3D env->CP0_SAARI & 0x3f; - if (target < 2) { - env->CP0_SAAR[target] =3D - (((uint64_t) arg1 << 32) & 0x00000fff00000000ULL) | - (env->CP0_SAAR[target] & 0x00000000ffffffffULL); - switch (target) { - case 0: - if (env->itu) { - itc_reconfigure(env->itu); - } - break; - } - } -} - -void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1) -{ - target_ulong old, val, mask; - mask =3D (TARGET_PAGE_MASK << 1) | env->CP0_EntryHi_ASID_mask; - if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >=3D 2) { - mask |=3D 1 << CP0EnHi_EHINV; - } - - /* 1k pages not implemented */ -#if defined(TARGET_MIPS64) - if (env->insn_flags & ISA_MIPS32R6) { - int entryhi_r =3D extract64(arg1, 62, 2); - int config0_at =3D extract32(env->CP0_Config0, 13, 2); - bool no_supervisor =3D (env->CP0_Status_rw_bitmask & 0x8) =3D=3D 0; - if ((entryhi_r =3D=3D 2) || - (entryhi_r =3D=3D 1 && (no_supervisor || config0_at =3D=3D 1))= ) { - /* skip EntryHi.R field if new value is reserved */ - mask &=3D ~(0x3ull << 62); - } - } - mask &=3D env->SEGMask; -#endif - old =3D env->CP0_EntryHi; - val =3D (arg1 & mask) | (old & ~mask); - env->CP0_EntryHi =3D val; - if (env->CP0_Config3 & (1 << CP0C3_MT)) { - sync_c0_entryhi(env, env->current_tc); - } - /* If the ASID changes, flush qemu's TLB. */ - if ((old & env->CP0_EntryHi_ASID_mask) !=3D - (val & env->CP0_EntryHi_ASID_mask)) { - tlb_flush(env_cpu(env)); - } -} - -void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - other->CP0_EntryHi =3D arg1; - sync_c0_entryhi(other, other_tc); -} - -void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1) -{ - cpu_mips_store_compare(env, arg1); -} - -void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t val, old; - - old =3D env->CP0_Status; - cpu_mips_store_status(env, arg1); - val =3D env->CP0_Status; - - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log("Status %08x (%08x) =3D> %08x (%08x) Cause %08x", - old, old & env->CP0_Cause & CP0Ca_IP_mask, - val, val & env->CP0_Cause & CP0Ca_IP_mask, - env->CP0_Cause); - switch (cpu_mmu_index(env, false)) { - case 3: - qemu_log(", ERL\n"); - break; - case MIPS_HFLAG_UM: - qemu_log(", UM\n"); - break; - case MIPS_HFLAG_SM: - qemu_log(", SM\n"); - break; - case MIPS_HFLAG_KM: - qemu_log("\n"); - break; - default: - cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); - break; - } - } -} - -void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - uint32_t mask =3D env->CP0_Status_rw_bitmask & ~0xf1000018; - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - other->CP0_Status =3D (other->CP0_Status & ~mask) | (arg1 & mask); - sync_c0_status(env, other, other_tc); -} - -void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_IntCtl =3D (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003= e0); -} - -void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1) -{ - uint32_t mask =3D (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS); - env->CP0_SRSCtl =3D (env->CP0_SRSCtl & ~mask) | (arg1 & mask); -} - -void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1) -{ - cpu_mips_store_cause(env, arg1); -} - -void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - cpu_mips_store_cause(other, arg1); -} - -target_ulong helper_mftc0_epc(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - return other->CP0_EPC; -} - -target_ulong helper_mftc0_ebase(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - return other->CP0_EBase; -} - -void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1) -{ - target_ulong mask =3D 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; - if (arg1 & env->CP0_EBaseWG_rw_bitmask) { - mask |=3D ~0x3FFFFFFF; - } - env->CP0_EBase =3D (env->CP0_EBase & ~mask) | (arg1 & mask); -} - -void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - target_ulong mask =3D 0x3FFFF000 | env->CP0_EBaseWG_rw_bitmask; - if (arg1 & env->CP0_EBaseWG_rw_bitmask) { - mask |=3D ~0x3FFFFFFF; - } - other->CP0_EBase =3D (other->CP0_EBase & ~mask) | (arg1 & mask); -} - -target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - switch (idx) { - case 0: return other->CP0_Config0; - case 1: return other->CP0_Config1; - case 2: return other->CP0_Config2; - case 3: return other->CP0_Config3; - /* 4 and 5 are reserved. */ - case 6: return other->CP0_Config6; - case 7: return other->CP0_Config7; - default: - break; - } - return 0; -} - -void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_Config0 =3D (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000= 007); -} - -void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1) -{ - /* tertiary/secondary caches not implemented */ - env->CP0_Config2 =3D (env->CP0_Config2 & 0x8FFF0FFF); -} - -void helper_mtc0_config3(CPUMIPSState *env, target_ulong arg1) -{ - if (env->insn_flags & ASE_MICROMIPS) { - env->CP0_Config3 =3D (env->CP0_Config3 & ~(1 << CP0C3_ISA_ON_EXC))= | - (arg1 & (1 << CP0C3_ISA_ON_EXC)); - } -} - -void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_Config4 =3D (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask= )) | - (arg1 & env->CP0_Config4_rw_bitmask); -} - -void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_Config5 =3D (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask= )) | - (arg1 & env->CP0_Config5_rw_bitmask); - env->CP0_EntryHi_ASID_mask =3D (env->CP0_Config5 & (1 << CP0C5_MI)) ? - 0x0 : (env->CP0_Config4 & (1 << CP0C4_AE)) ? 0x3ff : 0xff; - compute_hflags(env); -} - -void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1) -{ - target_long mask =3D env->CP0_LLAddr_rw_bitmask; - arg1 =3D arg1 << env->CP0_LLAddr_shift; - env->CP0_LLAddr =3D (env->CP0_LLAddr & ~mask) | (arg1 & mask); -} - -#define MTC0_MAAR_MASK(env) \ - ((0x1ULL << 63) | ((env->PAMask >> 4) & ~0xFFFull) | 0x3) - -void helper_mtc0_maar(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_MAAR[env->CP0_MAARI] =3D arg1 & MTC0_MAAR_MASK(env); -} - -void helper_mthc0_maar(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_MAAR[env->CP0_MAARI] =3D - (((uint64_t) arg1 << 32) & MTC0_MAAR_MASK(env)) | - (env->CP0_MAAR[env->CP0_MAARI] & 0x00000000ffffffffULL); -} - -void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1) -{ - int index =3D arg1 & 0x3f; - if (index =3D=3D 0x3f) { - /* - * Software may write all ones to INDEX to determine the - * maximum value supported. - */ - env->CP0_MAARI =3D MIPS_MAAR_MAX - 1; - } else if (index < MIPS_MAAR_MAX) { - env->CP0_MAARI =3D index; - } - /* - * Other than the all ones, if the value written is not supported, - * then INDEX is unchanged from its previous value. - */ -} - -void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) -{ - /* - * Watch exceptions for instructions, data loads, data stores - * not implemented. - */ - env->CP0_WatchLo[sel] =3D (arg1 & ~0x7); -} - -void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t se= l) -{ - uint64_t mask =3D 0x40000FF8 | (env->CP0_EntryHi_ASID_mask << CP0WH_AS= ID); - if ((env->CP0_Config5 >> CP0C5_MI) & 1) { - mask |=3D 0xFFFFFFFF00000000ULL; /* MMID */ - } - env->CP0_WatchHi[sel] =3D arg1 & mask; - env->CP0_WatchHi[sel] &=3D ~(env->CP0_WatchHi[sel] & arg1 & 0x7); -} - -void helper_mthc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t s= el) -{ - env->CP0_WatchHi[sel] =3D ((uint64_t) (arg1) << 32) | - (env->CP0_WatchHi[sel] & 0x00000000ffffffffULL= ); -} - -void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1) -{ - target_ulong mask =3D (1ULL << (env->SEGBITS - 7)) - 1; - env->CP0_XContext =3D (env->CP0_XContext & mask) | (arg1 & ~mask); -} - -void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_Framemask =3D arg1; /* XXX */ -} - -void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_Debug =3D (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120); - if (arg1 & (1 << CP0DB_DM)) { - env->hflags |=3D MIPS_HFLAG_DM; - } else { - env->hflags &=3D ~MIPS_HFLAG_DM; - } -} - -void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - uint32_t val =3D arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - /* XXX: Might be wrong, check with EJTAG spec. */ - if (other_tc =3D=3D other->current_tc) { - other->active_tc.CP0_Debug_tcstatus =3D val; - } else { - other->tcs[other_tc].CP0_Debug_tcstatus =3D val; - } - other->CP0_Debug =3D (other->CP0_Debug & - ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) | - (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))); -} - -void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_Performance0 =3D arg1 & 0x000007ff; -} - -void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1) -{ - int32_t wst =3D arg1 & (1 << CP0EC_WST); - int32_t spr =3D arg1 & (1 << CP0EC_SPR); - int32_t itc =3D env->itc_tag ? (arg1 & (1 << CP0EC_ITC)) : 0; - - env->CP0_ErrCtl =3D wst | spr | itc; - - if (itc && !wst && !spr) { - env->hflags |=3D MIPS_HFLAG_ITC_CACHE; - } else { - env->hflags &=3D ~MIPS_HFLAG_ITC_CACHE; - } -} - -void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1) -{ - if (env->hflags & MIPS_HFLAG_ITC_CACHE) { - /* - * If CACHE instruction is configured for ITC tags then make all - * CP0.TagLo bits writable. The actual write to ITC Configuration - * Tag will take care of the read-only bits. - */ - env->CP0_TagLo =3D arg1; - } else { - env->CP0_TagLo =3D arg1 & 0xFFFFFCF6; - } -} - -void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_DataLo =3D arg1; /* XXX */ -} - -void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_TagHi =3D arg1; /* XXX */ -} - -void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1) -{ - env->CP0_DataHi =3D arg1; /* XXX */ -} - -/* MIPS MT functions */ -target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.gpr[sel]; - } else { - return other->tcs[other_tc].gpr[sel]; - } -} - -target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.LO[sel]; - } else { - return other->tcs[other_tc].LO[sel]; - } -} - -target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.HI[sel]; - } else { - return other->tcs[other_tc].HI[sel]; - } -} - -target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.ACX[sel]; - } else { - return other->tcs[other_tc].ACX[sel]; - } -} - -target_ulong helper_mftdsp(CPUMIPSState *env) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - return other->active_tc.DSPControl; - } else { - return other->tcs[other_tc].DSPControl; - } -} - -void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.gpr[sel] =3D arg1; - } else { - other->tcs[other_tc].gpr[sel] =3D arg1; - } -} - -void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.LO[sel] =3D arg1; - } else { - other->tcs[other_tc].LO[sel] =3D arg1; - } -} - -void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.HI[sel] =3D arg1; - } else { - other->tcs[other_tc].HI[sel] =3D arg1; - } -} - -void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.ACX[sel] =3D arg1; - } else { - other->tcs[other_tc].ACX[sel] =3D arg1; - } -} - -void helper_mttdsp(CPUMIPSState *env, target_ulong arg1) -{ - int other_tc =3D env->CP0_VPEControl & (0xff << CP0VPECo_TargTC); - CPUMIPSState *other =3D mips_cpu_map_tc(env, &other_tc); - - if (other_tc =3D=3D other->current_tc) { - other->active_tc.DSPControl =3D arg1; - } else { - other->tcs[other_tc].DSPControl =3D arg1; - } -} - -/* MIPS MT functions */ -target_ulong helper_dmt(void) -{ - /* TODO */ - return 0; -} - -target_ulong helper_emt(void) -{ - /* TODO */ - return 0; -} - -target_ulong helper_dvpe(CPUMIPSState *env) -{ - CPUState *other_cs =3D first_cpu; - target_ulong prev =3D env->mvp->CP0_MVPControl; - - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - /* Turn off all VPEs except the one executing the dvpe. */ - if (&other_cpu->env !=3D env) { - other_cpu->env.mvp->CP0_MVPControl &=3D ~(1 << CP0MVPCo_EVP); - mips_vpe_sleep(other_cpu); - } - } - return prev; -} - -target_ulong helper_evpe(CPUMIPSState *env) -{ - CPUState *other_cs =3D first_cpu; - target_ulong prev =3D env->mvp->CP0_MVPControl; - - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - - if (&other_cpu->env !=3D env - /* If the VPE is WFI, don't disturb its sleep. */ - && !mips_vpe_is_wfi(other_cpu)) { - /* Enable the VPE. */ - other_cpu->env.mvp->CP0_MVPControl |=3D (1 << CP0MVPCo_EVP); - mips_vpe_wake(other_cpu); /* And wake it up. */ - } - } - return prev; -} -#endif /* !CONFIG_USER_ONLY */ - -void helper_fork(target_ulong arg1, target_ulong arg2) -{ - /* - * arg1 =3D rt, arg2 =3D rs - * TODO: store to TC register - */ -} - -target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) -{ - target_long arg1 =3D arg; - - if (arg1 < 0) { - /* No scheduling policy implemented. */ - if (arg1 !=3D -2) { - if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && - env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { - env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); - env->CP0_VPEControl |=3D 4 << CP0VPECo_EXCPT; - do_raise_exception(env, EXCP_THREAD, GETPC()); - } - } - } else if (arg1 =3D=3D 0) { - if (0) { - /* TODO: TC underflow */ - env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); - do_raise_exception(env, EXCP_THREAD, GETPC()); - } else { - /* TODO: Deallocate TC */ - } - } else if (arg1 > 0) { - /* Yield qualifier inputs not implemented. */ - env->CP0_VPEControl &=3D ~(0x7 << CP0VPECo_EXCPT); - env->CP0_VPEControl |=3D 2 << CP0VPECo_EXCPT; - do_raise_exception(env, EXCP_THREAD, GETPC()); - } - return env->CP0_YQMask; -} - -/* R6 Multi-threading */ -#ifndef CONFIG_USER_ONLY -target_ulong helper_dvp(CPUMIPSState *env) -{ - CPUState *other_cs =3D first_cpu; - target_ulong prev =3D env->CP0_VPControl; - - if (!((env->CP0_VPControl >> CP0VPCtl_DIS) & 1)) { - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - /* Turn off all VPs except the one executing the dvp. */ - if (&other_cpu->env !=3D env) { - mips_vpe_sleep(other_cpu); - } - } - env->CP0_VPControl |=3D (1 << CP0VPCtl_DIS); - } - return prev; -} - -target_ulong helper_evp(CPUMIPSState *env) -{ - CPUState *other_cs =3D first_cpu; - target_ulong prev =3D env->CP0_VPControl; - - if ((env->CP0_VPControl >> CP0VPCtl_DIS) & 1) { - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu =3D MIPS_CPU(other_cs); - if ((&other_cpu->env !=3D env) && !mips_vp_is_wfi(other_cpu)) { - /* - * If the VP is WFI, don't disturb its sleep. - * Otherwise, wake it up. - */ - mips_vpe_wake(other_cpu); - } - } - env->CP0_VPControl &=3D ~(1 << CP0VPCtl_DIS); - } - return prev; -} -#endif /* !CONFIG_USER_ONLY */ =20 #ifndef CONFIG_USER_ONLY /* TLB management */ --=20 2.7.4 From nobody Fri May 17 10:44:31 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580803569810664.5946971929376; Tue, 4 Feb 2020 00:06:09 -0800 (PST) Received: from localhost ([::1]:54236 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iytDj-0007Hf-JP for importer@patchew.org; Tue, 04 Feb 2020 03:06:07 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38978) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iytAI-0002ri-Jg for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iytA8-0001Dw-Fm for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:34 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:42631 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1iytA4-00014n-GK for qemu-devel@nongnu.org; Tue, 04 Feb 2020 03:02:24 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 30FDD1A152E; Tue, 4 Feb 2020 09:02:18 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id A73AC1A0F0A; Tue, 4 Feb 2020 09:02:17 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PULL v2 3/3] target/mips: Separate FPU-related helpers into their own file Date: Tue, 4 Feb 2020 09:01:57 +0100 Message-Id: <1580803317-4422-4-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1580803317-4422-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1580803317-4422-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, amarkovic@wavecomp.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic For clarity and easier maintenence, create target/mips/fpu_helper.c, and move all FPU-related content form target/mips/op_helper.c to that file. Signed-off-by: Aleksandar Markovic Reviewed-by: Aleksandar Rikalo Message-Id: <1580745443-24650-3-git-send-email-aleksandar.markovic@rt-rk.co= m> --- target/mips/Makefile.objs | 2 +- target/mips/fpu_helper.c | 1911 +++++++++++++++++++++++++++++++++++++++++= ++++ target/mips/op_helper.c | 1877 -----------------------------------------= --- 3 files changed, 1912 insertions(+), 1878 deletions(-) create mode 100644 target/mips/fpu_helper.c diff --git a/target/mips/Makefile.objs b/target/mips/Makefile.objs index 3ca2bde..91eb691 100644 --- a/target/mips/Makefile.objs +++ b/target/mips/Makefile.objs @@ -1,5 +1,5 @@ obj-y +=3D translate.o cpu.o gdbstub.o helper.o -obj-y +=3D op_helper.o cp0_helper.o +obj-y +=3D op_helper.o cp0_helper.o fpu_helper.o obj-y +=3D dsp_helper.o lmi_helper.o msa_helper.o obj-$(CONFIG_SOFTMMU) +=3D mips-semi.o obj-$(CONFIG_SOFTMMU) +=3D machine.o cp0_timer.o diff --git a/target/mips/fpu_helper.c b/target/mips/fpu_helper.c new file mode 100644 index 0000000..5287c86 --- /dev/null +++ b/target/mips/fpu_helper.c @@ -0,0 +1,1911 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * Copyright (C) 2020 Wave Computing, Inc. + * Copyright (C) 2020 Aleksandar Markovic + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + * + */ + +#include "qemu/osdep.h" +#include "qemu/main-loop.h" +#include "cpu.h" +#include "internal.h" +#include "qemu/host-utils.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/cpu_ldst.h" +#include "exec/memop.h" +#include "sysemu/kvm.h" +#include "fpu/softfloat.h" + + +/* Complex FPU operations which may need stack space. */ + +#define FLOAT_TWO32 make_float32(1 << 30) +#define FLOAT_TWO64 make_float64(1ULL << 62) + +#define FP_TO_INT32_OVERFLOW 0x7fffffff +#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +unsigned int ieee_rm[] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; + +target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) +{ + target_ulong arg1 =3D 0; + + switch (reg) { + case 0: + arg1 =3D (int32_t)env->active_fpu.fcr0; + break; + case 1: + /* UFR Support - Read Status FR */ + if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) { + if (env->CP0_Config5 & (1 << CP0C5_UFR)) { + arg1 =3D (int32_t) + ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); + } else { + do_raise_exception(env, EXCP_RI, GETPC()); + } + } + break; + case 5: + /* FRE Support - read Config5.FRE bit */ + if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { + if (env->CP0_Config5 & (1 << CP0C5_UFE)) { + arg1 =3D (env->CP0_Config5 >> CP0C5_FRE) & 1; + } else { + helper_raise_exception(env, EXCP_RI); + } + } + break; + case 25: + arg1 =3D ((env->active_fpu.fcr31 >> 24) & 0xfe) | + ((env->active_fpu.fcr31 >> 23) & 0x1); + break; + case 26: + arg1 =3D env->active_fpu.fcr31 & 0x0003f07c; + break; + case 28: + arg1 =3D (env->active_fpu.fcr31 & 0x00000f83) | + ((env->active_fpu.fcr31 >> 22) & 0x4); + break; + default: + arg1 =3D (int32_t)env->active_fpu.fcr31; + break; + } + + return arg1; +} + +void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32= _t rt) +{ + switch (fs) { + case 1: + /* UFR Alias - Reset Status FR */ + if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt =3D=3D 0)))= { + return; + } + if (env->CP0_Config5 & (1 << CP0C5_UFR)) { + env->CP0_Status &=3D ~(1 << CP0St_FR); + compute_hflags(env); + } else { + do_raise_exception(env, EXCP_RI, GETPC()); + } + break; + case 4: + /* UNFR Alias - Set Status FR */ + if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt =3D=3D 0)))= { + return; + } + if (env->CP0_Config5 & (1 << CP0C5_UFR)) { + env->CP0_Status |=3D (1 << CP0St_FR); + compute_hflags(env); + } else { + do_raise_exception(env, EXCP_RI, GETPC()); + } + break; + case 5: + /* FRE Support - clear Config5.FRE bit */ + if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt =3D=3D 0)))= { + return; + } + if (env->CP0_Config5 & (1 << CP0C5_UFE)) { + env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); + compute_hflags(env); + } else { + helper_raise_exception(env, EXCP_RI); + } + break; + case 6: + /* FRE Support - set Config5.FRE bit */ + if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt =3D=3D 0)))= { + return; + } + if (env->CP0_Config5 & (1 << CP0C5_UFE)) { + env->CP0_Config5 |=3D (1 << CP0C5_FRE); + compute_hflags(env); + } else { + helper_raise_exception(env, EXCP_RI); + } + break; + case 25: + if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { + return; + } + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | + ((arg1 & 0xfe) << 24) | + ((arg1 & 0x1) << 23); + break; + case 26: + if (arg1 & 0x007c0000) { + return; + } + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfffc0f83) | + (arg1 & 0x0003f07c); + break; + case 28: + if (arg1 & 0x007c0000) { + return; + } + env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfefff07c) | + (arg1 & 0x00000f83) | + ((arg1 & 0x4) << 22); + break; + case 31: + env->active_fpu.fcr31 =3D (arg1 & env->active_fpu.fcr31_rw_bitmask= ) | + (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask= )); + break; + default: + if (env->insn_flags & ISA_MIPS32R6) { + do_raise_exception(env, EXCP_RI, GETPC()); + } + return; + } + restore_fp_status(env); + set_float_exception_flags(0, &env->active_fpu.fp_status); + if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & + GET_FP_CAUSE(env->active_fpu.fcr31)) { + do_raise_exception(env, EXCP_FPE, GETPC()); + } +} + +int ieee_ex_to_mips(int xcpt) +{ + int ret =3D 0; + if (xcpt) { + if (xcpt & float_flag_invalid) { + ret |=3D FP_INVALID; + } + if (xcpt & float_flag_overflow) { + ret |=3D FP_OVERFLOW; + } + if (xcpt & float_flag_underflow) { + ret |=3D FP_UNDERFLOW; + } + if (xcpt & float_flag_divbyzero) { + ret |=3D FP_DIV0; + } + if (xcpt & float_flag_inexact) { + ret |=3D FP_INEXACT; + } + } + return ret; +} + +static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) +{ + int tmp =3D ieee_ex_to_mips(get_float_exception_flags( + &env->active_fpu.fp_status)); + + SET_FP_CAUSE(env->active_fpu.fcr31, tmp); + + if (tmp) { + set_float_exception_flags(0, &env->active_fpu.fp_status); + + if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { + do_raise_exception(env, EXCP_FPE, pc); + } else { + UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); + } + } +} + +/* + * Float support. + * Single precition routines have a "s" suffix, double precision a + * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", + * paired single lower "pl", paired single upper "pu". + */ + +/* unary operations, modifying fp status */ +uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) +{ + fdt0 =3D float64_sqrt(fdt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt0; +} + +uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) +{ + fst0 =3D float32_sqrt(fst0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst0; +} + +uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t fdt2; + + fdt2 =3D float32_to_float64(fst0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) +{ + uint64_t fdt2; + + fdt2 =3D int32_to_float64(wt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) +{ + uint64_t fdt2; + + fdt2 =3D int64_to_float64(dt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) +{ + uint32_t fst2; + uint32_t fsth2; + + fst2 =3D int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status= ); + fsth2 =3D int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + uint32_t wth2; + int excp, excph; + + wt2 =3D float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status= ); + excp =3D get_float_exception_flags(&env->active_fpu.fp_status); + if (excp & (float_flag_overflow | float_flag_invalid)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wth2 =3D float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); + excph =3D get_float_exception_flags(&env->active_fpu.fp_status); + if (excph & (float_flag_overflow | float_flag_invalid)) { + wth2 =3D FP_TO_INT32_OVERFLOW; + } + + set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + + return ((uint64_t)wth2 << 32) | wt2; +} + +uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t fst2; + + fst2 =3D float64_to_float32(fdt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst2; +} + +uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) +{ + uint32_t fst2; + + fst2 =3D int32_to_float32(wt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst2; +} + +uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) +{ + uint32_t fst2; + + fst2 =3D int64_to_float32(dt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst2; +} + +uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) +{ + uint32_t wt2; + + wt2 =3D wt0; + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) +{ + uint32_t wt2; + + wt2 =3D wth0; + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + dt2 =3D float64_to_int64_round_to_zero(fdt0, + &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + dt2 =3D float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_statu= s); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + wt2 =3D float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + wt2 =3D float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_statu= s); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + dt2 =3D FP_TO_INT64_OVERFLOW; + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { + wt2 =3D FP_TO_INT32_OVERFLOW; + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_nearest_even, + &env->active_fpu.fp_status); + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + dt2 =3D float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + dt2 =3D float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_statu= s); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + wt2 =3D float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + wt2 =3D float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_statu= s); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0) +{ + uint64_t dt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + dt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return dt2; +} + +uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float64_is_any_nan(fdt0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t wt2; + + set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); + wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); + restore_rounding_mode(env); + if (get_float_exception_flags(&env->active_fpu.fp_status) + & float_flag_invalid) { + if (float32_is_any_nan(fst0)) { + wt2 =3D 0; + } + } + update_fcr31(env, GETPC()); + return wt2; +} + +/* unary operations, not modifying fp status */ +#define FLOAT_UNOP(name) \ +uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ +{ \ + return float64_ ## name(fdt0); \ +} \ +uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ +{ \ + return float32_ ## name(fst0); \ +} \ +uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ +{ \ + uint32_t wt0; \ + uint32_t wth0; \ + \ + wt0 =3D float32_ ## name(fdt0 & 0XFFFFFFFF); \ + wth0 =3D float32_ ## name(fdt0 >> 32); \ + return ((uint64_t)wth0 << 32) | wt0; \ +} +FLOAT_UNOP(abs) +FLOAT_UNOP(chs) +#undef FLOAT_UNOP + +/* MIPS specific unary operations */ +uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t fdt2; + + fdt2 =3D float64_div(float64_one, fdt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t fst2; + + fst2 =3D float32_div(float32_one, fst0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst2; +} + +uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t fdt2; + + fdt2 =3D float64_sqrt(fdt0, &env->active_fpu.fp_status); + fdt2 =3D float64_div(float64_one, fdt2, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t fst2; + + fst2 =3D float32_sqrt(fst0, &env->active_fpu.fp_status); + fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst2; +} + +uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t fdt2; + + fdt2 =3D float64_div(float64_one, fdt0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t fst2; + + fst2 =3D float32_div(float32_one, fst0, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst2; +} + +uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t fst2; + uint32_t fsth2; + + fst2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, + &env->active_fpu.fp_status); + fsth2 =3D float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_sta= tus); + update_fcr31(env, GETPC()); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) +{ + uint64_t fdt2; + + fdt2 =3D float64_sqrt(fdt0, &env->active_fpu.fp_status); + fdt2 =3D float64_div(float64_one, fdt2, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) +{ + uint32_t fst2; + + fst2 =3D float32_sqrt(fst0, &env->active_fpu.fp_status); + fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return fst2; +} + +uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) +{ + uint32_t fst2; + uint32_t fsth2; + + fst2 =3D float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 =3D float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); + fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); + fsth2 =3D float32_div(float32_one, fsth2, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)fsth2 << 32) | fst2; +} + +#define FLOAT_RINT(name, bits) = \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, = \ + uint ## bits ## _t fs) = \ +{ = \ + uint ## bits ## _t fdret; = \ + = \ + fdret =3D float ## bits ## _round_to_int(fs, &env->active_fpu.fp_statu= s); \ + update_fcr31(env, GETPC()); = \ + return fdret; = \ +} + +FLOAT_RINT(rint_s, 32) +FLOAT_RINT(rint_d, 64) +#undef FLOAT_RINT + +#define FLOAT_CLASS_SIGNALING_NAN 0x001 +#define FLOAT_CLASS_QUIET_NAN 0x002 +#define FLOAT_CLASS_NEGATIVE_INFINITY 0x004 +#define FLOAT_CLASS_NEGATIVE_NORMAL 0x008 +#define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010 +#define FLOAT_CLASS_NEGATIVE_ZERO 0x020 +#define FLOAT_CLASS_POSITIVE_INFINITY 0x040 +#define FLOAT_CLASS_POSITIVE_NORMAL 0x080 +#define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100 +#define FLOAT_CLASS_POSITIVE_ZERO 0x200 + +#define FLOAT_CLASS(name, bits) \ +uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \ + float_status *status) \ +{ \ + if (float ## bits ## _is_signaling_nan(arg, status)) { \ + return FLOAT_CLASS_SIGNALING_NAN; \ + } else if (float ## bits ## _is_quiet_nan(arg, status)) { \ + return FLOAT_CLASS_QUIET_NAN; \ + } else if (float ## bits ## _is_neg(arg)) { \ + if (float ## bits ## _is_infinity(arg)) { \ + return FLOAT_CLASS_NEGATIVE_INFINITY; \ + } else if (float ## bits ## _is_zero(arg)) { \ + return FLOAT_CLASS_NEGATIVE_ZERO; \ + } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ + return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \ + } else { \ + return FLOAT_CLASS_NEGATIVE_NORMAL; \ + } \ + } else { \ + if (float ## bits ## _is_infinity(arg)) { \ + return FLOAT_CLASS_POSITIVE_INFINITY; \ + } else if (float ## bits ## _is_zero(arg)) { \ + return FLOAT_CLASS_POSITIVE_ZERO; \ + } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ + return FLOAT_CLASS_POSITIVE_SUBNORMAL; \ + } else { \ + return FLOAT_CLASS_POSITIVE_NORMAL; \ + } \ + } \ +} \ + \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t arg) \ +{ \ + return float_ ## name(arg, &env->active_fpu.fp_status); \ +} + +FLOAT_CLASS(class_s, 32) +FLOAT_CLASS(class_d, 64) +#undef FLOAT_CLASS + +/* binary operations */ +#define FLOAT_BINOP(name) \ +uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ + uint64_t fdt0, uint64_t fdt1) \ +{ \ + uint64_t dt2; \ + \ + dt2 =3D float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\ + update_fcr31(env, GETPC()); \ + return dt2; \ +} \ + \ +uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ + uint32_t fst0, uint32_t fst1) \ +{ \ + uint32_t wt2; \ + \ + wt2 =3D float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\ + update_fcr31(env, GETPC()); \ + return wt2; \ +} \ + \ +uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, \ + uint64_t fdt1) \ +{ \ + uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 =3D fdt0 >> 32; \ + uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 =3D fdt1 >> 32; \ + uint32_t wt2; \ + uint32_t wth2; \ + \ + wt2 =3D float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \ + wth2 =3D float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \ + update_fcr31(env, GETPC()); \ + return ((uint64_t)wth2 << 32) | wt2; \ +} + +FLOAT_BINOP(add) +FLOAT_BINOP(sub) +FLOAT_BINOP(mul) +FLOAT_BINOP(div) +#undef FLOAT_BINOP + +/* MIPS specific binary operations */ +uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t = fdt2) +{ + fdt2 =3D float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); + fdt2 =3D float64_chs(float64_sub(fdt2, float64_one, + &env->active_fpu.fp_status)); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t = fst2) +{ + fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fst2 =3D float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); + update_fcr31(env, GETPC()); + return fst2; +} + +uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) +{ + uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fsth0 =3D fdt0 >> 32; + uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; + uint32_t fsth2 =3D fdt2 >> 32; + + fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); + fst2 =3D float32_chs(float32_sub(fst2, float32_one, + &env->active_fpu.fp_status)); + fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, + &env->active_fpu.fp_status)); + update_fcr31(env, GETPC()); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t = fdt2) +{ + fdt2 =3D float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); + fdt2 =3D float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); + fdt2 =3D float64_chs(float64_div(fdt2, FLOAT_TWO64, + &env->active_fpu.fp_status)); + update_fcr31(env, GETPC()); + return fdt2; +} + +uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t = fst2) +{ + fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); + fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); + update_fcr31(env, GETPC()); + return fst2; +} + +uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) +{ + uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fsth0 =3D fdt0 >> 32; + uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; + uint32_t fsth2 =3D fdt2 >> 32; + + fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); + fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); + fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); + fsth2 =3D float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); + fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, + &env->active_fpu.fp_status)); + fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, + &env->active_fpu.fp_status)); + update_fcr31(env, GETPC()); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) +{ + uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fsth0 =3D fdt0 >> 32; + uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; + uint32_t fsth1 =3D fdt1 >> 32; + uint32_t fst2; + uint32_t fsth2; + + fst2 =3D float32_add(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_add(fst1, fsth1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)fsth2 << 32) | fst2; +} + +uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) +{ + uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; + uint32_t fsth0 =3D fdt0 >> 32; + uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; + uint32_t fsth1 =3D fdt1 >> 32; + uint32_t fst2; + uint32_t fsth2; + + fst2 =3D float32_mul(fst0, fsth0, &env->active_fpu.fp_status); + fsth2 =3D float32_mul(fst1, fsth1, &env->active_fpu.fp_status); + update_fcr31(env, GETPC()); + return ((uint64_t)fsth2 << 32) | fst2; +} + +#define FLOAT_MINMAX(name, bits, minmaxfunc) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t fs, \ + uint ## bits ## _t ft) \ +{ \ + uint ## bits ## _t fdret; \ + \ + fdret =3D float ## bits ## _ ## minmaxfunc(fs, ft, \ + &env->active_fpu.fp_status); \ + update_fcr31(env, GETPC()); \ + return fdret; \ +} + +FLOAT_MINMAX(max_s, 32, maxnum) +FLOAT_MINMAX(max_d, 64, maxnum) +FLOAT_MINMAX(maxa_s, 32, maxnummag) +FLOAT_MINMAX(maxa_d, 64, maxnummag) + +FLOAT_MINMAX(min_s, 32, minnum) +FLOAT_MINMAX(min_d, 64, minnum) +FLOAT_MINMAX(mina_s, 32, minnummag) +FLOAT_MINMAX(mina_d, 64, minnummag) +#undef FLOAT_MINMAX + +/* ternary operations */ +#define UNFUSED_FMA(prefix, a, b, c, flags) \ +{ \ + a =3D prefix##_mul(a, b, &env->active_fpu.fp_status); \ + if ((flags) & float_muladd_negate_c) { \ + a =3D prefix##_sub(a, c, &env->active_fpu.fp_status); \ + } else { \ + a =3D prefix##_add(a, c, &env->active_fpu.fp_status); \ + } \ + if ((flags) & float_muladd_negate_result) { \ + a =3D prefix##_chs(a); \ + } \ +} + +/* FMA based operations */ +#define FLOAT_FMA(name, type) \ +uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ + uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \ + update_fcr31(env, GETPC()); \ + return fdt0; \ +} \ + \ +uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ + uint32_t fst0, uint32_t fst1, \ + uint32_t fst2) \ +{ \ + UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ + update_fcr31(env, GETPC()); \ + return fst0; \ +} \ + \ +uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 =3D fdt0 >> 32; \ + uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 =3D fdt1 >> 32; \ + uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; \ + uint32_t fsth2 =3D fdt2 >> 32; \ + \ + UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ + UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \ + update_fcr31(env, GETPC()); \ + return ((uint64_t)fsth0 << 32) | fst0; \ +} +FLOAT_FMA(madd, 0) +FLOAT_FMA(msub, float_muladd_negate_c) +FLOAT_FMA(nmadd, float_muladd_negate_result) +FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) +#undef FLOAT_FMA + +#define FLOAT_FMADDSUB(name, bits, muladd_arg) \ +uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ + uint ## bits ## _t fs, \ + uint ## bits ## _t ft, \ + uint ## bits ## _t fd) \ +{ \ + uint ## bits ## _t fdret; \ + \ + fdret =3D float ## bits ## _muladd(fs, ft, fd, muladd_arg, \ + &env->active_fpu.fp_status); \ + update_fcr31(env, GETPC()); \ + return fdret; \ +} + +FLOAT_FMADDSUB(maddf_s, 32, 0) +FLOAT_FMADDSUB(maddf_d, 64, 0) +FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product) +FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product) +#undef FLOAT_FMADDSUB + +/* compare operations */ +#define FOP_COND_D(op, cond) \ +void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ +{ \ + int c; \ + c =3D cond; \ + update_fcr31(env, GETPC()); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} \ +void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ +{ \ + int c; \ + fdt0 =3D float64_abs(fdt0); \ + fdt1 =3D float64_abs(fdt1); \ + c =3D cond; \ + update_fcr31(env, GETPC()); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} + +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called. + */ +FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_COND_D(ngle, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status)) +FOP_COND_D(seq, float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(lt, float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(nge, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(le, float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) +FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status)) + +#define FOP_COND_S(op, cond) \ +void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1, int cc) \ +{ \ + int c; \ + c =3D cond; \ + update_fcr31(env, GETPC()); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} \ +void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1, int cc) \ +{ \ + int c; \ + fst0 =3D float32_abs(fst0); \ + fst1 =3D float32_abs(fst1); \ + c =3D cond; \ + update_fcr31(env, GETPC()); \ + if (c) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ +} + +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_S(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_COND_S(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status)) +FOP_COND_S(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status)) +FOP_COND_S(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status)) + +#define FOP_COND_PS(op, condl, condh) \ +void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ +{ \ + uint32_t fst0, fsth0, fst1, fsth1; \ + int ch, cl; \ + fst0 =3D fdt0 & 0XFFFFFFFF; \ + fsth0 =3D fdt0 >> 32; \ + fst1 =3D fdt1 & 0XFFFFFFFF; \ + fsth1 =3D fdt1 >> 32; \ + cl =3D condl; \ + ch =3D condh; \ + update_fcr31(env, GETPC()); \ + if (cl) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ + if (ch) \ + SET_FP_COND(cc + 1, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc + 1, env->active_fpu); \ +} \ +void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1, int cc) \ +{ \ + uint32_t fst0, fsth0, fst1, fsth1; \ + int ch, cl; \ + fst0 =3D float32_abs(fdt0 & 0XFFFFFFFF); \ + fsth0 =3D float32_abs(fdt0 >> 32); \ + fst1 =3D float32_abs(fdt1 & 0XFFFFFFFF); \ + fsth1 =3D float32_abs(fdt1 >> 32); \ + cl =3D condl; \ + ch =3D condh; \ + update_fcr31(env, GETPC()); \ + if (cl) \ + SET_FP_COND(cc, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc, env->active_fpu); \ + if (ch) \ + SET_FP_COND(cc + 1, env->active_fpu); \ + else \ + CLEAR_FP_COND(cc + 1, env->active_fpu); \ +} + +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered_quiet(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le_quiet(fsth0, fsth1, + &env->active_fpu.fp_status)) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_COND_PS(sf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0), + (float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status), 0)) +FOP_COND_PS(ngle, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status)) +FOP_COND_PS(seq, float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngl, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_eq(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(lt, float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(nge, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_lt(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(le, float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) +FOP_COND_PS(ngt, float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status), + float32_unordered(fsth1, fsth0, + &env->active_fpu.fp_status) + || float32_le(fsth0, fsth1, + &env->active_fpu.fp_status)) + +/* R6 compare operations */ +#define FOP_CONDN_D(op, cond) \ +uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ + uint64_t fdt1) \ +{ \ + uint64_t c; \ + c =3D cond; \ + update_fcr31(env, GETPC()); \ + if (c) { \ + return -1; \ + } else { \ + return 0; \ + } \ +} + +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered_quiet() is still called. + */ +FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float64_unordered() is still called.\ + */ +FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status))) +FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_eq(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt_quiet(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_le(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) +FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, + &env->active_fpu.fp_status) + || float64_lt(fdt0, fdt1, + &env->active_fpu.fp_status))) + +#define FOP_CONDN_S(op, cond) \ +uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ + uint32_t fst1) \ +{ \ + uint64_t c; \ + c =3D cond; \ + update_fcr31(env, GETPC()); \ + if (c) { \ + return -1; \ + } else { \ + return 0; \ + } \ +} + +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered_quiet() is still called. + */ +FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +/* + * NOTE: the comma operator will make "cond" to eval to false, + * but float32_unordered() is still called. + */ +FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status), 0)) +FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status))) +FOP_CONDN_S(seq, (float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_eq(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(slt, (float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sle, (float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt_quiet(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sor, (float32_le(fst1, fst0, + &env->active_fpu.fp_status) + || float32_le(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) +FOP_CONDN_S(sne, (float32_lt(fst1, fst0, + &env->active_fpu.fp_status) + || float32_lt(fst0, fst1, + &env->active_fpu.fp_status))) diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 27c3963..9552b28 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -28,7 +28,6 @@ #include "exec/cpu_ldst.h" #include "exec/memop.h" #include "sysemu/kvm.h" -#include "fpu/softfloat.h" =20 =20 /*************************************************************************= ****/ @@ -1178,1882 +1177,6 @@ void mips_cpu_do_transaction_failed(CPUState *cs, = hwaddr physaddr, } #endif /* !CONFIG_USER_ONLY */ =20 -/* Complex FPU operations which may need stack space. */ - -#define FLOAT_TWO32 make_float32(1 << 30) -#define FLOAT_TWO64 make_float64(1ULL << 62) - -#define FP_TO_INT32_OVERFLOW 0x7fffffff -#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL - -/* convert MIPS rounding mode in FCR31 to IEEE library */ -unsigned int ieee_rm[] =3D { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - -target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) -{ - target_ulong arg1 =3D 0; - - switch (reg) { - case 0: - arg1 =3D (int32_t)env->active_fpu.fcr0; - break; - case 1: - /* UFR Support - Read Status FR */ - if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) { - if (env->CP0_Config5 & (1 << CP0C5_UFR)) { - arg1 =3D (int32_t) - ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); - } else { - do_raise_exception(env, EXCP_RI, GETPC()); - } - } - break; - case 5: - /* FRE Support - read Config5.FRE bit */ - if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) { - if (env->CP0_Config5 & (1 << CP0C5_UFE)) { - arg1 =3D (env->CP0_Config5 >> CP0C5_FRE) & 1; - } else { - helper_raise_exception(env, EXCP_RI); - } - } - break; - case 25: - arg1 =3D ((env->active_fpu.fcr31 >> 24) & 0xfe) | - ((env->active_fpu.fcr31 >> 23) & 0x1); - break; - case 26: - arg1 =3D env->active_fpu.fcr31 & 0x0003f07c; - break; - case 28: - arg1 =3D (env->active_fpu.fcr31 & 0x00000f83) | - ((env->active_fpu.fcr31 >> 22) & 0x4); - break; - default: - arg1 =3D (int32_t)env->active_fpu.fcr31; - break; - } - - return arg1; -} - -void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32= _t rt) -{ - switch (fs) { - case 1: - /* UFR Alias - Reset Status FR */ - if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt =3D=3D 0)))= { - return; - } - if (env->CP0_Config5 & (1 << CP0C5_UFR)) { - env->CP0_Status &=3D ~(1 << CP0St_FR); - compute_hflags(env); - } else { - do_raise_exception(env, EXCP_RI, GETPC()); - } - break; - case 4: - /* UNFR Alias - Set Status FR */ - if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt =3D=3D 0)))= { - return; - } - if (env->CP0_Config5 & (1 << CP0C5_UFR)) { - env->CP0_Status |=3D (1 << CP0St_FR); - compute_hflags(env); - } else { - do_raise_exception(env, EXCP_RI, GETPC()); - } - break; - case 5: - /* FRE Support - clear Config5.FRE bit */ - if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt =3D=3D 0)))= { - return; - } - if (env->CP0_Config5 & (1 << CP0C5_UFE)) { - env->CP0_Config5 &=3D ~(1 << CP0C5_FRE); - compute_hflags(env); - } else { - helper_raise_exception(env, EXCP_RI); - } - break; - case 6: - /* FRE Support - set Config5.FRE bit */ - if (!((env->active_fpu.fcr0 & (1 << FCR0_FREP)) && (rt =3D=3D 0)))= { - return; - } - if (env->CP0_Config5 & (1 << CP0C5_UFE)) { - env->CP0_Config5 |=3D (1 << CP0C5_FRE); - compute_hflags(env); - } else { - helper_raise_exception(env, EXCP_RI); - } - break; - case 25: - if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) { - return; - } - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0x017fffff) | - ((arg1 & 0xfe) << 24) | - ((arg1 & 0x1) << 23); - break; - case 26: - if (arg1 & 0x007c0000) { - return; - } - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfffc0f83) | - (arg1 & 0x0003f07c); - break; - case 28: - if (arg1 & 0x007c0000) { - return; - } - env->active_fpu.fcr31 =3D (env->active_fpu.fcr31 & 0xfefff07c) | - (arg1 & 0x00000f83) | - ((arg1 & 0x4) << 22); - break; - case 31: - env->active_fpu.fcr31 =3D (arg1 & env->active_fpu.fcr31_rw_bitmask= ) | - (env->active_fpu.fcr31 & ~(env->active_fpu.fcr31_rw_bitmask= )); - break; - default: - if (env->insn_flags & ISA_MIPS32R6) { - do_raise_exception(env, EXCP_RI, GETPC()); - } - return; - } - restore_fp_status(env); - set_float_exception_flags(0, &env->active_fpu.fp_status); - if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & - GET_FP_CAUSE(env->active_fpu.fcr31)) { - do_raise_exception(env, EXCP_FPE, GETPC()); - } -} - -int ieee_ex_to_mips(int xcpt) -{ - int ret =3D 0; - if (xcpt) { - if (xcpt & float_flag_invalid) { - ret |=3D FP_INVALID; - } - if (xcpt & float_flag_overflow) { - ret |=3D FP_OVERFLOW; - } - if (xcpt & float_flag_underflow) { - ret |=3D FP_UNDERFLOW; - } - if (xcpt & float_flag_divbyzero) { - ret |=3D FP_DIV0; - } - if (xcpt & float_flag_inexact) { - ret |=3D FP_INEXACT; - } - } - return ret; -} - -static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) -{ - int tmp =3D ieee_ex_to_mips(get_float_exception_flags( - &env->active_fpu.fp_status)); - - SET_FP_CAUSE(env->active_fpu.fcr31, tmp); - - if (tmp) { - set_float_exception_flags(0, &env->active_fpu.fp_status); - - if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { - do_raise_exception(env, EXCP_FPE, pc); - } else { - UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); - } - } -} - -/* - * Float support. - * Single precition routines have a "s" suffix, double precision a - * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps", - * paired single lower "pl", paired single upper "pu". - */ - -/* unary operations, modifying fp status */ -uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) -{ - fdt0 =3D float64_sqrt(fdt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt0; -} - -uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) -{ - fst0 =3D float32_sqrt(fst0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst0; -} - -uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t fdt2; - - fdt2 =3D float32_to_float64(fst0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) -{ - uint64_t fdt2; - - fdt2 =3D int32_to_float64(wt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) -{ - uint64_t fdt2; - - fdt2 =3D int64_to_float64(dt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint64_t helper_float_cvt_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_cvt_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) -{ - uint32_t fst2; - uint32_t fsth2; - - fst2 =3D int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status= ); - fsth2 =3D int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; -} - -uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - uint32_t wth2; - int excp, excph; - - wt2 =3D float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status= ); - excp =3D get_float_exception_flags(&env->active_fpu.fp_status); - if (excp & (float_flag_overflow | float_flag_invalid)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - - set_float_exception_flags(0, &env->active_fpu.fp_status); - wth2 =3D float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); - excph =3D get_float_exception_flags(&env->active_fpu.fp_status); - if (excph & (float_flag_overflow | float_flag_invalid)) { - wth2 =3D FP_TO_INT32_OVERFLOW; - } - - set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - - return ((uint64_t)wth2 << 32) | wt2; -} - -uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t fst2; - - fst2 =3D float64_to_float32(fdt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst2; -} - -uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) -{ - uint32_t fst2; - - fst2 =3D int32_to_float32(wt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst2; -} - -uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) -{ - uint32_t fst2; - - fst2 =3D int64_to_float32(dt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst2; -} - -uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) -{ - uint32_t wt2; - - wt2 =3D wt0; - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) -{ - uint32_t wt2; - - wt2 =3D wth0; - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_cvt_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_cvt_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - dt2 =3D float64_to_int64_round_to_zero(fdt0, - &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_trunc_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - dt2 =3D float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_statu= s); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_trunc_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - wt2 =3D float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_trunc_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - wt2 =3D float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_statu= s); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_ceil_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_ceil_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_ceil_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_ceil_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_floor_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_floor_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - dt2 =3D FP_TO_INT64_OVERFLOW; - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_floor_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_floor_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & (float_flag_invalid | float_flag_overflow)) { - wt2 =3D FP_TO_INT32_OVERFLOW; - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_cvt_2008_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_cvt_2008_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_cvt_2008_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_cvt_2008_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_round_2008_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_round_2008_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_round_2008_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_round_2008_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_nearest_even, - &env->active_fpu.fp_status); - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_trunc_2008_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - dt2 =3D float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_trunc_2008_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - dt2 =3D float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_statu= s); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_trunc_2008_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - wt2 =3D float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_statu= s); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_trunc_2008_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - wt2 =3D float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_statu= s); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_ceil_2008_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_ceil_2008_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_ceil_2008_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_ceil_2008_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint64_t helper_float_floor_2008_l_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - dt2 =3D float64_to_int64(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint64_t helper_float_floor_2008_l_s(CPUMIPSState *env, uint32_t fst0) -{ - uint64_t dt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - dt2 =3D float32_to_int64(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - dt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return dt2; -} - -uint32_t helper_float_floor_2008_w_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - wt2 =3D float64_to_int32(fdt0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float64_is_any_nan(fdt0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -uint32_t helper_float_floor_2008_w_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t wt2; - - set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); - wt2 =3D float32_to_int32(fst0, &env->active_fpu.fp_status); - restore_rounding_mode(env); - if (get_float_exception_flags(&env->active_fpu.fp_status) - & float_flag_invalid) { - if (float32_is_any_nan(fst0)) { - wt2 =3D 0; - } - } - update_fcr31(env, GETPC()); - return wt2; -} - -/* unary operations, not modifying fp status */ -#define FLOAT_UNOP(name) \ -uint64_t helper_float_ ## name ## _d(uint64_t fdt0) \ -{ \ - return float64_ ## name(fdt0); \ -} \ -uint32_t helper_float_ ## name ## _s(uint32_t fst0) \ -{ \ - return float32_ ## name(fst0); \ -} \ -uint64_t helper_float_ ## name ## _ps(uint64_t fdt0) \ -{ \ - uint32_t wt0; \ - uint32_t wth0; \ - \ - wt0 =3D float32_ ## name(fdt0 & 0XFFFFFFFF); \ - wth0 =3D float32_ ## name(fdt0 >> 32); \ - return ((uint64_t)wth0 << 32) | wt0; \ -} -FLOAT_UNOP(abs) -FLOAT_UNOP(chs) -#undef FLOAT_UNOP - -/* MIPS specific unary operations */ -uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t fdt2; - - fdt2 =3D float64_div(float64_one, fdt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t fst2; - - fst2 =3D float32_div(float32_one, fst0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst2; -} - -uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t fdt2; - - fdt2 =3D float64_sqrt(fdt0, &env->active_fpu.fp_status); - fdt2 =3D float64_div(float64_one, fdt2, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t fst2; - - fst2 =3D float32_sqrt(fst0, &env->active_fpu.fp_status); - fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst2; -} - -uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t fdt2; - - fdt2 =3D float64_div(float64_one, fdt0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t fst2; - - fst2 =3D float32_div(float32_one, fst0, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst2; -} - -uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t fst2; - uint32_t fsth2; - - fst2 =3D float32_div(float32_one, fdt0 & 0XFFFFFFFF, - &env->active_fpu.fp_status); - fsth2 =3D float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_sta= tus); - update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; -} - -uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) -{ - uint64_t fdt2; - - fdt2 =3D float64_sqrt(fdt0, &env->active_fpu.fp_status); - fdt2 =3D float64_div(float64_one, fdt2, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) -{ - uint32_t fst2; - - fst2 =3D float32_sqrt(fst0, &env->active_fpu.fp_status); - fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return fst2; -} - -uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) -{ - uint32_t fst2; - uint32_t fsth2; - - fst2 =3D float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); - fsth2 =3D float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); - fst2 =3D float32_div(float32_one, fst2, &env->active_fpu.fp_status); - fsth2 =3D float32_div(float32_one, fsth2, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; -} - -#define FLOAT_RINT(name, bits) = \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, = \ - uint ## bits ## _t fs) = \ -{ = \ - uint ## bits ## _t fdret; = \ - = \ - fdret =3D float ## bits ## _round_to_int(fs, &env->active_fpu.fp_statu= s); \ - update_fcr31(env, GETPC()); = \ - return fdret; = \ -} - -FLOAT_RINT(rint_s, 32) -FLOAT_RINT(rint_d, 64) -#undef FLOAT_RINT - -#define FLOAT_CLASS_SIGNALING_NAN 0x001 -#define FLOAT_CLASS_QUIET_NAN 0x002 -#define FLOAT_CLASS_NEGATIVE_INFINITY 0x004 -#define FLOAT_CLASS_NEGATIVE_NORMAL 0x008 -#define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010 -#define FLOAT_CLASS_NEGATIVE_ZERO 0x020 -#define FLOAT_CLASS_POSITIVE_INFINITY 0x040 -#define FLOAT_CLASS_POSITIVE_NORMAL 0x080 -#define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100 -#define FLOAT_CLASS_POSITIVE_ZERO 0x200 - -#define FLOAT_CLASS(name, bits) \ -uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \ - float_status *status) \ -{ \ - if (float ## bits ## _is_signaling_nan(arg, status)) { \ - return FLOAT_CLASS_SIGNALING_NAN; \ - } else if (float ## bits ## _is_quiet_nan(arg, status)) { \ - return FLOAT_CLASS_QUIET_NAN; \ - } else if (float ## bits ## _is_neg(arg)) { \ - if (float ## bits ## _is_infinity(arg)) { \ - return FLOAT_CLASS_NEGATIVE_INFINITY; \ - } else if (float ## bits ## _is_zero(arg)) { \ - return FLOAT_CLASS_NEGATIVE_ZERO; \ - } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ - return FLOAT_CLASS_NEGATIVE_SUBNORMAL; \ - } else { \ - return FLOAT_CLASS_NEGATIVE_NORMAL; \ - } \ - } else { \ - if (float ## bits ## _is_infinity(arg)) { \ - return FLOAT_CLASS_POSITIVE_INFINITY; \ - } else if (float ## bits ## _is_zero(arg)) { \ - return FLOAT_CLASS_POSITIVE_ZERO; \ - } else if (float ## bits ## _is_zero_or_denormal(arg)) { \ - return FLOAT_CLASS_POSITIVE_SUBNORMAL; \ - } else { \ - return FLOAT_CLASS_POSITIVE_NORMAL; \ - } \ - } \ -} \ - \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ - uint ## bits ## _t arg) \ -{ \ - return float_ ## name(arg, &env->active_fpu.fp_status); \ -} - -FLOAT_CLASS(class_s, 32) -FLOAT_CLASS(class_d, 64) -#undef FLOAT_CLASS - -/* binary operations */ -#define FLOAT_BINOP(name) \ -uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ - uint64_t fdt0, uint64_t fdt1) \ -{ \ - uint64_t dt2; \ - \ - dt2 =3D float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\ - update_fcr31(env, GETPC()); \ - return dt2; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ - uint32_t fst0, uint32_t fst1) \ -{ \ - uint32_t wt2; \ - \ - wt2 =3D float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\ - update_fcr31(env, GETPC()); \ - return wt2; \ -} \ - \ -uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ - uint64_t fdt0, \ - uint64_t fdt1) \ -{ \ - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; \ - uint32_t fsth0 =3D fdt0 >> 32; \ - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; \ - uint32_t fsth1 =3D fdt1 >> 32; \ - uint32_t wt2; \ - uint32_t wth2; \ - \ - wt2 =3D float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \ - wth2 =3D float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \ - update_fcr31(env, GETPC()); \ - return ((uint64_t)wth2 << 32) | wt2; \ -} - -FLOAT_BINOP(add) -FLOAT_BINOP(sub) -FLOAT_BINOP(mul) -FLOAT_BINOP(div) -#undef FLOAT_BINOP - -/* MIPS specific binary operations */ -uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t = fdt2) -{ - fdt2 =3D float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 =3D float64_chs(float64_sub(fdt2, float64_one, - &env->active_fpu.fp_status)); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t = fst2) -{ - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, - &env->active_fpu.fp_status)); - update_fcr31(env, GETPC()); - return fst2; -} - -uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) -{ - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; - uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; - uint32_t fsth2 =3D fdt2 >> 32; - - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_sub(fst2, float32_one, - &env->active_fpu.fp_status)); - fsth2 =3D float32_chs(float32_sub(fsth2, float32_one, - &env->active_fpu.fp_status)); - update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; -} - -uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t = fdt2) -{ - fdt2 =3D float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 =3D float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); - fdt2 =3D float64_chs(float64_div(fdt2, FLOAT_TWO64, - &env->active_fpu.fp_status)); - update_fcr31(env, GETPC()); - return fdt2; -} - -uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t = fst2) -{ - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, - &env->active_fpu.fp_status)); - update_fcr31(env, GETPC()); - return fst2; -} - -uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t= fdt2) -{ - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; - uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; - uint32_t fsth2 =3D fdt2 >> 32; - - fst2 =3D float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fsth2 =3D float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 =3D float32_sub(fst2, float32_one, &env->active_fpu.fp_status); - fsth2 =3D float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); - fst2 =3D float32_chs(float32_div(fst2, FLOAT_TWO32, - &env->active_fpu.fp_status)); - fsth2 =3D float32_chs(float32_div(fsth2, FLOAT_TWO32, - &env->active_fpu.fp_status)); - update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; -} - -uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) -{ - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; - uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; - uint32_t fsth1 =3D fdt1 >> 32; - uint32_t fst2; - uint32_t fsth2; - - fst2 =3D float32_add(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_add(fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; -} - -uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t f= dt1) -{ - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; - uint32_t fsth0 =3D fdt0 >> 32; - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; - uint32_t fsth1 =3D fdt1 >> 32; - uint32_t fst2; - uint32_t fsth2; - - fst2 =3D float32_mul(fst0, fsth0, &env->active_fpu.fp_status); - fsth2 =3D float32_mul(fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(env, GETPC()); - return ((uint64_t)fsth2 << 32) | fst2; -} - -#define FLOAT_MINMAX(name, bits, minmaxfunc) \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft) \ -{ \ - uint ## bits ## _t fdret; \ - \ - fdret =3D float ## bits ## _ ## minmaxfunc(fs, ft, \ - &env->active_fpu.fp_status); \ - update_fcr31(env, GETPC()); \ - return fdret; \ -} - -FLOAT_MINMAX(max_s, 32, maxnum) -FLOAT_MINMAX(max_d, 64, maxnum) -FLOAT_MINMAX(maxa_s, 32, maxnummag) -FLOAT_MINMAX(maxa_d, 64, maxnummag) - -FLOAT_MINMAX(min_s, 32, minnum) -FLOAT_MINMAX(min_d, 64, minnum) -FLOAT_MINMAX(mina_s, 32, minnummag) -FLOAT_MINMAX(mina_d, 64, minnummag) -#undef FLOAT_MINMAX - -/* ternary operations */ -#define UNFUSED_FMA(prefix, a, b, c, flags) \ -{ \ - a =3D prefix##_mul(a, b, &env->active_fpu.fp_status); \ - if ((flags) & float_muladd_negate_c) { \ - a =3D prefix##_sub(a, c, &env->active_fpu.fp_status); \ - } else { \ - a =3D prefix##_add(a, c, &env->active_fpu.fp_status); \ - } \ - if ((flags) & float_muladd_negate_result) { \ - a =3D prefix##_chs(a); \ - } \ -} - -/* FMA based operations */ -#define FLOAT_FMA(name, type) \ -uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ - uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type); \ - update_fcr31(env, GETPC()); \ - return fdt0; \ -} \ - \ -uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ - uint32_t fst0, uint32_t fst1, \ - uint32_t fst2) \ -{ \ - UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ - update_fcr31(env, GETPC()); \ - return fst0; \ -} \ - \ -uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ - uint64_t fdt0, uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - uint32_t fst0 =3D fdt0 & 0XFFFFFFFF; \ - uint32_t fsth0 =3D fdt0 >> 32; \ - uint32_t fst1 =3D fdt1 & 0XFFFFFFFF; \ - uint32_t fsth1 =3D fdt1 >> 32; \ - uint32_t fst2 =3D fdt2 & 0XFFFFFFFF; \ - uint32_t fsth2 =3D fdt2 >> 32; \ - \ - UNFUSED_FMA(float32, fst0, fst1, fst2, type); \ - UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type); \ - update_fcr31(env, GETPC()); \ - return ((uint64_t)fsth0 << 32) | fst0; \ -} -FLOAT_FMA(madd, 0) -FLOAT_FMA(msub, float_muladd_negate_c) -FLOAT_FMA(nmadd, float_muladd_negate_result) -FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) -#undef FLOAT_FMA - -#define FLOAT_FMADDSUB(name, bits, muladd_arg) \ -uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \ - uint ## bits ## _t fs, \ - uint ## bits ## _t ft, \ - uint ## bits ## _t fd) \ -{ \ - uint ## bits ## _t fdret; \ - \ - fdret =3D float ## bits ## _muladd(fs, ft, fd, muladd_arg, \ - &env->active_fpu.fp_status); \ - update_fcr31(env, GETPC()); \ - return fdret; \ -} - -FLOAT_FMADDSUB(maddf_s, 32, 0) -FLOAT_FMADDSUB(maddf_d, 64, 0) -FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product) -FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product) -#undef FLOAT_FMADDSUB - -/* compare operations */ -#define FOP_COND_D(op, cond) \ -void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ - uint64_t fdt1, int cc) \ -{ \ - int c; \ - c =3D cond; \ - update_fcr31(env, GETPC()); \ - if (c) \ - SET_FP_COND(cc, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc, env->active_fpu); \ -} \ -void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ - uint64_t fdt1, int cc) \ -{ \ - int c; \ - fdt0 =3D float64_abs(fdt0); \ - fdt1 =3D float64_abs(fdt1); \ - c =3D cond; \ - update_fcr31(env, GETPC()); \ - if (c) \ - SET_FP_COND(cc, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc, env->active_fpu); \ -} - -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. - */ -FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status), 0)) -FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status)) -FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_eq_quiet(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_le_quiet(fdt0, fdt1, - &env->active_fpu.fp_status)) -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called. - */ -FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status), 0)) -FOP_COND_D(ngle, float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status)) -FOP_COND_D(seq, float64_eq(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_eq(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(lt, float64_lt(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(nge, float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(le, float64_le(fdt0, fdt1, - &env->active_fpu.fp_status)) -FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_le(fdt0, fdt1, - &env->active_fpu.fp_status)) - -#define FOP_COND_S(op, cond) \ -void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ - uint32_t fst1, int cc) \ -{ \ - int c; \ - c =3D cond; \ - update_fcr31(env, GETPC()); \ - if (c) \ - SET_FP_COND(cc, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc, env->active_fpu); \ -} \ -void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ - uint32_t fst1, int cc) \ -{ \ - int c; \ - fst0 =3D float32_abs(fst0); \ - fst1 =3D float32_abs(fst1); \ - c =3D cond; \ - update_fcr31(env, GETPC()); \ - if (c) \ - SET_FP_COND(cc, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc, env->active_fpu); \ -} - -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. - */ -FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status), 0)) -FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status)) -FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_eq_quiet(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(ole, float32_le_quiet(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, - &env->active_fpu.fp_status)) -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. - */ -FOP_COND_S(sf, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status), 0)) -FOP_COND_S(ngle, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status)) -FOP_COND_S(seq, float32_eq(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(ngl, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_eq(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(lt, float32_lt(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(nge, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(le, float32_le(fst0, fst1, - &env->active_fpu.fp_status)) -FOP_COND_S(ngt, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le(fst0, fst1, - &env->active_fpu.fp_status)) - -#define FOP_COND_PS(op, condl, condh) \ -void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ - uint64_t fdt1, int cc) \ -{ \ - uint32_t fst0, fsth0, fst1, fsth1; \ - int ch, cl; \ - fst0 =3D fdt0 & 0XFFFFFFFF; \ - fsth0 =3D fdt0 >> 32; \ - fst1 =3D fdt1 & 0XFFFFFFFF; \ - fsth1 =3D fdt1 >> 32; \ - cl =3D condl; \ - ch =3D condh; \ - update_fcr31(env, GETPC()); \ - if (cl) \ - SET_FP_COND(cc, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc, env->active_fpu); \ - if (ch) \ - SET_FP_COND(cc + 1, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc + 1, env->active_fpu); \ -} \ -void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ - uint64_t fdt1, int cc) \ -{ \ - uint32_t fst0, fsth0, fst1, fsth1; \ - int ch, cl; \ - fst0 =3D float32_abs(fdt0 & 0XFFFFFFFF); \ - fsth0 =3D float32_abs(fdt0 >> 32); \ - fst1 =3D float32_abs(fdt1 & 0XFFFFFFFF); \ - fsth1 =3D float32_abs(fdt1 >> 32); \ - cl =3D condl; \ - ch =3D condh; \ - update_fcr31(env, GETPC()); \ - if (cl) \ - SET_FP_COND(cc, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc, env->active_fpu); \ - if (ch) \ - SET_FP_COND(cc + 1, env->active_fpu); \ - else \ - CLEAR_FP_COND(cc + 1, env->active_fpu); \ -} - -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. - */ -FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status), 0), - (float32_unordered_quiet(fsth1, fsth0, - &env->active_fpu.fp_status), 0)) -FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, - &env->active_fpu.fp_status)) -FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, - &env->active_fpu.fp_status), - float32_eq_quiet(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_eq_quiet(fst0, fst1, - &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, - &env->active_fpu.fp_status) - || float32_eq_quiet(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status), - float32_lt_quiet(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, - &env->active_fpu.fp_status) - || float32_lt_quiet(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, - &env->active_fpu.fp_status), - float32_le_quiet(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, - &env->active_fpu.fp_status), - float32_unordered_quiet(fsth1, fsth0, - &env->active_fpu.fp_status) - || float32_le_quiet(fsth0, fsth1, - &env->active_fpu.fp_status)) -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. - */ -FOP_COND_PS(sf, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status), 0), - (float32_unordered(fsth1, fsth0, - &env->active_fpu.fp_status), 0)) -FOP_COND_PS(ngle, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, - &env->active_fpu.fp_status)) -FOP_COND_PS(seq, float32_eq(fst0, fst1, - &env->active_fpu.fp_status), - float32_eq(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(ngl, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_eq(fst0, fst1, - &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, - &env->active_fpu.fp_status) - || float32_eq(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(lt, float32_lt(fst0, fst1, - &env->active_fpu.fp_status), - float32_lt(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(nge, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, - &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, - &env->active_fpu.fp_status) - || float32_lt(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(le, float32_le(fst0, fst1, - &env->active_fpu.fp_status), - float32_le(fsth0, fsth1, - &env->active_fpu.fp_status)) -FOP_COND_PS(ngt, float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le(fst0, fst1, - &env->active_fpu.fp_status), - float32_unordered(fsth1, fsth0, - &env->active_fpu.fp_status) - || float32_le(fsth0, fsth1, - &env->active_fpu.fp_status)) - -/* R6 compare operations */ -#define FOP_CONDN_D(op, cond) \ -uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ - uint64_t fdt1) \ -{ \ - uint64_t c; \ - c =3D cond; \ - update_fcr31(env, GETPC()); \ - if (c) { \ - return -1; \ - } else { \ - return 0; \ - } \ -} - -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered_quiet() is still called. - */ -FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status), 0)) -FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status))) -FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_eq_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_le_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float64_unordered() is still called.\ - */ -FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status), 0)) -FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status))) -FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_eq(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_le(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_le_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt_quiet(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_le(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, - &env->active_fpu.fp_status))) -FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, - &env->active_fpu.fp_status) - || float64_lt(fdt0, fdt1, - &env->active_fpu.fp_status))) - -#define FOP_CONDN_S(op, cond) \ -uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ - uint32_t fst1) \ -{ \ - uint64_t c; \ - c =3D cond; \ - update_fcr31(env, GETPC()); \ - if (c) { \ - return -1; \ - } else { \ - return 0; \ - } \ -} - -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered_quiet() is still called. - */ -FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status), 0)) -FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status))) -FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_eq_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -/* - * NOTE: the comma operator will make "cond" to eval to false, - * but float32_unordered() is still called. - */ -FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status), 0)) -FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status))) -FOP_CONDN_S(seq, (float32_eq(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_eq(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(slt, (float32_lt(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(sle, (float32_le(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt_quiet(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(sor, (float32_le(fst1, fst0, - &env->active_fpu.fp_status) - || float32_le(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, - &env->active_fpu.fp_status))) -FOP_CONDN_S(sne, (float32_lt(fst1, fst0, - &env->active_fpu.fp_status) - || float32_lt(fst0, fst1, - &env->active_fpu.fp_status))) =20 /* MSA */ /* Data format min and max values */ --=20 2.7.4