From nobody Mon Feb 9 09:15:34 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1580487107801328.58600131208686; Fri, 31 Jan 2020 08:11:47 -0800 (PST) Received: from localhost ([::1]:55522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixYtW-0006uR-NS for importer@patchew.org; Fri, 31 Jan 2020 11:11:46 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:40327) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ixXzB-00062a-Mo for qemu-devel@nongnu.org; Fri, 31 Jan 2020 10:13:35 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ixXz8-0006b0-9D for qemu-devel@nongnu.org; Fri, 31 Jan 2020 10:13:32 -0500 Received: from us-smtp-2.mimecast.com ([207.211.31.81]:33736 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ixXz8-0006Zt-4u for qemu-devel@nongnu.org; Fri, 31 Jan 2020 10:13:30 -0500 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-283-jXrj0U3IMxyCz3kVjekrtQ-1; Fri, 31 Jan 2020 10:13:25 -0500 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 953151088380 for ; Fri, 31 Jan 2020 15:13:24 +0000 (UTC) Received: from dell-r430-03.lab.eng.brq.redhat.com (dell-r430-03.lab.eng.brq.redhat.com [10.37.153.18]) by smtp.corp.redhat.com (Postfix) with ESMTP id 1C83C86C4B for ; Fri, 31 Jan 2020 15:13:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1580483609; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XSz0fh95TiXEIYskr68dnamMm5+1Fzfe2ip323eVXVM=; b=fo3eAD7AuKC/+TU7XSLGyzwhriNIU3CB85dn7uyNDoV7EN1IPv41No0AtD4lBgkTGsBQT0 zg2EfZgZOF21km1yFNl5OdO3UeswMJD29/f+Kz9RJ95l7maO0bGOSvb3ux3/4Ux5qxu3DJ UyumvSpbY5+r5bFoA0v2bPcJHfpBbik= From: Igor Mammedov To: qemu-devel@nongnu.org Subject: [PATCH v4 65/80] ppc/{ppc440_bamboo, sam460ex}: use memdev for RAM Date: Fri, 31 Jan 2020 16:09:35 +0100 Message-Id: <1580483390-131164-66-git-send-email-imammedo@redhat.com> In-Reply-To: <1580483390-131164-1-git-send-email-imammedo@redhat.com> References: <1580483390-131164-1-git-send-email-imammedo@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-MC-Unique: jXrj0U3IMxyCz3kVjekrtQ-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @redhat.com) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" memory_region_allocate_system_memory() API is going away, so replace it with memdev allocated MemoryRegion. The later is initialized by generic code, so board only needs to opt in to memdev scheme by providing MachineClass::default_ram_id and using MachineState::ram instead of manually initializing RAM memory region. Signed-off-by: Igor Mammedov Reviewed-by: BALATON Zoltan Acked-by: David Gibson --- v3: * drop ram_size from comment above ppc4xx_sdram_banks (BALATON Zoltan ) * move memory alias initialization into the same loop where RAM is split on banks. (BALATON Zoltan ) v3.1 * rebase on top of previous patch due to changed context --- include/hw/ppc/ppc4xx.h | 2 +- hw/ppc/ppc440_bamboo.c | 3 ++- hw/ppc/ppc4xx_devs.c | 25 +++++++++---------------- hw/ppc/sam460ex.c | 3 ++- 4 files changed, 14 insertions(+), 19 deletions(-) diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index b8c8f32..cc19c8d 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -42,7 +42,7 @@ enum { qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); =20 -void ppc4xx_sdram_banks(ram_addr_t ram_size, int nr_banks, +void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[], const ram_addr_t sdram_bank_sizes[]); diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 7e3bc0e..4c5e9e4 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -202,7 +202,7 @@ static void bamboo_init(MachineState *machine) /* SDRAM controller */ memset(ram_bases, 0, sizeof(ram_bases)); memset(ram_sizes, 0, sizeof(ram_sizes)); - ppc4xx_sdram_banks(machine->ram_size, PPC440EP_SDRAM_NR_BANKS, ram_mem= ories, + ppc4xx_sdram_banks(machine->ram, PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0= . */ ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, @@ -289,6 +289,7 @@ static void bamboo_machine_init(MachineClass *mc) mc->desc =3D "bamboo"; mc->init =3D bamboo_init; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("440epb"); + mc->default_ram_id =3D "ppc4xx.sdram"; } =20 DEFINE_MACHINE("bamboo", bamboo_machine_init) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index d89008a..0e2f81c 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -666,7 +666,7 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq,= int nbanks, sdram_map_bcr(sdram); } =20 -/* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. +/* Split RAM between SDRAM banks. * * sdram_bank_sizes[] must be in descending order, that is sizes[i] > size= s[i+1] * and must be 0-terminated. @@ -674,16 +674,14 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq ir= q, int nbanks, * The 4xx SDRAM controller supports a small number of banks, and each bank * must be one of a small set of sizes. The number of banks and the suppor= ted * sizes varies by SoC. */ -void ppc4xx_sdram_banks(ram_addr_t ram_size, int nr_banks, +void ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks, MemoryRegion ram_memories[], hwaddr ram_bases[], hwaddr ram_sizes[], const ram_addr_t sdram_bank_sizes[]) { - MemoryRegion *ram =3D g_malloc0(sizeof(*ram)); - ram_addr_t size_left =3D ram_size; + ram_addr_t size_left =3D memory_region_size(ram); ram_addr_t base =3D 0; ram_addr_t bank_size; - int last_bank =3D 0; int i; int j; =20 @@ -691,11 +689,15 @@ void ppc4xx_sdram_banks(ram_addr_t ram_size, int nr_b= anks, for (j =3D 0; sdram_bank_sizes[j] !=3D 0; j++) { bank_size =3D sdram_bank_sizes[j]; if (bank_size <=3D size_left) { + char name[32]; + ram_bases[i] =3D base; ram_sizes[i] =3D bank_size; base +=3D bank_size; size_left -=3D bank_size; - last_bank =3D i; + snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); + memory_region_init_alias(&ram_memories[i], NULL, name, ram, + ram_bases[i], ram_sizes[i]); break; } } @@ -706,7 +708,7 @@ void ppc4xx_sdram_banks(ram_addr_t ram_size, int nr_ban= ks, } =20 if (size_left) { - ram_addr_t used_size =3D ram_size - size_left; + ram_addr_t used_size =3D memory_region_size(ram) - size_left; GString *s =3D g_string_new(NULL); =20 for (i =3D 0; sdram_bank_sizes[i]; i++) { @@ -722,15 +724,6 @@ void ppc4xx_sdram_banks(ram_addr_t ram_size, int nr_ba= nks, g_string_free(s, true); exit(EXIT_FAILURE); } - - memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_si= ze); - - for (i =3D 0; i <=3D last_bank; i++) { - char name[32]; - snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); - memory_region_init_alias(&ram_memories[i], NULL, name, ram, - ram_bases[i], ram_sizes[i]); - } } =20 /*************************************************************************= ****/ diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 17d40bd..898453c 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -324,7 +324,7 @@ static void sam460ex_init(MachineState *machine) /* SDRAM controller */ /* put all RAM on first bank because board has one slot * and firmware only checks that */ - ppc4xx_sdram_banks(machine->ram_size, 1, ram_memories, ram_bases, ram_= sizes, + ppc4xx_sdram_banks(machine->ram, 1, ram_memories, ram_bases, ram_sizes, ppc460ex_sdram_bank_sizes); =20 /* FIXME: does 460EX have ECC interrupts? */ @@ -484,6 +484,7 @@ static void sam460ex_machine_init(MachineClass *mc) mc->init =3D sam460ex_init; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("460exb"); mc->default_ram_size =3D 512 * MiB; + mc->default_ram_id =3D "ppc4xx.sdram"; } =20 DEFINE_MACHINE("sam460ex", sam460ex_machine_init) --=20 2.7.4