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X-Received-From: 2a00:1450:4864:20::32f X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Greg Kurz Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Greg Kurz Convert all targets to use cpu_class_set_parent_reset() with the following coccinelle script: @@ type CPUParentClass; CPUParentClass *pcc; CPUClass *cc; identifier parent_fn; identifier child_fn; @@ +cpu_class_set_parent_reset(cc, child_fn, &pcc->parent_fn); -pcc->parent_fn =3D cc->reset; ... -cc->reset =3D child_fn; Signed-off-by: Greg Kurz Acked-by: David Gibson Reviewed-by: Alistair Francis Reviewed-by: Cornelia Huck Acked-by: David Hildenbrand Message-Id: <157650847817.354886.7047137349018460524.stgit@bahia.lan> Signed-off-by: Paolo Bonzini --- target/arm/cpu.c | 3 +-- target/cris/cpu.c | 3 +-- target/i386/cpu.c | 3 +-- target/lm32/cpu.c | 3 +-- target/m68k/cpu.c | 3 +-- target/microblaze/cpu.c | 3 +-- target/mips/cpu.c | 3 +-- target/moxie/cpu.c | 3 +-- target/nios2/cpu.c | 3 +-- target/openrisc/cpu.c | 3 +-- target/ppc/translate_init.inc.c | 3 +-- target/riscv/cpu.c | 3 +-- target/s390x/cpu.c | 3 +-- target/sh4/cpu.c | 3 +-- target/sparc/cpu.c | 3 +-- target/tilegx/cpu.c | 3 +-- target/tricore/cpu.c | 3 +-- target/xtensa/cpu.c | 3 +-- 18 files changed, 18 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d62fd5f..411faaa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2707,8 +2707,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void = *data) &acc->parent_realize); dc->props =3D arm_cpu_properties; =20 - acc->parent_reset =3D cc->reset; - cc->reset =3D arm_cpu_reset; + cpu_class_set_parent_reset(cc, arm_cpu_reset, &acc->parent_reset); =20 cc->class_by_name =3D arm_cpu_class_by_name; cc->has_work =3D arm_cpu_has_work; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 6a857f5..17c6712 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -264,8 +264,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *= data) device_class_set_parent_realize(dc, cris_cpu_realizefn, &ccc->parent_realize); =20 - ccc->parent_reset =3D cc->reset; - cc->reset =3D cris_cpu_reset; + cpu_class_set_parent_reset(cc, cris_cpu_reset, &ccc->parent_reset); =20 cc->class_by_name =3D cris_cpu_class_by_name; cc->has_work =3D cris_cpu_has_work; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 41f28ce..78bdb7c 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7149,8 +7149,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc= , void *data) &xcc->parent_unrealize); dc->props =3D x86_cpu_properties; =20 - xcc->parent_reset =3D cc->reset; - cc->reset =3D x86_cpu_reset; + cpu_class_set_parent_reset(cc, x86_cpu_reset, &xcc->parent_reset); cc->reset_dump_flags =3D CPU_DUMP_FPU | CPU_DUMP_CCOP; =20 cc->class_by_name =3D x86_cpu_class_by_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index b35537d..687bf35 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -218,8 +218,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *= data) =20 device_class_set_parent_realize(dc, lm32_cpu_realizefn, &lcc->parent_realize); - lcc->parent_reset =3D cc->reset; - cc->reset =3D lm32_cpu_reset; + cpu_class_set_parent_reset(cc, lm32_cpu_reset, &lcc->parent_reset); =20 cc->class_by_name =3D lm32_cpu_class_by_name; cc->has_work =3D lm32_cpu_has_work; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index f276335..f0653cd 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -273,8 +273,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *d= ata) =20 device_class_set_parent_realize(dc, m68k_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D m68k_cpu_reset; + cpu_class_set_parent_reset(cc, m68k_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D m68k_cpu_class_by_name; cc->has_work =3D m68k_cpu_has_work; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9cfd744..71d88f6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -292,8 +292,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *da= ta) =20 device_class_set_parent_realize(dc, mb_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D mb_cpu_reset; + cpu_class_set_parent_reset(cc, mb_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mb_cpu_class_by_name; cc->has_work =3D mb_cpu_has_work; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bbcf7ca..6cd6b96 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -189,8 +189,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) =20 device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D mips_cpu_reset; + cpu_class_set_parent_reset(cc, mips_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mips_cpu_class_by_name; cc->has_work =3D mips_cpu_has_work; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 48996d0..cf47bc7 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -101,8 +101,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void = *data) =20 device_class_set_parent_realize(dc, moxie_cpu_realizefn, &mcc->parent_realize); - mcc->parent_reset =3D cc->reset; - cc->reset =3D moxie_cpu_reset; + cpu_class_set_parent_reset(cc, moxie_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D moxie_cpu_class_by_name; =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ca9c7a6..bbdbc0c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -188,8 +188,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void = *data) device_class_set_parent_realize(dc, nios2_cpu_realizefn, &ncc->parent_realize); dc->props =3D nios2_properties; - ncc->parent_reset =3D cc->reset; - cc->reset =3D nios2_cpu_reset; + cpu_class_set_parent_reset(cc, nios2_cpu_reset, &ncc->parent_reset); =20 cc->class_by_name =3D nios2_cpu_class_by_name; cc->has_work =3D nios2_cpu_has_work; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 506aec6..5cd04da 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -150,8 +150,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, vo= id *data) =20 device_class_set_parent_realize(dc, openrisc_cpu_realizefn, &occ->parent_realize); - occ->parent_reset =3D cc->reset; - cc->reset =3D openrisc_cpu_reset; + cpu_class_set_parent_reset(cc, openrisc_cpu_reset, &occ->parent_reset); =20 cc->class_by_name =3D openrisc_cpu_class_by_name; cc->has_work =3D openrisc_cpu_has_work; diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index d33d65d..5ffd07c 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -10873,8 +10873,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, voi= d *data) pcc->interrupts_big_endian =3D ppc_cpu_interrupts_big_endian_always; dc->props =3D ppc_cpu_properties; =20 - pcc->parent_reset =3D cc->reset; - cc->reset =3D ppc_cpu_reset; + cpu_class_set_parent_reset(cc, ppc_cpu_reset, &pcc->parent_reset); =20 cc->class_by_name =3D ppc_cpu_class_by_name; pcc->parent_parse_features =3D cc->parse_features; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index d37861a..d6f1872 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -462,8 +462,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *= data) device_class_set_parent_realize(dc, riscv_cpu_realize, &mcc->parent_realize); =20 - mcc->parent_reset =3D cc->reset; - cc->reset =3D riscv_cpu_reset; + cpu_class_set_parent_reset(cc, riscv_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D riscv_cpu_class_by_name; cc->has_work =3D riscv_cpu_has_work; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index 625daee..ca487f5 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -456,12 +456,11 @@ static void s390_cpu_class_init(ObjectClass *oc, void= *data) dc->props =3D s390x_cpu_properties; dc->user_creatable =3D true; =20 - scc->parent_reset =3D cc->reset; + cpu_class_set_parent_reset(cc, s390_cpu_reset_full, &scc->parent_reset= ); #if !defined(CONFIG_USER_ONLY) scc->load_normal =3D s390_cpu_load_normal; #endif scc->reset =3D s390_cpu_reset; - cc->reset =3D s390_cpu_reset_full; cc->class_by_name =3D s390_cpu_class_by_name, cc->has_work =3D s390_cpu_has_work; #ifdef CONFIG_TCG diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index d0a7707..70c8d81 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -214,8 +214,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_realize(dc, superh_cpu_realizefn, &scc->parent_realize); =20 - scc->parent_reset =3D cc->reset; - cc->reset =3D superh_cpu_reset; + cpu_class_set_parent_reset(cc, superh_cpu_reset, &scc->parent_reset); =20 cc->class_by_name =3D superh_cpu_class_by_name; cc->has_work =3D superh_cpu_has_work; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index bc65929..9c306e5 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -859,8 +859,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void = *data) &scc->parent_realize); dc->props =3D sparc_cpu_properties; =20 - scc->parent_reset =3D cc->reset; - cc->reset =3D sparc_cpu_reset; + cpu_class_set_parent_reset(cc, sparc_cpu_reset, &scc->parent_reset); =20 cc->class_by_name =3D sparc_cpu_class_by_name; cc->parse_features =3D sparc_cpu_parse_features; diff --git a/target/tilegx/cpu.c b/target/tilegx/cpu.c index 2b2a7cc..cd422a0 100644 --- a/target/tilegx/cpu.c +++ b/target/tilegx/cpu.c @@ -142,8 +142,7 @@ static void tilegx_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_realize(dc, tilegx_cpu_realizefn, &tcc->parent_realize); =20 - tcc->parent_reset =3D cc->reset; - cc->reset =3D tilegx_cpu_reset; + cpu_class_set_parent_reset(cc, tilegx_cpu_reset, &tcc->parent_reset); =20 cc->class_by_name =3D tilegx_cpu_class_by_name; cc->has_work =3D tilegx_cpu_has_work; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index df807c1..85bc9f0 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -153,8 +153,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void= *data) device_class_set_parent_realize(dc, tricore_cpu_realizefn, &mcc->parent_realize); =20 - mcc->parent_reset =3D cc->reset; - cc->reset =3D tricore_cpu_reset; + cpu_class_set_parent_reset(cc, tricore_cpu_reset, &mcc->parent_reset); cc->class_by_name =3D tricore_cpu_class_by_name; cc->has_work =3D tricore_cpu_has_work; =20 diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index c65dcf9..4856aee 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -184,8 +184,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void= *data) device_class_set_parent_realize(dc, xtensa_cpu_realizefn, &xcc->parent_realize); =20 - xcc->parent_reset =3D cc->reset; - cc->reset =3D xtensa_cpu_reset; + cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset); =20 cc->class_by_name =3D xtensa_cpu_class_by_name; cc->has_work =3D xtensa_cpu_has_work; --=20 1.8.3.1