[PATCH] target/riscv: Set mstatus.DS & FS correctly

shihpo.hung@sifive.com posted 1 patch 4 years, 2 months ago
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git fetch https://github.com/patchew-project/qemu tags/patchew/1578647134-13216-1-git-send-email-shihpo.hung@sifive.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <Alistair.Francis@wdc.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
target/riscv/csr.c                      | 3 +--
target/riscv/insn_trans/trans_rvd.inc.c | 1 -
target/riscv/insn_trans/trans_rvf.inc.c | 1 -
target/riscv/translate.c                | 6 +-----
4 files changed, 2 insertions(+), 9 deletions(-)
[PATCH] target/riscv: Set mstatus.DS & FS correctly
Posted by shihpo.hung@sifive.com 4 years, 2 months ago
It was found that running libquantum on riscv-linux qemu produced an
incorrect result. After investigation, FP registers are not saved
during context switch due to incorrect mstatus.FS.

Because ctx->mstatus_fs changes dynamically during runtime, we should
remove the mstatus_fs check at the translation stage.

Signed-off-by: ShihPo Hung <shihpo.hung@sifive.com>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: qemu-riscv@nongnu.org
---
 target/riscv/csr.c                      | 3 +--
 target/riscv/insn_trans/trans_rvd.inc.c | 1 -
 target/riscv/insn_trans/trans_rvf.inc.c | 1 -
 target/riscv/translate.c                | 6 +-----
 4 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index da02f9f..0e34c29 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -341,8 +341,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
 
     mstatus = (mstatus & ~mask) | (val & mask);
 
-    dirty = (riscv_cpu_fp_enabled(env) &&
-             ((mstatus & MSTATUS_FS) == MSTATUS_FS)) |
+    dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
             ((mstatus & MSTATUS_XS) == MSTATUS_XS);
     mstatus = set_field(mstatus, MSTATUS_SD, dirty);
     env->mstatus = mstatus;
diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.inc.c
index 393fa02..ea1044f 100644
--- a/target/riscv/insn_trans/trans_rvd.inc.c
+++ b/target/riscv/insn_trans/trans_rvd.inc.c
@@ -43,7 +43,6 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
 
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEQ);
 
-    mark_fs_dirty(ctx);
     tcg_temp_free(t0);
     return true;
 }
diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.inc.c
index 172dbfa..e23cd63 100644
--- a/target/riscv/insn_trans/trans_rvf.inc.c
+++ b/target/riscv/insn_trans/trans_rvf.inc.c
@@ -52,7 +52,6 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
     tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], t0, ctx->mem_idx, MO_TEUL);
 
     tcg_temp_free(t0);
-    mark_fs_dirty(ctx);
     return true;
 }
 
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index ab6a891..4ef7300 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -386,15 +386,11 @@ static void gen_store_c(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
 static void mark_fs_dirty(DisasContext *ctx)
 {
     TCGv tmp;
-    if (ctx->mstatus_fs == MSTATUS_FS) {
-        return;
-    }
-    /* Remember the state change for the rest of the TB.  */
-    ctx->mstatus_fs = MSTATUS_FS;
 
     tmp = tcg_temp_new();
     tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
     tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS);
+    tcg_gen_ori_tl(tmp, tmp, MSTATUS_SD);
     tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus));
     tcg_temp_free(tmp);
 }
-- 
2.7.4


Re: [PATCH] target/riscv: Set mstatus.DS & FS correctly
Posted by Richard Henderson 4 years, 2 months ago
On 1/9/20 11:05 PM, shihpo.hung@sifive.com wrote:
> Because ctx->mstatus_fs changes dynamically during runtime, we should
> remove the mstatus_fs check at the translation stage.

This change is incorrect.

The actual bug is in cpu_get_tb_cpu_state(), as I just noticed during review:

"[PATCH 2/3] RISC-V: use FIELD macro to define tb flags"
https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg02455.html


r~

Re: [PATCH] target/riscv: Set mstatus.DS & FS correctly
Posted by ShihPo Hung 4 years, 2 months ago
On Tue, Jan 14, 2020 at 10:32 AM Richard Henderson <
richard.henderson@linaro.org> wrote:

> On 1/9/20 11:05 PM, shihpo.hung@sifive.com wrote:
> > Because ctx->mstatus_fs changes dynamically during runtime, we should
> > remove the mstatus_fs check at the translation stage.
>
> This change is incorrect.
>
> The actual bug is in cpu_get_tb_cpu_state(), as I just noticed during
> review:
>
> "[PATCH 2/3] RISC-V: use FIELD macro to define tb flags"
> https://lists.gnu.org/archive/html/qemu-devel/2020-01/msg02455.html


I didn't understand the purpose of mstatus_fs, but now I get it.
Thanks for pointing me to.
I will resend my patches.