From nobody Sat May 4 17:28:56 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1578306649; cv=none; d=zohomail.com; s=zohoarc; b=JGB8tZdTGN1o3N1cW9ft98SYWXlLn8eIEk2Tq3AfYu1ytQczeHu3TRX8n+ndnfnrW9Auba7CdR7aCkTQLDv5MG2f/SrjZZP/yV/oFl6zvnIHGOTGxcziy4O/hVmG3eBvaCPi82zTlxp1FQULAGhj7+OcxaMF0bD73zmZxFhgly4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1578306649; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Sender:Subject:To; bh=9GpqhyssTsj/EDiBZ19eJ517hlVLRaOyYFi/KWcb/mo=; b=NOZmxjCPLMRLOIh1+sULzCeKsTTCOyOWK3TFYBgxVh/M1Jtbm08QKoX5uUFt5c7fvWFwv35tLl5U8djHCzFjZhwhW+2NNDjhJZTig1jkY/s1PP8T6oBFHCcLjsOCFTHE1w8vmjEzk/dDq0uXU4QnkWeti3kjI1OIqEstOCIKytU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1578306649172114.77198267756023; Mon, 6 Jan 2020 02:30:49 -0800 (PST) Received: from localhost ([::1]:50278 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ioPep-0003GW-R5 for importer@patchew.org; Mon, 06 Jan 2020 05:30:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:41073) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ioPdw-0002BS-O5 for qemu-devel@nongnu.org; Mon, 06 Jan 2020 05:29:54 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ioPdv-0002qS-Ad for qemu-devel@nongnu.org; Mon, 06 Jan 2020 05:29:52 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:50044) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ioPdv-0002pT-2I for qemu-devel@nongnu.org; Mon, 06 Jan 2020 05:29:51 -0500 Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 006ASLaN076148 for ; Mon, 6 Jan 2020 05:29:49 -0500 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2xb92kwbqq-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Mon, 06 Jan 2020 05:29:49 -0500 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Mon, 6 Jan 2020 10:29:44 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 006AThuc49283148 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 6 Jan 2020 10:29:43 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A1580A405F; Mon, 6 Jan 2020 10:29:43 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6F762A405C; Mon, 6 Jan 2020 10:29:43 +0000 (GMT) Received: from bahia.lan (unknown [9.145.66.144]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Mon, 6 Jan 2020 10:29:43 +0000 (GMT) Subject: [PATCH] ppc/pnv: Drop "num-chips" machine property From: Greg Kurz To: David Gibson , =?utf-8?q?C=C3=A9dric?= Le Goater Date: Mon, 06 Jan 2020 11:29:42 +0100 User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 20010610-4275-0000-0000-0000039509F0 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 20010610-4276-0000-0000-000038A8F24C Message-Id: <157830658266.533764.2214183961444213947.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2020-01-06_03:2020-01-06,2020-01-06 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 phishscore=0 priorityscore=1501 impostorscore=0 bulkscore=0 malwarescore=0 mlxlogscore=999 suspectscore=0 clxscore=1034 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-2001060096 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The number of CPU chips of the powernv machine is configurable through a "num-chips" property. This doesn't fit well with the CPU topology, eg. some configurations can come up with more CPUs than the maximum of CPUs set in the toplogy. This causes assertion to be hit with mttcg: -machine powernv,num-chips=3D2 -smp cores=3D2 -accel tcg,thread=3Dmulti ERROR: tcg/tcg.c:789:tcg_register_thread: assertion failed: (n < ms->smp.max_cpus) Aborted (core dumped) Mttcg mandates the CPU topology to be dimensioned to the actual number of CPUs, depending on the number of chips the user asked for. That is, '-machine num-chips=3DN' should always have a '-smp' companion with a topology that meats the resulting number of CPUs, typically '-smp sockets=3DN'. It thus seems that "num-chips" doesn't bring anything but forcing the user to specify the requested number of chips on the command line twice. Simplify the command line by computing the number of chips based on the CPU topology exclusively. The powernv machine isn't a production thing ; it is mostly used by developpers to prepare the bringup of real HW. Because of this and for simplicity, this deliberately ignores the official deprecation process and dumps "num-chips" right away : '-smp sockets=3DN' is now the only way to control the number of CPU chips. This is done at machine init because smp_parse() is called after instance init. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 62 +++++++++++-------------------------------------------= ---- 1 file changed, 12 insertions(+), 50 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f77e7ca84ede..b225ffbb2c41 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -768,6 +768,18 @@ static void pnv_init(MachineState *machine) exit(1); } =20 + pnv->num_chips =3D + machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads= ); + /* + * TODO: should we decide on how many chips we can create based + * on #cores and Venice vs. Murano vs. Naples chip type etc..., + */ + if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { + error_report("invalid number of chips: '%d'", pnv->num_chips); + error_printf("Try '-smp sockets=3DN'. Valid values are : 1, 2 or 4= .\n"); + exit(1); + } + pnv->chips =3D g_new0(PnvChip *, pnv->num_chips); for (i =3D 0; i < pnv->num_chips; i++) { char chip_name[32]; @@ -1696,53 +1708,6 @@ PnvChip *pnv_get_chip(uint32_t chip_id) return NULL; } =20 -static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); -} - -static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - PnvMachineState *pnv =3D PNV_MACHINE(obj); - uint32_t num_chips; - Error *local_err =3D NULL; - - visit_type_uint32(v, name, &num_chips, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - /* - * TODO: should we decide on how many chips we can create based - * on #cores and Venice vs. Murano vs. Naples chip type etc..., - */ - if (!is_power_of_2(num_chips) || num_chips > 4) { - error_setg(errp, "invalid number of chips: '%d'", num_chips); - return; - } - - pnv->num_chips =3D num_chips; -} - -static void pnv_machine_instance_init(Object *obj) -{ - PnvMachineState *pnv =3D PNV_MACHINE(obj); - pnv->num_chips =3D 1; -} - -static void pnv_machine_class_props_init(ObjectClass *oc) -{ - object_class_property_add(oc, "num-chips", "uint32", - pnv_get_num_chips, pnv_set_num_chips, - NULL, NULL, NULL); - object_class_property_set_description(oc, "num-chips", - "Specifies the number of processor chips", - NULL); -} - static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -1812,8 +1777,6 @@ static void pnv_machine_class_init(ObjectClass *oc, v= oid *data) */ mc->default_ram_size =3D INITRD_LOAD_ADDR + INITRD_MAX_SIZE; ispc->print_info =3D pnv_pic_print_info; - - pnv_machine_class_props_init(oc); } =20 #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ @@ -1866,7 +1829,6 @@ static const TypeInfo types[] =3D { .parent =3D TYPE_MACHINE, .abstract =3D true, .instance_size =3D sizeof(PnvMachineState), - .instance_init =3D pnv_machine_instance_init, .class_init =3D pnv_machine_class_init, .class_size =3D sizeof(PnvMachineClass), .interfaces =3D (InterfaceInfo[]) {