From nobody Mon Apr 29 15:59:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576766099; cv=none; d=zohomail.com; s=zohoarc; b=gvp5yD6bRpPZLxt15NqrnaVsSIb4ievcSEHVqhP7io5v6W+mkD2lgRelyVoZlQSQaBDUS/FZ4knrA66339DUH8+vmuuEaSQievAhcMX9cz6bxRIXtji2Eb2xgPpFGB1cBEz/Q0YSLvPiLnlaWsanibewQ6s8sNngYog4XBvVvAU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576766099; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=VhTQECwhbid621c0TWo6jHTqY6s2/b+CuPcB0FB/ILY=; b=oH4ScdEWIrCulH0AzPp3+BIH5pSfhho0XqW1/YtawsMtQlPYOytvfomx/n0THlYmRkSvZtrHWTBVo7z4WUmPmMzgu/89tQGX5yW5dvMCdU/98LEa3jie6L02R/MmUFj9D1OhkYDqxlOYTqDyFw5mfDhIPCnRZipX/otJVUPNQV4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576766099017405.32194398662807; Thu, 19 Dec 2019 06:34:59 -0800 (PST) Received: from localhost ([::1]:42684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihwtF-0007fV-CG for importer@patchew.org; Thu, 19 Dec 2019 09:34:57 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:55029) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ihwba-0000BG-Nr for qemu-devel@nongnu.org; Thu, 19 Dec 2019 09:16:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihwbZ-00007c-1e for qemu-devel@nongnu.org; Thu, 19 Dec 2019 09:16:42 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:60266 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihwbY-0003zI-KA for qemu-devel@nongnu.org; Thu, 19 Dec 2019 09:16:40 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 6F2571A2277; Thu, 19 Dec 2019 15:15:37 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 4E0D11A2190; Thu, 19 Dec 2019 15:15:37 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/mips: Add support for MIPS<32|64>R6 CRC32 ISA Date: Thu, 19 Dec 2019 15:15:19 +0100 Message-Id: <1576764920-24514-2-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576764920-24514-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1576764920-24514-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com, Aleksandar Markovic , aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Add support for eight CRC-related MIPS<32|64>R6 instructions. Signed-off-by: Aleksandar Markovic --- disas/mips.c | 8 +++ target/mips/helper.h | 2 + target/mips/op_helper.c | 19 ++++++++ target/mips/translate.c | 127 ++++++++++++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 156 insertions(+) diff --git a/disas/mips.c b/disas/mips.c index dfefe5e..75c48b3 100644 --- a/disas/mips.c +++ b/disas/mips.c @@ -1409,6 +1409,14 @@ const struct mips_opcode mips_builtin_opcodes[] =3D {"dvp", "t", 0x41600024, 0xffe0ffff, TRAP|WR_t, 0, I= 32R6}, {"evp", "", 0x41600004, 0xffffffff, TRAP, 0, I= 32R6}, {"evp", "t", 0x41600004, 0xffe0ffff, TRAP|WR_t, 0, I= 32R6}, +{"crc32b", "t,v,t", 0x7c00000f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32h", "t,v,t", 0x7c00004f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32w", "t,v,t", 0x7c00008f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32d", "t,v,t", 0x7c0000cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 64R6}, +{"crc32cb", "t,v,t", 0x7c00010f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32ch", "t,v,t", 0x7c00014f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32cw", "t,v,t", 0x7c00018f, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 32R6}, +{"crc32cd", "t,v,t", 0x7c0001cf, 0xfc00ff3f, WR_d | RD_s | RD_t, 0, I= 64R6}, =20 /* MSA */ {"sll.b", "+d,+e,+f", 0x7800000d, 0xffe0003f, WR_VD|RD_VS|RD_VT, 0, MSA= }, diff --git a/target/mips/helper.h b/target/mips/helper.h index 7b8ad74..2095330 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -40,6 +40,8 @@ DEF_HELPER_FLAGS_1(bitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) #endif =20 +DEF_HELPER_3(crc32, tl, tl, tl, i32) +DEF_HELPER_3(crc32c, tl, tl, tl, i32) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) =20 #ifndef CONFIG_USER_ONLY diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 18fcee4..5cd396d 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -27,6 +27,8 @@ #include "exec/memop.h" #include "sysemu/kvm.h" #include "fpu/softfloat.h" +#include "qemu/crc32c.h" +#include =20 /*************************************************************************= ****/ /* Exceptions processing helpers */ @@ -350,6 +352,23 @@ target_ulong helper_rotx(target_ulong rs, uint32_t shi= ft, uint32_t shiftx, return (int64_t)(int32_t)(uint32_t)tmp5; } =20 +/* these crc32 functions are based on target/arm/helper-a64.c */ +target_ulong helper_crc32(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + + stq_le_p(buf, m); + return (int32_t) (crc32(val ^ 0xffffffff, buf, sz) ^ 0xffffffff); +} + +target_ulong helper_crc32c(target_ulong val, target_ulong m, uint32_t sz) +{ + uint8_t buf[8]; + + stq_le_p(buf, m); + return (int32_t) (crc32c(val, buf, sz) ^ 0xffffffff); +} + #ifndef CONFIG_USER_ONLY =20 static inline hwaddr do_translate_address(CPUMIPSState *env, diff --git a/target/mips/translate.c b/target/mips/translate.c index 4bff585..1b38356 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -451,6 +451,7 @@ enum { OPC_LWE =3D 0x2F | OPC_SPECIAL3, =20 /* R6 */ + OPC_CRC32 =3D 0x0F | OPC_SPECIAL3, R6_OPC_PREF =3D 0x35 | OPC_SPECIAL3, R6_OPC_CACHE =3D 0x25 | OPC_SPECIAL3, R6_OPC_LL =3D 0x36 | OPC_SPECIAL3, @@ -2547,6 +2548,7 @@ typedef struct DisasContext { bool nan2008; bool abs2008; bool saar; + bool crcp; } DisasContext; =20 #define DISAS_STOP DISAS_TARGET_0 @@ -27117,11 +27119,96 @@ static void decode_opc_special2_legacy(CPUMIPSSta= te *env, DisasContext *ctx) } } =20 +static void gen_crc32(DisasContext *ctx, int rd, int rs, int rt, int sz, + int crc32c) +{ + TCGv t0; + TCGv t1; + TCGv_i32 tsz =3D tcg_const_i32(1 << sz); + uint64_t mask =3D 0; + + if (rd =3D=3D 0) { + /* Treat as NOP. */ + return; + } + t0 =3D tcg_temp_new(); + t1 =3D tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + + if (sz !=3D 3) { + switch (sz) { + case 0: + mask =3D 0xFF; + break; + case 1: + mask =3D 0xFFFF; + break; + case 2: + mask =3D 0xFFFFFFFF; + break; + } + tcg_gen_andi_tl(t1, t1, mask); + } + + if (crc32c) { + gen_helper_crc32c(cpu_gpr[rd], t0, t1, tsz); + } else { + gen_helper_crc32(cpu_gpr[rd], t0, t1, tsz); + } + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free_i32(tsz); +} + +static void gen_crc32b(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 0, 0); +} + +static void gen_crc32h(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 1, 0); +} + +static void gen_crc32w(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 2, 0); +} + +static void gen_crc32d(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 3, 0); +} + +static void gen_crc32cb(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 0, 1); +} + +static void gen_crc32ch(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 1, 1); +} + +static void gen_crc32cw(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 2, 1); +} + +static void gen_crc32cd(DisasContext *ctx, int rd, int rs, int rt) +{ + gen_crc32(ctx, rd, rs, rt, 3, 1); +} + static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) { int rs, rt, rd, sa; uint32_t op1, op2; int16_t imm; + int sz, crc32c; =20 rs =3D (ctx->opcode >> 21) & 0x1f; rt =3D (ctx->opcode >> 16) & 0x1f; @@ -27131,6 +27218,45 @@ static void decode_opc_special3_r6(CPUMIPSState *e= nv, DisasContext *ctx) =20 op1 =3D MASK_SPECIAL3(ctx->opcode); switch (op1) { + case OPC_CRC32: + sz =3D extract32(ctx->opcode, 6, 2); + crc32c =3D extract32(ctx->opcode, 8, 3); + if (unlikely(!ctx->crcp) || + unlikely((sz =3D=3D 3) && (!(ctx->hflags & MIPS_HFLAG_64))) || + unlikely((crc32c >=3D 2))) { + generate_exception_end(ctx, EXCP_RI); + } + switch (sz) { + case 0: + if (crc32c) { + gen_crc32cb(ctx, rt, rs, rt); + } else { + gen_crc32b(ctx, rt, rs, rt); + } + break; + case 1: + if (crc32c) { + gen_crc32ch(ctx, rt, rs, rt); + } else { + gen_crc32h(ctx, rt, rs, rt); + } + break; + case 2: + if (crc32c) { + gen_crc32cw(ctx, rt, rs, rt); + } else { + gen_crc32w(ctx, rt, rs, rt); + } + break; + case 3: + if (crc32c) { + gen_crc32cd(ctx, rt, rs, rt); + } else { + gen_crc32d(ctx, rt, rs, rt); + } + break; + } + break; case R6_OPC_PREF: if (rt >=3D 24) { /* hint codes 24-31 are reserved and signal RI */ @@ -30727,6 +30853,7 @@ static void mips_tr_init_disas_context(DisasContext= Base *dcbase, CPUState *cs) ctx->mrp =3D (env->CP0_Config5 >> CP0C5_MRP) & 1; ctx->nan2008 =3D (env->active_fpu.fcr31 >> FCR31_NAN2008) & 1; ctx->abs2008 =3D (env->active_fpu.fcr31 >> FCR31_ABS2008) & 1; + ctx->crcp =3D (env->CP0_Config5 >> CP0C5_CRCP) & 1; restore_cpu_state(env, ctx); #ifdef CONFIG_USER_ONLY ctx->mem_idx =3D MIPS_HFLAG_UM; --=20 2.7.4 From nobody Mon Apr 29 15:59:46 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576765946; cv=none; d=zohomail.com; s=zohoarc; b=Gi50AxKsyHvFM34L0185f0145DELQcwe8E3ThEJw13m0Ak5nSyvVINCFl5AOcTU65/6LycFMf7OkEXOmrz/+YjtFQ8xmTT+KAytCd9RVaFU/pSy1dp0zj/o7omK3y4Ae0i1g1haJRsToeSkcPyHS1KNg5ayvsr+DD4AIB8kt+fk= ARC-Message-Signature: i=1; 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Thu, 19 Dec 2019 09:16:44 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ihwba-0000ET-5U for qemu-devel@nongnu.org; Thu, 19 Dec 2019 09:16:43 -0500 Received: from mx2.rt-rk.com ([89.216.37.149]:60276 helo=mail.rt-rk.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ihwbZ-00046g-T9 for qemu-devel@nongnu.org; Thu, 19 Dec 2019 09:16:42 -0500 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 99B3E1A2282; Thu, 19 Dec 2019 15:15:38 +0100 (CET) Received: from rtrkw774-lin.domain.local (rtrkw774-lin.domain.local [10.10.14.106]) by mail.rt-rk.com (Postfix) with ESMTPSA id 80B021A2190; Thu, 19 Dec 2019 15:15:38 +0100 (CET) X-Virus-Scanned: amavisd-new at rt-rk.com From: Aleksandar Markovic To: qemu-devel@nongnu.org Subject: [PATCH 2/2] target/mips: Correct data on deprecated r4k machine Date: Thu, 19 Dec 2019 15:15:20 +0100 Message-Id: <1576764920-24514-3-git-send-email-aleksandar.markovic@rt-rk.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1576764920-24514-1-git-send-email-aleksandar.markovic@rt-rk.com> References: <1576764920-24514-1-git-send-email-aleksandar.markovic@rt-rk.com> X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [fuzzy] X-Received-From: 89.216.37.149 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: aleksandar.rikalo@rt-rk.com, Aleksandar Markovic , aurelien@aurel32.net Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: Aleksandar Markovic Change the release since r4k machine is deprecated from 4.2 to 5.0. Signed-off-by: Aleksandar Markovic Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth --- qemu-deprecated.texi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu-deprecated.texi b/qemu-deprecated.texi index 62680f7..f71c740 100644 --- a/qemu-deprecated.texi +++ b/qemu-deprecated.texi @@ -254,7 +254,7 @@ The 'scsi-disk' device is deprecated. Users should use = 'scsi-hd' or =20 @section System emulator machines =20 -@subsection mips r4k platform (since 4.2) +@subsection mips r4k platform (since 5.0) =20 This machine type is very old and unmaintained. Users should use the 'malt= a' machine type instead. --=20 2.7.4