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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 11:59:35 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDBwqOj44958078 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 11:58:52 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B581252052; Fri, 13 Dec 2019 11:59:34 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 85F7352051; Fri, 13 Dec 2019 11:59:34 +0000 (GMT) Subject: [PATCH 01/13] ppc: Drop useless extern annotation for functions From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 12:59:34 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-TM-AS-GCONF: 00 x-cbid: 19121311-0028-0000-0000-000003C82A44 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121311-0029-0000-0000-0000248B6785 Message-Id: <157623837421.360005.412120366652768311.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 clxscore=1034 mlxlogscore=999 malwarescore=0 phishscore=0 spamscore=0 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 Content-Transfer-Encoding: quoted-printable X-MIME-Autoconverted: from 8bit to quoted-printable by mx0a-001b2d01.pphosted.com id xBDBvEpN049375 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/ppc/pnv_xscom.h | 22 +++++++++++----------- include/hw/ppc/spapr_vio.h | 6 +++--- 2 files changed, 14 insertions(+), 14 deletions(-) diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 09188d74b06b..2bdb7ae84fd3 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -113,16 +113,16 @@ typedef struct PnvXScomInterfaceClass { #define PNV10_XSCOM_PSIHB_BASE 0x3011D00 #define PNV10_XSCOM_PSIHB_SIZE 0x100 =20 -extern void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); -extern int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); - -extern void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, - MemoryRegion *mr); -extern void pnv_xscom_region_init(MemoryRegion *mr, - struct Object *owner, - const MemoryRegionOps *ops, - void *opaque, - const char *name, - uint64_t size); +void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); +int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); + +void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, + MemoryRegion *mr); +void pnv_xscom_region_init(MemoryRegion *mr, + struct Object *owner, + const MemoryRegionOps *ops, + void *opaque, + const char *name, + uint64_t size); =20 #endif /* PPC_PNV_XSCOM_H */ diff --git a/include/hw/ppc/spapr_vio.h b/include/hw/ppc/spapr_vio.h index 72762ed16b70..ce6d9b0c6605 100644 --- a/include/hw/ppc/spapr_vio.h +++ b/include/hw/ppc/spapr_vio.h @@ -80,10 +80,10 @@ struct SpaprVioBus { uint32_t next_reg; }; =20 -extern SpaprVioBus *spapr_vio_bus_init(void); -extern SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t re= g); +SpaprVioBus *spapr_vio_bus_init(void); +SpaprVioDevice *spapr_vio_find_by_reg(SpaprVioBus *bus, uint32_t reg); void spapr_dt_vdevice(SpaprVioBus *bus, void *fdt); -extern gchar *spapr_vio_stdout_path(SpaprVioBus *bus); +gchar *spapr_vio_stdout_path(SpaprVioBus *bus); =20 static inline void spapr_vio_irq_pulse(SpaprVioDevice *dev) { From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576238783; cv=none; d=zohomail.com; s=zohoarc; b=erQaiiAvuVANoXY3eErG0R/dG9V1PyKgIsSei38NCgctEXI3PONjoqYyV5vvx+Q7/C3ZAGjNzJmLqqf0gWUPmkBrMlJNmToF1baZx3Ic3t8GGQijaEA+G1TPYC+uG16NW9ccUYG/mWlb187jJ0PriMztHMyxvXZEMDhanvHznpA= ARC-Message-Signature: i=1; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 11:59:41 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDBxegZ39387514 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 11:59:40 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4AEE84C058; Fri, 13 Dec 2019 11:59:40 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1AA0B4C04E; Fri, 13 Dec 2019 11:59:40 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 11:59:40 +0000 (GMT) Subject: [PATCH 02/13] ppc/pnv: Introduce PnvPsiClass::compat From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 12:59:39 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121311-4275-0000-0000-0000038E93CB X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121311-4276-0000-0000-000038A250A8 Message-Id: <157623837974.360005.14706607446188964477.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 adultscore=0 clxscore=1034 spamscore=0 malwarescore=0 phishscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The Processor Service Interface (PSI) model has a chip_type class level attribute, which is used to generate the content of the "compatible" DT property according to the CPU type. Since the PSI model already has specialized classes for each supported CPU type, it seems cleaner to achieve this with QOM. Provide the content of the "compatible" property with a new class level attribute. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_psi.c | 25 +++++++++++-------------- include/hw/ppc/pnv_psi.h | 2 ++ 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 572924388b3c..98a82b25e01f 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -536,10 +536,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, E= rror **errp) qemu_register_reset(pnv_psi_reset, dev); } =20 -static const char compat_p8[] =3D "ibm,power8-psihb-x\0ibm,psihb-x"; -static const char compat_p9[] =3D "ibm,power9-psihb-x\0ibm,psihb-x"; -static const char compat_p10[] =3D "ibm,power10-psihb-x\0ibm,psihb-x"; - static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_o= ffset) { PnvPsiClass *ppc =3D PNV_PSI_GET_CLASS(dev); @@ -558,16 +554,8 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, vo= id *fdt, int xscom_offset) _FDT(fdt_setprop(fdt, offset, "reg", reg, sizeof(reg))); _FDT(fdt_setprop_cell(fdt, offset, "#address-cells", 2)); _FDT(fdt_setprop_cell(fdt, offset, "#size-cells", 1)); - if (ppc->chip_type =3D=3D PNV_CHIP_POWER10) { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p10, - sizeof(compat_p10))); - } else if (ppc->chip_type =3D=3D PNV_CHIP_POWER9) { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p9, - sizeof(compat_p9))); - } else { - _FDT(fdt_setprop(fdt, offset, "compatible", compat_p8, - sizeof(compat_p8))); - } + _FDT(fdt_setprop(fdt, offset, "compatible", ppc->compat, + ppc->compat_size)); return 0; } =20 @@ -581,6 +569,7 @@ static void pnv_psi_power8_class_init(ObjectClass *klas= s, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PnvPsiClass *ppc =3D PNV_PSI_CLASS(klass); + static const char compat[] =3D "ibm,power8-psihb-x\0ibm,psihb-x"; =20 dc->desc =3D "PowerNV PSI Controller POWER8"; dc->realize =3D pnv_psi_power8_realize; @@ -590,6 +579,8 @@ static void pnv_psi_power8_class_init(ObjectClass *klas= s, void *data) ppc->xscom_size =3D PNV_XSCOM_PSIHB_SIZE; ppc->bar_mask =3D PSIHB_BAR_MASK; ppc->irq_set =3D pnv_psi_power8_irq_set; + ppc->compat =3D compat; + ppc->compat_size =3D sizeof(compat); } =20 static const TypeInfo pnv_psi_power8_info =3D { @@ -888,6 +879,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klas= s, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvPsiClass *ppc =3D PNV_PSI_CLASS(klass); XiveNotifierClass *xfc =3D XIVE_NOTIFIER_CLASS(klass); + static const char compat[] =3D "ibm,power9-psihb-x\0ibm,psihb-x"; =20 dc->desc =3D "PowerNV PSI Controller POWER9"; dc->realize =3D pnv_psi_power9_realize; @@ -897,6 +889,8 @@ static void pnv_psi_power9_class_init(ObjectClass *klas= s, void *data) ppc->xscom_size =3D PNV9_XSCOM_PSIHB_SIZE; ppc->bar_mask =3D PSIHB9_BAR_MASK; ppc->irq_set =3D pnv_psi_power9_irq_set; + ppc->compat =3D compat; + ppc->compat_size =3D sizeof(compat); =20 xfc->notify =3D pnv_psi_notify; } @@ -917,12 +911,15 @@ static void pnv_psi_power10_class_init(ObjectClass *k= lass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); PnvPsiClass *ppc =3D PNV_PSI_CLASS(klass); + static const char compat[] =3D "ibm,power10-psihb-x\0ibm,psihb-x"; =20 dc->desc =3D "PowerNV PSI Controller POWER10"; =20 ppc->chip_type =3D PNV_CHIP_POWER10; ppc->xscom_pcba =3D PNV10_XSCOM_PSIHB_BASE; ppc->xscom_size =3D PNV10_XSCOM_PSIHB_SIZE; + ppc->compat =3D compat; + ppc->compat_size =3D sizeof(compat); } =20 static const TypeInfo pnv_psi_power10_info =3D { diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index a044aab304ae..fc068c95e543 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -83,6 +83,8 @@ typedef struct PnvPsiClass { uint32_t xscom_pcba; uint32_t xscom_size; uint64_t bar_mask; + const char *compat; + int compat_size; =20 void (*irq_set)(PnvPsi *psi, int, bool state); } PnvPsiClass; From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 11:59:46 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDBxjqQ57606320 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 11:59:45 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D0FC6A4057; Fri, 13 Dec 2019 11:59:45 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A2E0DA4040; Fri, 13 Dec 2019 11:59:45 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 11:59:45 +0000 (GMT) Subject: [PATCH 03/13] ppc/pnv: Drop PnvPsiClass::chip_type From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 12:59:45 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121311-0028-0000-0000-000003C82A47 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121311-0029-0000-0000-0000248B6788 Message-Id: <157623838530.360005.15470128760871845396.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=665 impostorscore=0 priorityscore=1501 clxscore=1034 suspectscore=0 bulkscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" It isn't used anymore. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv_psi.c | 3 --- include/hw/ppc/pnv_psi.h | 1 - 2 files changed, 4 deletions(-) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 98a82b25e01f..75e20d9da08b 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -574,7 +574,6 @@ static void pnv_psi_power8_class_init(ObjectClass *klas= s, void *data) dc->desc =3D "PowerNV PSI Controller POWER8"; dc->realize =3D pnv_psi_power8_realize; =20 - ppc->chip_type =3D PNV_CHIP_POWER8; ppc->xscom_pcba =3D PNV_XSCOM_PSIHB_BASE; ppc->xscom_size =3D PNV_XSCOM_PSIHB_SIZE; ppc->bar_mask =3D PSIHB_BAR_MASK; @@ -884,7 +883,6 @@ static void pnv_psi_power9_class_init(ObjectClass *klas= s, void *data) dc->desc =3D "PowerNV PSI Controller POWER9"; dc->realize =3D pnv_psi_power9_realize; =20 - ppc->chip_type =3D PNV_CHIP_POWER9; ppc->xscom_pcba =3D PNV9_XSCOM_PSIHB_BASE; ppc->xscom_size =3D PNV9_XSCOM_PSIHB_SIZE; ppc->bar_mask =3D PSIHB9_BAR_MASK; @@ -915,7 +913,6 @@ static void pnv_psi_power10_class_init(ObjectClass *kla= ss, void *data) =20 dc->desc =3D "PowerNV PSI Controller POWER10"; =20 - ppc->chip_type =3D PNV_CHIP_POWER10; ppc->xscom_pcba =3D PNV10_XSCOM_PSIHB_BASE; ppc->xscom_size =3D PNV10_XSCOM_PSIHB_SIZE; ppc->compat =3D compat; diff --git a/include/hw/ppc/pnv_psi.h b/include/hw/ppc/pnv_psi.h index fc068c95e543..f0f5b5519767 100644 --- a/include/hw/ppc/pnv_psi.h +++ b/include/hw/ppc/pnv_psi.h @@ -79,7 +79,6 @@ typedef struct Pnv9Psi { typedef struct PnvPsiClass { SysBusDeviceClass parent_class; =20 - int chip_type; uint32_t xscom_pcba; uint32_t xscom_size; uint64_t bar_mask; From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576238929; cv=none; d=zohomail.com; s=zohoarc; b=I3Mv0ZnKwe1jWe4jO3Fkuz3bQEJe1UG1usr2oe5RDaTWZ+mcq77WG0ukNpSbaEA5D+JPnzyAxEzF9x70ht1hl4gdTOuK4hGQwLw60R6LDcIwDFf8EmnqsLxwT/B3iS/0p602VQVKWRscs3fEEgXAca147TKyt5QFt/Scxg9KO3k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576238929; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qTLlH3J8HPg51qnNaiQbwVnygET3ihqujtvgFVTCfAs=; b=lpezL46bcTm3nRaT2G3GoP+8fP3ehrAvm8SnIAdCgUSr1178IYlhCpRuFJ+3hFoQHvN1qaOpsja7blHVztAajFE8wFiiO+jIrhWnxnrb8KCTMOakHC4HER5jgrbS9Sk3ZikMrtawPMA5PuNwhuHu748FJOmcQWscQBB+6nukpkw= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576238929411361.4475389782484; Fri, 13 Dec 2019 04:08:49 -0800 (PST) Received: from localhost ([::1]:48164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifjkV-0007ob-PO for importer@patchew.org; Fri, 13 Dec 2019 07:08:47 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:60180) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifjbz-0007Ha-NN for qemu-devel@nongnu.org; Fri, 13 Dec 2019 07:00:01 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifjby-00040x-9Q for qemu-devel@nongnu.org; Fri, 13 Dec 2019 06:59:59 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:44356) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifjby-000408-0l for qemu-devel@nongnu.org; Fri, 13 Dec 2019 06:59:58 -0500 Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBDBuw3r008357 for ; Fri, 13 Dec 2019 06:59:57 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wuhsdnqhh-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 13 Dec 2019 06:59:56 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 11:59:52 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDBxp4058327072 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 11:59:51 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 6927042042; Fri, 13 Dec 2019 11:59:51 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 379FE42041; Fri, 13 Dec 2019 11:59:51 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 11:59:51 +0000 (GMT) Subject: [PATCH 04/13] ppc/pnv: Introduce PnvMachineClass and PnvMachineClass::compat From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 12:59:50 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121311-0028-0000-0000-000003C82A48 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121311-0029-0000-0000-0000248B6789 Message-Id: <157623839085.360005.4046508784077843216.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 bulkscore=0 adultscore=0 clxscore=1034 phishscore=0 mlxlogscore=999 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The pnv_dt_create() function generates different contents for the "compatible" property of the root node in the DT, depending on the CPU type. This is open coded with multiple ifs using pnv_is_powerXX() helpers. It seems cleaner to achieve with QOM. Introduce a base class for the powernv machine and a compat attribute that each child class can use to provide the value for the "compatible" property. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 33 +++++++++++++++++++-------------- include/hw/ppc/pnv.h | 13 +++++++++++++ 2 files changed, 32 insertions(+), 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0be0b6b411c3..5ac149b149d8 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -484,9 +484,7 @@ static void pnv_dt_power_mgt(void *fdt) =20 static void *pnv_dt_create(MachineState *machine) { - const char plat_compat8[] =3D "qemu,powernv8\0qemu,powernv\0ibm,powern= v"; - const char plat_compat9[] =3D "qemu,powernv9\0ibm,powernv"; - const char plat_compat10[] =3D "qemu,powernv10\0ibm,powernv"; + PnvMachineClass *pmc =3D PNV_MACHINE_GET_CLASS(machine); PnvMachineState *pnv =3D PNV_MACHINE(machine); void *fdt; char *buf; @@ -504,17 +502,8 @@ static void *pnv_dt_create(MachineState *machine) _FDT((fdt_setprop_cell(fdt, 0, "#size-cells", 0x2))); _FDT((fdt_setprop_string(fdt, 0, "model", "IBM PowerNV (emulated by qemu)"))); - if (pnv_is_power10(pnv)) { - _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat10, - sizeof(plat_compat10)))); - } else if (pnv_is_power9(pnv)) { - _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat9, - sizeof(plat_compat9)))); - } else { - _FDT((fdt_setprop(fdt, 0, "compatible", plat_compat8, - sizeof(plat_compat8)))); - } - + _FDT((fdt_setprop(fdt, 0, "compatible", pmc->compat, + sizeof(pmc->compat)))); =20 buf =3D qemu_uuid_unparse_strdup(&qemu_uuid); _FDT((fdt_setprop_string(fdt, 0, "vm,uuid", buf))); @@ -1692,6 +1681,8 @@ static void pnv_machine_power8_class_init(ObjectClass= *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); XICSFabricClass *xic =3D XICS_FABRIC_CLASS(oc); + PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + static const char compat[] =3D "qemu,powernv8\0qemu,powernv\0ibm,power= nv"; =20 mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER8"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); @@ -1699,26 +1690,39 @@ static void pnv_machine_power8_class_init(ObjectCla= ss *oc, void *data) xic->icp_get =3D pnv_icp_get; xic->ics_get =3D pnv_ics_get; xic->ics_resend =3D pnv_ics_resend; + + pmc->compat =3D compat; + pmc->compat_size =3D sizeof(compat); } =20 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); + PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + static const char compat[] =3D "qemu,powernv9\0ibm,powernv"; =20 mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); xfc->match_nvt =3D pnv_match_nvt; =20 mc->alias =3D "powernv"; + + pmc->compat =3D compat; + pmc->compat_size =3D sizeof(compat); } =20 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); + PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); + static const char compat[] =3D "qemu,powernv10\0ibm,powernv"; =20 mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER10"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power10_v1.0"); + + pmc->compat =3D compat; + pmc->compat_size =3D sizeof(compat); } =20 static void pnv_machine_class_init(ObjectClass *oc, void *data) @@ -1796,6 +1800,7 @@ static const TypeInfo types[] =3D { .instance_size =3D sizeof(PnvMachineState), .instance_init =3D pnv_machine_instance_init, .class_init =3D pnv_machine_class_init, + .class_size =3D sizeof(PnvMachineClass), .interfaces =3D (InterfaceInfo[]) { { TYPE_INTERRUPT_STATS_PROVIDER }, { }, diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 92f80b1ccead..d534746bd493 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -185,6 +185,19 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t = pir); #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") #define PNV_MACHINE(obj) \ OBJECT_CHECK(PnvMachineState, (obj), TYPE_PNV_MACHINE) +#define PNV_MACHINE_GET_CLASS(obj) \ + OBJECT_GET_CLASS(PnvMachineClass, obj, TYPE_PNV_MACHINE) +#define PNV_MACHINE_CLASS(klass) \ + OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) + +typedef struct PnvMachineClass { + /*< private >*/ + MachineClass parent_class; + + /*< public >*/ + const char *compat; + int compat_size; +} PnvMachineClass; =20 typedef struct PnvMachineState { /*< private >*/ From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576239092; cv=none; d=zohomail.com; s=zohoarc; b=h2FRtgHBQwXuyoj1iBHwUFfndXk4Hq8S1VY/xW3XrjzpQQE4WSMs2BQt24PwhE8pEbb2oJ4QnxGBS4CMcNQZqH8+/vaSM5SZ3WlguRn0LuIPTEQose0B+EnSZoOgyoRVTSh1e+2hbJfjl4wihdMsg+9QxkqmEnhL+BJKxVeEvNs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576239092; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 11:59:57 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDBxvcK50331858 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 11:59:57 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 006C511C04C; Fri, 13 Dec 2019 11:59:57 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C35CD11C04A; Fri, 13 Dec 2019 11:59:56 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 11:59:56 +0000 (GMT) Subject: [PATCH 05/13] ppc/pnv: Introduce PnvMachineClass::dt_power_mgt() From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 12:59:56 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121311-0020-0000-0000-00000397C4C3 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121311-0021-0000-0000-000021EED233 Message-Id: <157623839642.360005.9243510140436689941.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 clxscore=1034 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 mlxlogscore=847 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" We add an extra node to advertise power management on some machines, namely powernv9 and powernv10. This is achieved by using the pnv_is_power9() and pnv_is_power10() helpers. This can be achieved with QOM. Add a method to the base class for powernv machines and have it implemented by machine types that support power management instead. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 10 ++++++---- include/hw/ppc/pnv.h | 8 ++++++-- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 5ac149b149d8..efc00f4cb67a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -472,7 +472,7 @@ static void pnv_dt_isa(PnvMachineState *pnv, void *fdt) &args); } =20 -static void pnv_dt_power_mgt(void *fdt) +static void pnv_dt_power_mgt(PnvMachineState *pnv, void *fdt) { int off; =20 @@ -540,9 +540,9 @@ static void *pnv_dt_create(MachineState *machine) pnv_dt_bmc_sensors(pnv->bmc, fdt); } =20 - /* Create an extra node for power management on Power9 and Power10 */ - if (pnv_is_power9(pnv) || pnv_is_power10(pnv)) { - pnv_dt_power_mgt(fdt); + /* Create an extra node for power management on machines that support = it */ + if (pmc->dt_power_mgt) { + pmc->dt_power_mgt(pnv, fdt); } =20 return fdt; @@ -1710,6 +1710,7 @@ static void pnv_machine_power9_class_init(ObjectClass= *oc, void *data) =20 pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); + pmc->dt_power_mgt =3D pnv_dt_power_mgt; } =20 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) @@ -1723,6 +1724,7 @@ static void pnv_machine_power10_class_init(ObjectClas= s *oc, void *data) =20 pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); + pmc->dt_power_mgt =3D pnv_dt_power_mgt; } =20 static void pnv_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index d534746bd493..8a42c199b65c 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -190,6 +190,8 @@ PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t p= ir); #define PNV_MACHINE_CLASS(klass) \ OBJECT_CLASS_CHECK(PnvMachineClass, klass, TYPE_PNV_MACHINE) =20 +typedef struct PnvMachineState PnvMachineState; + typedef struct PnvMachineClass { /*< private >*/ MachineClass parent_class; @@ -197,9 +199,11 @@ typedef struct PnvMachineClass { /*< public >*/ const char *compat; int compat_size; + + void (*dt_power_mgt)(PnvMachineState *pnv, void *fdt); } PnvMachineClass; =20 -typedef struct PnvMachineState { +struct PnvMachineState { /*< private >*/ MachineState parent_obj; =20 @@ -216,7 +220,7 @@ typedef struct PnvMachineState { Notifier powerdown_notifier; =20 PnvPnor *pnor; -} PnvMachineState; +}; =20 static inline bool pnv_chip_is_power9(const PnvChip *chip) { From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576239172; cv=none; d=zohomail.com; s=zohoarc; b=i7hItVhPfSheN0bXTQjOcq+sVOp8y4G0ciz2e6yRsm90GMqlakf0OxKv4/zXOI0BVKIp6ajplt8ooE3rArdZz01ylyb6uUe0mVdTHupW6iZpmYoe65RfRyDuxjUiqxzsfSZFip+oLUAfJ6JtmXGN7mYzMLqfG6AiDgTYcdWz4Jk= ARC-Message-Signature: i=1; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:03 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDBxKJc40632722 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 11:59:20 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 871FEAE051; Fri, 13 Dec 2019 12:00:02 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 58CC8AE055; Fri, 13 Dec 2019 12:00:02 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 12:00:02 +0000 (GMT) Subject: [PATCH 06/13] ppc/pnv: Drop pnv_is_power9() and pnv_is_power10() helpers From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:02 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0028-0000-0000-000003C82A4A X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0029-0000-0000-0000248B678B Message-Id: <157623840200.360005.1300941274565357363.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 clxscore=1034 suspectscore=0 adultscore=0 mlxlogscore=906 phishscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" They aren't used anymore. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 8a42c199b65c..c213bdd5ecd3 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -227,11 +227,6 @@ static inline bool pnv_chip_is_power9(const PnvChip *c= hip) return PNV_CHIP_GET_CLASS(chip)->chip_type =3D=3D PNV_CHIP_POWER9; } =20 -static inline bool pnv_is_power9(PnvMachineState *pnv) -{ - return pnv_chip_is_power9(pnv->chips[0]); -} - PnvChip *pnv_get_chip(uint32_t chip_id); =20 #define PNV_FDT_ADDR 0x01000000 @@ -242,11 +237,6 @@ static inline bool pnv_chip_is_power10(const PnvChip *= chip) return PNV_CHIP_GET_CLASS(chip)->chip_type =3D=3D PNV_CHIP_POWER10; } =20 -static inline bool pnv_is_power10(PnvMachineState *pnv) -{ - return pnv_chip_is_power10(pnv->chips[0]); -} - /* * BMC helpers */ From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576239344; cv=none; d=zohomail.com; s=zohoarc; b=Yal+I1t4RRnGJpH4gXgCgKjXPSKO8Txuf8Z1jxJS3Kd2DevUciTZGZVry0aO4AuLcnxs3MpMuwzhGxYkPAKIpcheZCj00II7iAAsmJhR18zdidLKdRrpAoxg9vnhYRzWu0pAKrzMy8DAhe+6HYq9WTX7DUtAfhvoBQSrdktW0Qk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576239344; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=o8Hz5ePiw9Rx4qYZo7jlL3rB0zzcpvl+WoPPMVg2dq4=; b=SqxD1RsWjT2zgOpA/ybWkufJgXSD89vrqhqfCfhFrtLYjtWVV0ftQv3VQju4OS3gU5bIcxu3c1Rbk6YaTgwWcf4pZcWuM4HU/Z/3t0N0mQmTEfY+KxdNIqjEDoV36sKIo5z+MaDCYefevqlU2uUYyhDsVAhGZm9rEXpOMS2zmzo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576239344684566.4332466156947; Fri, 13 Dec 2019 04:15:44 -0800 (PST) Received: from localhost ([::1]:48252 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifjrD-0008C8-5r for importer@patchew.org; Fri, 13 Dec 2019 07:15:43 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:34810) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifjcH-0007YS-N9 for qemu-devel@nongnu.org; Fri, 13 Dec 2019 07:00:19 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifjcG-0004Xd-4o for qemu-devel@nongnu.org; Fri, 13 Dec 2019 07:00:17 -0500 Received: from mx0a-001b2d01.pphosted.com ([148.163.156.1]:27654) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifjcF-0004Vk-RL for qemu-devel@nongnu.org; Fri, 13 Dec 2019 07:00:16 -0500 Received: from pps.filterd (m0098404.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBDBuvPT002806 for ; Fri, 13 Dec 2019 07:00:14 -0500 Received: from e06smtp04.uk.ibm.com (e06smtp04.uk.ibm.com [195.75.94.100]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wupyt0nj1-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 13 Dec 2019 07:00:14 -0500 Received: from localhost by e06smtp04.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:09 -0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDC083757999486 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 12:00:08 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 133A9A4068; Fri, 13 Dec 2019 12:00:08 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id E0F7AA4064; Fri, 13 Dec 2019 12:00:07 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 12:00:07 +0000 (GMT) Subject: [PATCH 07/13] ppc/pnv: Introduce PnvChipClass::intc_print_info() method From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:07 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0016-0000-0000-000002D47154 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0017-0000-0000-000033369CBB Message-Id: <157623840755.360005.5002022339473369934.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1034 adultscore=0 mlxlogscore=810 priorityscore=1501 impostorscore=0 phishscore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The pnv_pic_print_info() callback checks the type of the chip in order to forward to the request appropriate interrupt controller. This can be achieved with QOM. Introduce a method for this in the base chip class and implement it in child classes. This also prepares ground for the upcoming interrupt controller of POWER10 chips. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 30 +++++++++++++++++++++++++----- include/hw/ppc/pnv.h | 1 + 2 files changed, 26 insertions(+), 5 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index efc00f4cb67a..2a53e99bda2e 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -832,6 +832,12 @@ static void pnv_chip_power8_intc_destroy(PnvChip *chip= , PowerPCCPU *cpu) pnv_cpu->intc =3D NULL; } =20 +static void pnv_chip_power8_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, + Monitor *mon) +{ + icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); +} + /* * 0:48 Reserved - Read as zeroes * 49:52 Node ID @@ -889,6 +895,12 @@ static void pnv_chip_power9_intc_destroy(PnvChip *chip= , PowerPCCPU *cpu) pnv_cpu->intc =3D NULL; } =20 +static void pnv_chip_power9_intc_print_info(PnvChip *chip, PowerPCCPU *cpu, + Monitor *mon) +{ + xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), mon); +} + static void pnv_chip_power10_intc_create(PnvChip *chip, PowerPCCPU *cpu, Error **errp) { @@ -910,6 +922,11 @@ static void pnv_chip_power10_intc_destroy(PnvChip *chi= p, PowerPCCPU *cpu) pnv_cpu->intc =3D NULL; } =20 +static void pnv_chip_power10_intc_print_info(PnvChip *chip, PowerPCCPU *cp= u, + Monitor *mon) +{ +} + /* * Allowed core identifiers on a POWER8 Processor Chip : * @@ -1086,6 +1103,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; + k->intc_print_info =3D pnv_chip_power8_intc_print_info; k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; @@ -1107,6 +1125,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; + k->intc_print_info =3D pnv_chip_power8_intc_print_info; k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; @@ -1128,6 +1147,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->intc_create =3D pnv_chip_power8_intc_create; k->intc_reset =3D pnv_chip_power8_intc_reset; k->intc_destroy =3D pnv_chip_power8_intc_destroy; + k->intc_print_info =3D pnv_chip_power8_intc_print_info; k->isa_create =3D pnv_chip_power8nvl_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; @@ -1299,6 +1319,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->intc_create =3D pnv_chip_power9_intc_create; k->intc_reset =3D pnv_chip_power9_intc_reset; k->intc_destroy =3D pnv_chip_power9_intc_destroy; + k->intc_print_info =3D pnv_chip_power9_intc_print_info; k->isa_create =3D pnv_chip_power9_isa_create; k->dt_populate =3D pnv_chip_power9_dt_populate; k->pic_print_info =3D pnv_chip_power9_pic_print_info; @@ -1379,6 +1400,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) k->intc_create =3D pnv_chip_power10_intc_create; k->intc_reset =3D pnv_chip_power10_intc_reset; k->intc_destroy =3D pnv_chip_power10_intc_destroy; + k->intc_print_info =3D pnv_chip_power10_intc_print_info; k->isa_create =3D pnv_chip_power10_isa_create; k->dt_populate =3D pnv_chip_power10_dt_populate; k->pic_print_info =3D pnv_chip_power10_pic_print_info; @@ -1575,11 +1597,9 @@ static void pnv_pic_print_info(InterruptStatsProvide= r *obj, CPU_FOREACH(cs) { PowerPCCPU *cpu =3D POWERPC_CPU(cs); =20 - if (pnv_chip_is_power9(pnv->chips[0])) { - xive_tctx_pic_print_info(XIVE_TCTX(pnv_cpu_state(cpu)->intc), = mon); - } else { - icp_pic_print_info(ICP(pnv_cpu_state(cpu)->intc), mon); - } + /* XXX: loop on each chip/core/thread instead of CPU_FOREACH() */ + PNV_CHIP_GET_CLASS(pnv->chips[0])->intc_print_info(pnv->chips[0], = cpu, + mon); } =20 for (i =3D 0; i < pnv->num_chips; i++) { diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index c213bdd5ecd3..7d2402784d4b 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -133,6 +133,7 @@ typedef struct PnvChipClass { void (*intc_create)(PnvChip *chip, PowerPCCPU *cpu, Error **errp); void (*intc_reset)(PnvChip *chip, PowerPCCPU *cpu); void (*intc_destroy)(PnvChip *chip, PowerPCCPU *cpu); + void (*intc_print_info)(PnvChip *chip, PowerPCCPU *cpu, Monitor *mon); ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576238796; cv=none; d=zohomail.com; s=zohoarc; b=oECdzMi+TdW7gYh+LcNUzSu6NLK+FjKPUHNY+CFMvRiHy1Ixzypa96loTvT3fKgThWTmPgcK+oFSplh76M1HYUYo1gonq386jJz891adi1J5Jd4cjN8L1QUNkHyQSgeYz7Jiemxde6O7rKLV2bI9XeBq9Ak5mrRnDz4FY18nuSw= ARC-Message-Signature: i=1; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:15 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDC0EDS51249306 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 12:00:14 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A7A2352069; Fri, 13 Dec 2019 12:00:13 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 6F6B35207E; Fri, 13 Dec 2019 12:00:13 +0000 (GMT) Subject: [PATCH 08/13] ppc/pnv: Introduce PnvChipClass::xscom_core_base() method From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:13 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0020-0000-0000-00000397C4CB X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0021-0000-0000-000021EED23C Message-Id: <157623841311.360005.4705705734873339545.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 clxscore=1034 mlxlogscore=999 impostorscore=0 suspectscore=0 bulkscore=0 adultscore=0 lowpriorityscore=0 spamscore=0 priorityscore=1501 malwarescore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The pnv_chip_core_realize() function configures the XSCOM MMIO subregion for each core of a single chip. The base address of the subregion depends on the CPU type. Its computation is currently open-code using the pnv_chip_is_powerXX() helpers. This can be achieved with QOM. Introduce a method for this in the base chip class and implement it in child classes. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 31 ++++++++++++++++++++++++------- include/hw/ppc/pnv.h | 1 + 2 files changed, 25 insertions(+), 7 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 2a53e99bda2e..88efa755e611 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -616,6 +616,24 @@ static void pnv_chip_power9_pic_print_info(PnvChip *ch= ip, Monitor *mon) pnv_psi_pic_print_info(&chip9->psi, mon); } =20 +static uint64_t pnv_chip_power8_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV_XSCOM_EX_BASE(core_id); +} + +static uint64_t pnv_chip_power9_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV9_XSCOM_EC_BASE(core_id); +} + +static uint64_t pnv_chip_power10_xscom_core_base(PnvChip *chip, + uint32_t core_id) +{ + return PNV10_XSCOM_EC_BASE(core_id); +} + static bool pnv_match_cpu(const char *default_type, const char *cpu_type) { PowerPCCPUClass *ppc_default =3D @@ -1107,6 +1125,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; + k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; dc->desc =3D "PowerNV Chip POWER8E"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1129,6 +1148,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->isa_create =3D pnv_chip_power8_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; + k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; dc->desc =3D "PowerNV Chip POWER8"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1151,6 +1171,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->isa_create =3D pnv_chip_power8nvl_isa_create; k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; + k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; dc->desc =3D "PowerNV Chip POWER8NVL"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1323,6 +1344,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->isa_create =3D pnv_chip_power9_isa_create; k->dt_populate =3D pnv_chip_power9_dt_populate; k->pic_print_info =3D pnv_chip_power9_pic_print_info; + k->xscom_core_base =3D pnv_chip_power9_xscom_core_base; dc->desc =3D "PowerNV Chip POWER9"; =20 device_class_set_parent_realize(dc, pnv_chip_power9_realize, @@ -1404,6 +1426,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) k->isa_create =3D pnv_chip_power10_isa_create; k->dt_populate =3D pnv_chip_power10_dt_populate; k->pic_print_info =3D pnv_chip_power10_pic_print_info; + k->xscom_core_base =3D pnv_chip_power10_xscom_core_base; dc->desc =3D "PowerNV Chip POWER10"; =20 device_class_set_parent_realize(dc, pnv_chip_power10_realize, @@ -1491,13 +1514,7 @@ static void pnv_chip_core_realize(PnvChip *chip, Err= or **errp) &error_fatal); =20 /* Each core has an XSCOM MMIO region */ - if (pnv_chip_is_power10(chip)) { - xscom_core_base =3D PNV10_XSCOM_EC_BASE(core_hwid); - } else if (pnv_chip_is_power9(chip)) { - xscom_core_base =3D PNV9_XSCOM_EC_BASE(core_hwid); - } else { - xscom_core_base =3D PNV_XSCOM_EX_BASE(core_hwid); - } + xscom_core_base =3D pcc->xscom_core_base(chip, core_hwid); =20 pnv_xscom_add_subregion(chip, xscom_core_base, &pnv_core->xscom_regs); diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7d2402784d4b..17ca9a14ac8f 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -137,6 +137,7 @@ typedef struct PnvChipClass { ISABus *(*isa_create)(PnvChip *chip, Error **errp); void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); + uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); } PnvChipClass; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:22 -0000 Received: from d06av22.portsmouth.uk.ibm.com (d06av22.portsmouth.uk.ibm.com [9.149.105.58]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDC0L8R15335494 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 12:00:21 GMT Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4040F4C06E; Fri, 13 Dec 2019 12:00:19 +0000 (GMT) Received: from d06av22.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 17C084C07E; Fri, 13 Dec 2019 12:00:19 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av22.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 12:00:19 +0000 (GMT) Subject: [PATCH 09/13] ppc/pnv: Pass XSCOM base address and address size to pnv_dt_xscom() From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:18 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0016-0000-0000-000002D47158 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0017-0000-0000-000033369CC0 Message-Id: <157623841868.360005.17577624823547136435.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 clxscore=1034 mlxlogscore=999 malwarescore=0 phishscore=0 spamscore=0 bulkscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "reg" property. Just pass the base address and address size as arguments. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 12 +++++++++--- hw/ppc/pnv_xscom.c | 16 +++------------- include/hw/ppc/pnv_xscom.h | 3 ++- 3 files changed, 14 insertions(+), 17 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 88efa755e611..c532e98e752a 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -282,7 +282,9 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip, = void *fdt) { int i; =20 - pnv_dt_xscom(chip, fdt, 0); + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV_XSCOM_BASE(chip)), + cpu_to_be64(PNV_XSCOM_SIZE)); =20 for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D chip->cores[i]; @@ -302,7 +304,9 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip, = void *fdt) { int i; =20 - pnv_dt_xscom(chip, fdt, 0); + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV9_XSCOM_BASE(chip)), + cpu_to_be64(PNV9_XSCOM_SIZE)); =20 for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D chip->cores[i]; @@ -321,7 +325,9 @@ static void pnv_chip_power10_dt_populate(PnvChip *chip,= void *fdt) { int i; =20 - pnv_dt_xscom(chip, fdt, 0); + pnv_dt_xscom(chip, fdt, 0, + cpu_to_be64(PNV10_XSCOM_BASE(chip)), + cpu_to_be64(PNV10_XSCOM_SIZE)); =20 for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D chip->cores[i]; diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index df926003f2ba..8189767eb0bb 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -286,24 +286,14 @@ static const char compat_p8[] =3D "ibm,power8-xscom\0= ibm,xscom"; static const char compat_p9[] =3D "ibm,power9-xscom\0ibm,xscom"; static const char compat_p10[] =3D "ibm,power10-xscom\0ibm,xscom"; =20 -int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset) +int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, + uint64_t xscom_base, uint64_t xscom_size) { - uint64_t reg[2]; + uint64_t reg[] =3D { xscom_base, xscom_size }; int xscom_offset; ForeachPopulateArgs args; char *name; =20 - if (pnv_chip_is_power10(chip)) { - reg[0] =3D cpu_to_be64(PNV10_XSCOM_BASE(chip)); - reg[1] =3D cpu_to_be64(PNV10_XSCOM_SIZE); - } else if (pnv_chip_is_power9(chip)) { - reg[0] =3D cpu_to_be64(PNV9_XSCOM_BASE(chip)); - reg[1] =3D cpu_to_be64(PNV9_XSCOM_SIZE); - } else { - reg[0] =3D cpu_to_be64(PNV_XSCOM_BASE(chip)); - reg[1] =3D cpu_to_be64(PNV_XSCOM_SIZE); - } - name =3D g_strdup_printf("xscom@%" PRIx64, be64_to_cpu(reg[0])); xscom_offset =3D fdt_add_subnode(fdt, root_offset, name); _FDT(xscom_offset); diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index 2bdb7ae84fd3..ad53f788b44c 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -114,7 +114,8 @@ typedef struct PnvXScomInterfaceClass { #define PNV10_XSCOM_PSIHB_SIZE 0x100 =20 void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); -int pnv_dt_xscom(PnvChip *chip, void *fdt, int offset); +int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, + uint64_t xscom_base, uint64_t xscom_size); =20 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr); From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:26 -0000 Received: from d06av23.portsmouth.uk.ibm.com (d06av23.portsmouth.uk.ibm.com [9.149.105.59]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDC0Pjr36045302 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 12:00:25 GMT Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C80C6A4055; Fri, 13 Dec 2019 12:00:24 +0000 (GMT) Received: from d06av23.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A31E5A4051; Fri, 13 Dec 2019 12:00:24 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av23.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 12:00:24 +0000 (GMT) Subject: [PATCH 10/13] ppc/pnv: Pass content of the "compatible" property to pnv_dt_xscom() From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:24 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0012-0000-0000-000003747166 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0013-0000-0000-000021B050E5 Message-Id: <157623842430.360005.9513965612524265862.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 bulkscore=0 adultscore=0 clxscore=1034 spamscore=0 malwarescore=0 phishscore=0 impostorscore=0 mlxscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Since pnv_dt_xscom() is called from chip specific dt_populate() hooks, it shouldn't have to guess the chip type in order to populate the "compatible" property. Just pass the compat string and its size as arguments. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 12 +++++++++--- hw/ppc/pnv_xscom.c | 20 +++----------------- include/hw/ppc/pnv_xscom.h | 3 ++- 3 files changed, 14 insertions(+), 21 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index c532e98e752a..0447b534b8c5 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -280,11 +280,13 @@ static void pnv_dt_icp(PnvChip *chip, void *fdt, uint= 32_t pir, =20 static void pnv_chip_power8_dt_populate(PnvChip *chip, void *fdt) { + static const char compat[] =3D "ibm,power8-xscom\0ibm,xscom"; int i; =20 pnv_dt_xscom(chip, fdt, 0, cpu_to_be64(PNV_XSCOM_BASE(chip)), - cpu_to_be64(PNV_XSCOM_SIZE)); + cpu_to_be64(PNV_XSCOM_SIZE), + compat, sizeof(compat)); =20 for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D chip->cores[i]; @@ -302,11 +304,13 @@ static void pnv_chip_power8_dt_populate(PnvChip *chip= , void *fdt) =20 static void pnv_chip_power9_dt_populate(PnvChip *chip, void *fdt) { + static const char compat[] =3D "ibm,power9-xscom\0ibm,xscom"; int i; =20 pnv_dt_xscom(chip, fdt, 0, cpu_to_be64(PNV9_XSCOM_BASE(chip)), - cpu_to_be64(PNV9_XSCOM_SIZE)); + cpu_to_be64(PNV9_XSCOM_SIZE), + compat, sizeof(compat)); =20 for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D chip->cores[i]; @@ -323,11 +327,13 @@ static void pnv_chip_power9_dt_populate(PnvChip *chip= , void *fdt) =20 static void pnv_chip_power10_dt_populate(PnvChip *chip, void *fdt) { + static const char compat[] =3D "ibm,power10-xscom\0ibm,xscom"; int i; =20 pnv_dt_xscom(chip, fdt, 0, cpu_to_be64(PNV10_XSCOM_BASE(chip)), - cpu_to_be64(PNV10_XSCOM_SIZE)); + cpu_to_be64(PNV10_XSCOM_SIZE), + compat, sizeof(compat)); =20 for (i =3D 0; i < chip->nr_cores; i++) { PnvCore *pnv_core =3D chip->cores[i]; diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 8189767eb0bb..5ae9dfbb88ad 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -282,12 +282,9 @@ static int xscom_dt_child(Object *child, void *opaque) return 0; } =20 -static const char compat_p8[] =3D "ibm,power8-xscom\0ibm,xscom"; -static const char compat_p9[] =3D "ibm,power9-xscom\0ibm,xscom"; -static const char compat_p10[] =3D "ibm,power10-xscom\0ibm,xscom"; - int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, - uint64_t xscom_base, uint64_t xscom_size) + uint64_t xscom_base, uint64_t xscom_size, + const char *compat, int compat_size) { uint64_t reg[] =3D { xscom_base, xscom_size }; int xscom_offset; @@ -302,18 +299,7 @@ int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_of= fset, _FDT((fdt_setprop_cell(fdt, xscom_offset, "#address-cells", 1))); _FDT((fdt_setprop_cell(fdt, xscom_offset, "#size-cells", 1))); _FDT((fdt_setprop(fdt, xscom_offset, "reg", reg, sizeof(reg)))); - - if (pnv_chip_is_power10(chip)) { - _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p10, - sizeof(compat_p10)))); - } else if (pnv_chip_is_power9(chip)) { - _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p9, - sizeof(compat_p9)))); - } else { - _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat_p8, - sizeof(compat_p8)))); - } - + _FDT((fdt_setprop(fdt, xscom_offset, "compatible", compat, compat_size= ))); _FDT((fdt_setprop(fdt, xscom_offset, "scom-controller", NULL, 0))); =20 args.fdt =3D fdt; diff --git a/include/hw/ppc/pnv_xscom.h b/include/hw/ppc/pnv_xscom.h index ad53f788b44c..f74c81a980f3 100644 --- a/include/hw/ppc/pnv_xscom.h +++ b/include/hw/ppc/pnv_xscom.h @@ -115,7 +115,8 @@ typedef struct PnvXScomInterfaceClass { =20 void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp); int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset, - uint64_t xscom_base, uint64_t xscom_size); + uint64_t xscom_base, uint64_t xscom_size, + const char *compat, int compat_size); =20 void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset, MemoryRegion *mr); From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:32 -0000 Received: from d06av24.portsmouth.uk.ibm.com (mk.ibm.com [9.149.105.60]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDC0V2a34472352 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 12:00:31 GMT Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5EEA242042; Fri, 13 Dec 2019 12:00:30 +0000 (GMT) Received: from d06av24.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 38DA94204C; Fri, 13 Dec 2019 12:00:30 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av24.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 12:00:30 +0000 (GMT) Subject: [PATCH 11/13] ppc/pnv: Drop pnv_chip_is_power9() and pnv_chip_is_power10() helpers From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:29 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0008-0000-0000-00000340728E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0009-0000-0000-00004A607875 Message-Id: <157623842986.360005.1787401623906380181.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=916 lowpriorityscore=0 priorityscore=1501 impostorscore=0 malwarescore=0 phishscore=0 bulkscore=0 clxscore=1034 adultscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.156.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" They aren't used anymore. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- include/hw/ppc/pnv.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 17ca9a14ac8f..7a134a15d3b5 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -224,21 +224,11 @@ struct PnvMachineState { PnvPnor *pnor; }; =20 -static inline bool pnv_chip_is_power9(const PnvChip *chip) -{ - return PNV_CHIP_GET_CLASS(chip)->chip_type =3D=3D PNV_CHIP_POWER9; -} - PnvChip *pnv_get_chip(uint32_t chip_id); =20 #define PNV_FDT_ADDR 0x01000000 #define PNV_TIMEBASE_FREQ 512000000ULL =20 -static inline bool pnv_chip_is_power10(const PnvChip *chip) -{ - return PNV_CHIP_GET_CLASS(chip)->chip_type =3D=3D PNV_CHIP_POWER10; -} - /* * BMC helpers */ From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1576238961; cv=none; d=zohomail.com; s=zohoarc; b=PCyfh80cWfhpsG+DLhcfbo0+t/azgCFZ+uqHmSZ9tNVMyS/SUzM2kOgXJdDaErEuYYDcWDuV2lTgTOwPnSjpWqyTlIOoVUAVN6/91/YPMBclKYhHLJ+bURiXiH/gpGX/ChIdCyn1uLAiBlqUC6Nb5PP1cTdIkoOeUKZGH5rVzOs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1576238961; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q6WjJ9hNWQu1AyfT47RivNjsoPLKvIqut9Jk+gvY6YI=; b=Bu2yL8IEMX/ctALXoLep8Wth9MjDJ1OdgVjOpoxANVCJD5uAmdRA/nfDXYzKov8Fwbc2MJuVzPFaTh7ScqooFy54Xqn7TE9RKbVXAig8HdjpyxmQYztqEqs3Cx0YZKYFQAxvOBd9mn65lIeA0WqiUQT5cU7bYkH1IjRzxyP23ow= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1576238961674124.01755637223346; Fri, 13 Dec 2019 04:09:21 -0800 (PST) Received: from localhost ([::1]:48166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifjl1-00008I-Qe for importer@patchew.org; Fri, 13 Dec 2019 07:09:19 -0500 Received: from eggs.gnu.org ([2001:470:142:3::10]:38612) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ifjci-00085Q-W1 for qemu-devel@nongnu.org; Fri, 13 Dec 2019 07:00:46 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1ifjch-0005Fj-B8 for qemu-devel@nongnu.org; Fri, 13 Dec 2019 07:00:44 -0500 Received: from mx0b-001b2d01.pphosted.com ([148.163.158.5]:26324 helo=mx0a-001b2d01.pphosted.com) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1ifjch-0005FJ-4c for qemu-devel@nongnu.org; Fri, 13 Dec 2019 07:00:43 -0500 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id xBDBv6an061012 for ; Fri, 13 Dec 2019 07:00:42 -0500 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0a-001b2d01.pphosted.com with ESMTP id 2wujxsc4uv-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Fri, 13 Dec 2019 07:00:42 -0500 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:37 -0000 Received: from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com [9.149.105.61]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDBxrJL50462988 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 11:59:54 GMT Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0742111C05E; Fri, 13 Dec 2019 12:00:36 +0000 (GMT) Received: from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C9AA911C06F; Fri, 13 Dec 2019 12:00:35 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 12:00:35 +0000 (GMT) Subject: [PATCH 12/13] ppc/pnv: Introduce PnvChipClass::xscom_pcba() method From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:35 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0028-0000-0000-000003C82A54 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0029-0000-0000-0000248B6796 Message-Id: <157623843543.360005.13996472463887521794.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=884 impostorscore=0 priorityscore=1501 clxscore=1034 suspectscore=0 bulkscore=0 spamscore=0 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" The XSCOM bus is implemented with a QOM interface, which is mostly generic from a CPU type standpoint, except for the computation of addresses on the Pervasize Connect Bus (PCB) network. This is handled by the pnv_xscom_pcba() function with a switch statement based on the chip_type class level attribute of the CPU chip. This can be achieved using QOM. Also the address argument is masked with PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different sizes with other CPU types. Have each CPU chip type handle the appropriate computation with a QOM xscom_pcba() method. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 23 +++++++++++++++++++++++ hw/ppc/pnv_xscom.c | 14 +------------- include/hw/ppc/pnv.h | 1 + 3 files changed, 25 insertions(+), 13 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 0447b534b8c5..cc40b90e9cd2 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1121,6 +1121,12 @@ static void pnv_chip_power8_realize(DeviceState *dev= , Error **errp) &chip8->homer.regs); } =20 +static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &=3D (PNV_XSCOM_SIZE - 1); + return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); +} + static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -1138,6 +1144,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power8_xscom_pcba; dc->desc =3D "PowerNV Chip POWER8E"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1161,6 +1168,7 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power8_xscom_pcba; dc->desc =3D "PowerNV Chip POWER8"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1184,6 +1192,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) k->dt_populate =3D pnv_chip_power8_dt_populate; k->pic_print_info =3D pnv_chip_power8_pic_print_info; k->xscom_core_base =3D pnv_chip_power8_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power8_xscom_pcba; dc->desc =3D "PowerNV Chip POWER8NVL"; =20 device_class_set_parent_realize(dc, pnv_chip_power8_realize, @@ -1340,6 +1349,12 @@ static void pnv_chip_power9_realize(DeviceState *dev= , Error **errp) &chip9->homer.regs); } =20 +static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &=3D (PNV9_XSCOM_SIZE - 1); + return addr >> 3; +} + static void pnv_chip_power9_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -1357,6 +1372,7 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) k->dt_populate =3D pnv_chip_power9_dt_populate; k->pic_print_info =3D pnv_chip_power9_pic_print_info; k->xscom_core_base =3D pnv_chip_power9_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power9_xscom_pcba; dc->desc =3D "PowerNV Chip POWER9"; =20 device_class_set_parent_realize(dc, pnv_chip_power9_realize, @@ -1422,6 +1438,12 @@ static void pnv_chip_power10_realize(DeviceState *de= v, Error **errp) (uint64_t) PNV10_LPCM_BASE(chi= p)); } =20 +static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr) +{ + addr &=3D (PNV10_XSCOM_SIZE - 1); + return addr >> 3; +} + static void pnv_chip_power10_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); @@ -1439,6 +1461,7 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) k->dt_populate =3D pnv_chip_power10_dt_populate; k->pic_print_info =3D pnv_chip_power10_pic_print_info; k->xscom_core_base =3D pnv_chip_power10_xscom_core_base; + k->xscom_pcba =3D pnv_chip_power10_xscom_pcba; dc->desc =3D "PowerNV Chip POWER10"; =20 device_class_set_parent_realize(dc, pnv_chip_power10_realize, diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c index 5ae9dfbb88ad..b681c72575b2 100644 --- a/hw/ppc/pnv_xscom.c +++ b/hw/ppc/pnv_xscom.c @@ -57,19 +57,7 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_b= its) =20 static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr) { - addr &=3D (PNV_XSCOM_SIZE - 1); - - switch (PNV_CHIP_GET_CLASS(chip)->chip_type) { - case PNV_CHIP_POWER8E: - case PNV_CHIP_POWER8: - case PNV_CHIP_POWER8NVL: - return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf); - case PNV_CHIP_POWER9: - case PNV_CHIP_POWER10: - return addr >> 3; - default: - g_assert_not_reached(); - } + return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr); } =20 static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 7a134a15d3b5..4972e93c2619 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -138,6 +138,7 @@ typedef struct PnvChipClass { void (*dt_populate)(PnvChip *chip, void *fdt); void (*pic_print_info)(PnvChip *chip, Monitor *mon); uint64_t (*xscom_core_base)(PnvChip *chip, uint32_t core_id); + uint32_t (*xscom_pcba)(PnvChip *chip, uint64_t addr); } PnvChipClass; =20 #define PNV_CHIP_TYPE_SUFFIX "-" TYPE_PNV_CHIP From nobody Sun Apr 28 21:16:39 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Fri, 13 Dec 2019 12:00:42 -0000 Received: from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com [9.149.105.62]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id xBDC0fpQ30867664 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Fri, 13 Dec 2019 12:00:41 GMT Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8EBB0AE058; Fri, 13 Dec 2019 12:00:41 +0000 (GMT) Received: from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 601D8AE04D; Fri, 13 Dec 2019 12:00:41 +0000 (GMT) Received: from bahia.lan (unknown [9.145.185.241]) by d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP; Fri, 13 Dec 2019 12:00:41 +0000 (GMT) Subject: [PATCH 13/13] ppc/pnv: Drop PnvChipClass::type From: Greg Kurz To: David Gibson Date: Fri, 13 Dec 2019 13:00:41 +0100 In-Reply-To: <157623836852.360005.1112241220707384093.stgit@bahia.lan> References: <157623836852.360005.1112241220707384093.stgit@bahia.lan> User-Agent: StGit/unknown-version MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 x-cbid: 19121312-0020-0000-0000-00000397C4D0 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19121312-0021-0000-0000-000021EED241 Message-Id: <157623844102.360005.12070225703151669294.stgit@bahia.lan> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.95,18.0.572 definitions=2019-12-13_03:2019-12-13,2019-12-13 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 priorityscore=1501 adultscore=0 clxscore=1034 malwarescore=0 suspectscore=0 impostorscore=0 bulkscore=0 phishscore=0 spamscore=0 mlxscore=0 mlxlogscore=868 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-1910280000 definitions=main-1912130097 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 148.163.158.5 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, =?utf-8?q?C=C3=A9dric?= Le Goater , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" It isn't used anymore. Signed-off-by: Greg Kurz Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/pnv.c | 5 ----- include/hw/ppc/pnv.h | 9 --------- 2 files changed, 14 deletions(-) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index cc40b90e9cd2..232b4a25603c 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1132,7 +1132,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *= klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->chip_type =3D PNV_CHIP_POWER8E; k->chip_cfam_id =3D 0x221ef04980000000ull; /* P8 Murano DD2.1 */ k->cores_mask =3D POWER8E_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; @@ -1156,7 +1155,6 @@ static void pnv_chip_power8_class_init(ObjectClass *k= lass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->chip_type =3D PNV_CHIP_POWER8; k->chip_cfam_id =3D 0x220ea04980000000ull; /* P8 Venice DD2.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; @@ -1180,7 +1178,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass= *klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->chip_type =3D PNV_CHIP_POWER8NVL; k->chip_cfam_id =3D 0x120d304980000000ull; /* P8 Naples DD1.0 */ k->cores_mask =3D POWER8_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p8; @@ -1360,7 +1357,6 @@ static void pnv_chip_power9_class_init(ObjectClass *k= lass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->chip_type =3D PNV_CHIP_POWER9; k->chip_cfam_id =3D 0x220d104900008000ull; /* P9 Nimbus DD2.0 */ k->cores_mask =3D POWER9_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p9; @@ -1449,7 +1445,6 @@ static void pnv_chip_power10_class_init(ObjectClass *= klass, void *data) DeviceClass *dc =3D DEVICE_CLASS(klass); PnvChipClass *k =3D PNV_CHIP_CLASS(klass); =20 - k->chip_type =3D PNV_CHIP_POWER10; k->chip_cfam_id =3D 0x120da04900008000ull; /* P10 DD1.0 (with NX) */ k->cores_mask =3D POWER10_CORE_MASK; k->core_pir =3D pnv_chip_core_pir_p10; diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 4972e93c2619..f78fd0dd967c 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -38,14 +38,6 @@ #define PNV_CHIP_GET_CLASS(obj) \ OBJECT_GET_CLASS(PnvChipClass, (obj), TYPE_PNV_CHIP) =20 -typedef enum PnvChipType { - PNV_CHIP_POWER8E, /* AKA Murano (default) */ - PNV_CHIP_POWER8, /* AKA Venice */ - PNV_CHIP_POWER8NVL, /* AKA Naples */ - PNV_CHIP_POWER9, /* AKA Nimbus */ - PNV_CHIP_POWER10, /* AKA TBD */ -} PnvChipType; - typedef struct PnvChip { /*< private >*/ SysBusDevice parent_obj; @@ -123,7 +115,6 @@ typedef struct PnvChipClass { SysBusDeviceClass parent_class; =20 /*< public >*/ - PnvChipType chip_type; uint64_t chip_cfam_id; uint64_t cores_mask; =20